LLVM 17.0.0git
PPCXCOFFObjectWriter.cpp
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1//===-- PPCXCOFFObjectWriter.cpp - PowerPC XCOFF Writer -------------------===//
2//
3//
4// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5// See https://llvm.org/LICENSE.txt for license information.
6// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7//
8//===----------------------------------------------------------------------===//
9
13#include "llvm/MC/MCFixup.h"
15#include "llvm/MC/MCValue.h"
17
18using namespace llvm;
19
20namespace {
21class PPCXCOFFObjectWriter : public MCXCOFFObjectTargetWriter {
22 static constexpr uint8_t SignBitMask = 0x80;
23
24public:
25 PPCXCOFFObjectWriter(bool Is64Bit);
26
27 std::pair<uint8_t, uint8_t>
29 bool IsPCRel) const override;
30};
31} // end anonymous namespace
32
33PPCXCOFFObjectWriter::PPCXCOFFObjectWriter(bool Is64Bit)
34 : MCXCOFFObjectTargetWriter(Is64Bit) {}
35
36std::unique_ptr<MCObjectTargetWriter>
38 return std::make_unique<PPCXCOFFObjectWriter>(Is64Bit);
39}
40
41std::pair<uint8_t, uint8_t> PPCXCOFFObjectWriter::getRelocTypeAndSignSize(
42 const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const {
43 const MCSymbolRefExpr::VariantKind Modifier =
44 Target.isAbsolute() ? MCSymbolRefExpr::VK_None
45 : Target.getSymA()->getKind();
46 // People from AIX OS team says AIX link editor does not care about
47 // the sign bit in the relocation entry "most" of the time.
48 // The system assembler seems to set the sign bit on relocation entry
49 // based on similar property of IsPCRel. So we will do the same here.
50 // TODO: More investigation on how assembler decides to set the sign
51 // bit, and we might want to match that.
52 const uint8_t EncodedSignednessIndicator = IsPCRel ? SignBitMask : 0u;
53
54 // The magic number we use in SignAndSize has a strong relationship with
55 // the corresponding MCFixupKind. In most cases, it's the MCFixupKind
56 // number - 1, because SignAndSize encodes the bit length being
57 // relocated minus 1.
58 switch ((unsigned)Fixup.getKind()) {
59 default:
60 report_fatal_error("Unimplemented fixup kind.");
62 const uint8_t SignAndSizeForHalf16 = EncodedSignednessIndicator | 15;
63 switch (Modifier) {
64 default:
65 report_fatal_error("Unsupported modifier for half16 fixup.");
67 return {XCOFF::RelocationType::R_TOC, SignAndSizeForHalf16};
69 return {XCOFF::RelocationType::R_TOCU, SignAndSizeForHalf16};
71 return {XCOFF::RelocationType::R_TOCL, SignAndSizeForHalf16};
72 }
73 } break;
76 if (IsPCRel)
77 report_fatal_error("Invalid PC-relative relocation.");
78 switch (Modifier) {
79 default:
80 llvm_unreachable("Unsupported Modifier");
82 return {XCOFF::RelocationType::R_TOC, 15};
84 return {XCOFF::RelocationType::R_TOCL, 15};
85 }
86 } break;
88 // Branches are 4 byte aligned, so the 24 bits we encode in
89 // the instruction actually represents a 26 bit offset.
90 return {XCOFF::RelocationType::R_RBR, EncodedSignednessIndicator | 25};
92 return {XCOFF::RelocationType::R_RBA, EncodedSignednessIndicator | 25};
93 case FK_Data_4:
94 case FK_Data_8:
95 const uint8_t SignAndSizeForFKData =
96 EncodedSignednessIndicator |
97 ((unsigned)Fixup.getKind() == FK_Data_4 ? 31 : 63);
98 switch (Modifier) {
99 default:
100 report_fatal_error("Unsupported modifier");
102 return {XCOFF::RelocationType::R_TLS, SignAndSizeForFKData};
104 return {XCOFF::RelocationType::R_TLSM, SignAndSizeForFKData};
106 return {XCOFF::RelocationType::R_POS, SignAndSizeForFKData};
107 }
108 }
109}
PowerPC TLS Dynamic Call Fixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
This represents an "assembler immediate".
Definition: MCValue.h:36
virtual std::pair< uint8_t, uint8_t > getRelocTypeAndSignSize(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const =0
Target - Wrapper for Target specific information.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_ppc_half16
A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
Definition: PPCFixupKinds.h:37
@ fixup_ppc_half16dq
A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.
Definition: PPCFixupKinds.h:56
@ fixup_ppc_half16ds
A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
Definition: PPCFixupKinds.h:41
@ fixup_ppc_br24abs
24-bit absolute relocation for direct branches like 'ba' and 'bla'.
Definition: PPCFixupKinds.h:30
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
std::unique_ptr< MCObjectTargetWriter > createPPCXCOFFObjectWriter(bool Is64Bit)
Construct a PPC XCOFF object writer.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25