LLVM  13.0.0git
VEAsmBackend.cpp
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1 //===-- VEAsmBackend.cpp - VE Assembler Backend ---------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "llvm/MC/MCAsmBackend.h"
13 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCObjectWriter.h"
17 #include "llvm/MC/MCValue.h"
20 
21 using namespace llvm;
22 
23 static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
24  switch (Kind) {
25  default:
26  llvm_unreachable("Unknown fixup kind!");
27  case FK_Data_1:
28  case FK_Data_2:
29  case FK_Data_4:
30  case FK_Data_8:
31  case FK_PCRel_1:
32  case FK_PCRel_2:
33  case FK_PCRel_4:
34  case FK_PCRel_8:
35  return Value;
36  case VE::fixup_ve_hi32:
43  return (Value >> 32) & 0xffffffff;
45  case VE::fixup_ve_lo32:
52  return Value & 0xffffffff;
53  }
54 }
55 
56 /// getFixupKindNumBytes - The number of bytes the fixup may change.
57 static unsigned getFixupKindNumBytes(unsigned Kind) {
58  switch (Kind) {
59  default:
60  llvm_unreachable("Unknown fixup kind!");
61  case FK_Data_1:
62  case FK_PCRel_1:
63  return 1;
64  case FK_Data_2:
65  case FK_PCRel_2:
66  return 2;
67  return 4;
68  case FK_Data_4:
69  case FK_PCRel_4:
71  case VE::fixup_ve_hi32:
72  case VE::fixup_ve_lo32:
85  return 4;
86  case FK_Data_8:
87  case FK_PCRel_8:
88  return 8;
89  }
90 }
91 
92 namespace {
93 class VEAsmBackend : public MCAsmBackend {
94 protected:
95  const Target &TheTarget;
96 
97 public:
98  VEAsmBackend(const Target &T) : MCAsmBackend(support::little), TheTarget(T) {}
99 
100  unsigned getNumFixupKinds() const override { return VE::NumTargetFixupKinds; }
101 
102  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
103  const static MCFixupKindInfo Infos[VE::NumTargetFixupKinds] = {
104  // name, offset, bits, flags
105  {"fixup_ve_reflong", 0, 32, 0},
106  {"fixup_ve_hi32", 0, 32, 0},
107  {"fixup_ve_lo32", 0, 32, 0},
108  {"fixup_ve_pc_hi32", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
109  {"fixup_ve_pc_lo32", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
110  {"fixup_ve_got_hi32", 0, 32, 0},
111  {"fixup_ve_got_lo32", 0, 32, 0},
112  {"fixup_ve_gotoff_hi32", 0, 32, 0},
113  {"fixup_ve_gotoff_lo32", 0, 32, 0},
114  {"fixup_ve_plt_hi32", 0, 32, 0},
115  {"fixup_ve_plt_lo32", 0, 32, 0},
116  {"fixup_ve_tls_gd_hi32", 0, 32, 0},
117  {"fixup_ve_tls_gd_lo32", 0, 32, 0},
118  {"fixup_ve_tpoff_hi32", 0, 32, 0},
119  {"fixup_ve_tpoff_lo32", 0, 32, 0},
120  };
121 
124 
125  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
126  "Invalid kind!");
127  return Infos[Kind - FirstTargetFixupKind];
128  }
129 
130  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
131  const MCValue &Target) override {
132  switch ((VE::Fixups)Fixup.getKind()) {
133  default:
134  return false;
139  return true;
140  }
141  }
142 
143  bool mayNeedRelaxation(const MCInst &Inst,
144  const MCSubtargetInfo &STI) const override {
145  // Not implemented yet. For example, if we have a branch with
146  // lager than SIMM32 immediate value, we want to relaxation such
147  // branch instructions.
148  return false;
149  }
150 
151  /// fixupNeedsRelaxation - Target specific predicate for whether a given
152  /// fixup requires the associated instruction to be relaxed.
153  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
154  const MCRelaxableFragment *DF,
155  const MCAsmLayout &Layout) const override {
156  // Not implemented yet. For example, if we have a branch with
157  // lager than SIMM32 immediate value, we want to relaxation such
158  // branch instructions.
159  return false;
160  }
161  void relaxInstruction(MCInst &Inst,
162  const MCSubtargetInfo &STI) const override {
163  // Aurora VE doesn't support relaxInstruction yet.
164  llvm_unreachable("relaxInstruction() should not be called");
165  }
166 
167  bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
168  if ((Count % 8) != 0)
169  return false;
170 
171  for (uint64_t i = 0; i < Count; i += 8)
172  support::endian::write<uint64_t>(OS, 0x7900000000000000ULL,
174 
175  return true;
176  }
177 };
178 
179 class ELFVEAsmBackend : public VEAsmBackend {
180  Triple::OSType OSType;
181 
182 public:
183  ELFVEAsmBackend(const Target &T, Triple::OSType OSType)
184  : VEAsmBackend(T), OSType(OSType) {}
185 
186  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
188  uint64_t Value, bool IsResolved,
189  const MCSubtargetInfo *STI) const override {
190  Value = adjustFixupValue(Fixup.getKind(), Value);
191  if (!Value)
192  return; // Doesn't change encoding.
193 
194  MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
195 
196  // Shift the value into position.
197  Value <<= Info.TargetOffset;
198 
199  unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
200  unsigned Offset = Fixup.getOffset();
201  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
202  // For each byte of the fragment that the fixup touches, mask in the bits
203  // from the fixup value. The Value has been "split up" into the
204  // appropriate bitfields above.
205  for (unsigned i = 0; i != NumBytes; ++i) {
206  unsigned Idx = Endian == support::little ? i : (NumBytes - 1) - i;
207  Data[Offset + Idx] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
208  }
209  }
210 
211  std::unique_ptr<MCObjectTargetWriter>
212  createObjectTargetWriter() const override {
213  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
214  return createVEELFObjectWriter(OSABI);
215  }
216 };
217 } // end anonymous namespace
218 
220  const MCSubtargetInfo &STI,
221  const MCRegisterInfo &MRI,
222  const MCTargetOptions &Options) {
223  return new ELFVEAsmBackend(T, STI.getTargetTriple().getOS());
224 }
llvm::VE::fixup_ve_reflong
@ fixup_ve_reflong
fixup_ve_reflong - 32-bit fixup corresponding to foo
Definition: VEFixupKinds.h:18
i
i
Definition: README.txt:29
llvm::VE::fixup_ve_plt_hi32
@ fixup_ve_plt_hi32
fixup_ve_plt_hi32/lo32
Definition: VEFixupKinds.h:45
llvm::VE::fixup_ve_pc_lo32
@ fixup_ve_pc_lo32
fixup_ve_pc_lo32 - 32-bit fixup corresponding to foo@pc_lo
Definition: VEFixupKinds.h:30
llvm
Definition: AllocatorList.h:23
llvm::MCRelaxableFragment
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:271
llvm::MCAsmBackend::getFixupKindInfo
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Definition: MCAsmBackend.cpp:74
llvm::FK_PCRel_8
@ FK_PCRel_8
A eight-byte pc relative fixup.
Definition: MCFixup.h:31
llvm::createVEELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createVEELFObjectWriter(uint8_t OSABI)
Definition: VEELFObjectWriter.cpp:133
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:125
llvm::FirstTargetFixupKind
@ FirstTargetFixupKind
Definition: MCFixup.h:55
llvm::VE::fixup_ve_pc_hi32
@ fixup_ve_pc_hi32
fixup_ve_pc_hi32 - 32-bit fixup corresponding to foo@pc_hi
Definition: VEFixupKinds.h:27
llvm::VE::fixup_ve_tls_gd_lo32
@ fixup_ve_tls_gd_lo32
Definition: VEFixupKinds.h:50
MCFixupKindInfo.h
T
#define T
Definition: Mips16ISelLowering.cpp:341
VEFixupKinds.h
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::createVEAsmBackend
MCAsmBackend * createVEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: VEAsmBackend.cpp:219
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Data
@ Data
Definition: SIMachineScheduler.h:56
llvm::FK_PCRel_1
@ FK_PCRel_1
A one-byte pc relative fixup.
Definition: MCFixup.h:28
llvm::VE::Fixups
Fixups
Definition: VEFixupKinds.h:16
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
MCAsmBackend.h
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
llvm::support::little
@ little
Definition: Endian.h:27
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
MCSubtargetInfo.h
llvm::VE::fixup_ve_lo32
@ fixup_ve_lo32
fixup_ve_lo32 - 32-bit fixup corresponding to foo@lo
Definition: VEFixupKinds.h:24
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
DF
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
VEMCTargetDesc.h
llvm::VE::NumTargetFixupKinds
@ NumTargetFixupKinds
Definition: VEFixupKinds.h:56
llvm::MCAssembler
Definition: MCAssembler.h:60
llvm::Triple::getOS
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:316
llvm::VE::fixup_ve_tls_gd_hi32
@ fixup_ve_tls_gd_hi32
fixups for Thread Local Storage
Definition: VEFixupKinds.h:49
MCELFObjectWriter.h
llvm::VE::fixup_ve_gotoff_lo32
@ fixup_ve_gotoff_lo32
fixup_ve_gotoff_lo32 - 32-bit fixup corresponding to foo@gotoff_lo
Definition: VEFixupKinds.h:42
getFixupKindNumBytes
static unsigned getFixupKindNumBytes(unsigned Kind)
getFixupKindNumBytes - The number of bytes the fixup may change.
Definition: VEAsmBackend.cpp:57
llvm::MCFixupKindInfo::FKF_IsPCRel
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Definition: MCFixupKindInfo.h:19
llvm::VE::fixup_ve_gotoff_hi32
@ fixup_ve_gotoff_hi32
fixup_ve_gotoff_hi32 - 32-bit fixup corresponding to foo@gotoff_hi
Definition: VEFixupKinds.h:39
llvm::VE::fixup_ve_hi32
@ fixup_ve_hi32
fixup_ve_hi32 - 32-bit fixup corresponding to foo@hi
Definition: VEFixupKinds.h:21
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCFixupKindInfo
Target independent information on a fixup kind.
Definition: MCFixupKindInfo.h:15
llvm::VE::fixup_ve_got_lo32
@ fixup_ve_got_lo32
fixup_ve_got_lo32 - 32-bit fixup corresponding to foo@got_lo
Definition: VEFixupKinds.h:36
llvm::FK_PCRel_2
@ FK_PCRel_2
A two-byte pc relative fixup.
Definition: MCFixup.h:29
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::FK_PCRel_4
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::VE::fixup_ve_got_hi32
@ fixup_ve_got_hi32
fixup_ve_got_hi32 - 32-bit fixup corresponding to foo@got_hi
Definition: VEFixupKinds.h:33
llvm::MCELFObjectTargetWriter::getOSABI
uint8_t getOSABI() const
Definition: MCELFObjectWriter.h:99
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:235
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
MCObjectWriter.h
llvm::Triple::OSType
OSType
Definition: Triple.h:164
llvm::VE::fixup_ve_tpoff_lo32
@ fixup_ve_tpoff_lo32
Definition: VEFixupKinds.h:52
EndianStream.h
llvm::MCAsmLayout
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::VE::fixup_ve_plt_lo32
@ fixup_ve_plt_lo32
Definition: VEFixupKinds.h:46
MCValue.h
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
support
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
Definition: README.txt:10
adjustFixupValue
static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value)
Definition: VEAsmBackend.cpp:23
llvm::VE::fixup_ve_tpoff_hi32
@ fixup_ve_tpoff_hi32
Definition: VEFixupKinds.h:51
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:37
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
TargetRegistry.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:81
llvm::Value
LLVM Value Representation.
Definition: Value.h:75