LLVM  14.0.0git
PPCInstPrinter.cpp
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1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an PPC MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
16 #include "PPCInstrInfo.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSymbol.h"
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "asm-printer"
29 
30 // FIXME: Once the integrated assembler supports full register names, tie this
31 // to the verbose-asm setting.
32 static cl::opt<bool>
33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34  cl::desc("Use full register names when printing assembly"));
35 
36 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
37 static cl::opt<bool>
38 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
39  cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
40 
41 // Prints full register names with percent symbol.
42 static cl::opt<bool>
43 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
44  cl::init(false),
45  cl::desc("Prints full register names with percent"));
46 
47 #define PRINT_ALIAS_INSTR
48 #include "PPCGenAsmWriter.inc"
49 
50 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51  const char *RegName = getRegisterName(RegNo);
52  OS << RegName;
53 }
54 
56  StringRef Annot, const MCSubtargetInfo &STI,
57  raw_ostream &O) {
58  // Customize printing of the addis instruction on AIX. When an operand is a
59  // symbol reference, the instruction syntax is changed to look like a load
60  // operation, i.e:
61  // Transform: addis $rD, $rA, $src --> addis $rD, $src($rA).
62  if (TT.isOSAIX() &&
63  (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
64  MI->getOperand(2).isExpr()) {
65  assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
66  "The first and the second operand of an addis instruction"
67  " should be registers.");
68 
69  assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&
70  "The third operand of an addis instruction should be a symbol "
71  "reference expression if it is an expression at all.");
72 
73  O << "\taddis ";
74  printOperand(MI, 0, STI, O);
75  O << ", ";
76  printOperand(MI, 2, STI, O);
77  O << "(";
78  printOperand(MI, 1, STI, O);
79  O << ")";
80  return;
81  }
82 
83  // Check if the last operand is an expression with the variant kind
84  // VK_PPC_PCREL_OPT. If this is the case then this is a linker optimization
85  // relocation and the .reloc directive needs to be added.
86  unsigned LastOp = MI->getNumOperands() - 1;
87  if (MI->getNumOperands() > 1) {
88  const MCOperand &Operand = MI->getOperand(LastOp);
89  if (Operand.isExpr()) {
90  const MCExpr *Expr = Operand.getExpr();
91  const MCSymbolRefExpr *SymExpr =
92  static_cast<const MCSymbolRefExpr *>(Expr);
93 
94  if (SymExpr && SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT) {
95  const MCSymbol &Symbol = SymExpr->getSymbol();
96  if (MI->getOpcode() == PPC::PLDpc) {
97  printInstruction(MI, Address, STI, O);
98  O << "\n";
99  Symbol.print(O, &MAI);
100  O << ":";
101  return;
102  } else {
103  O << "\t.reloc ";
104  Symbol.print(O, &MAI);
105  O << "-8,R_PPC64_PCREL_OPT,.-(";
106  Symbol.print(O, &MAI);
107  O << "-8)\n";
108  }
109  }
110  }
111  }
112 
113  // Check for slwi/srwi mnemonics.
114  if (MI->getOpcode() == PPC::RLWINM) {
115  unsigned char SH = MI->getOperand(2).getImm();
116  unsigned char MB = MI->getOperand(3).getImm();
117  unsigned char ME = MI->getOperand(4).getImm();
118  bool useSubstituteMnemonic = false;
119  if (SH <= 31 && MB == 0 && ME == (31-SH)) {
120  O << "\tslwi "; useSubstituteMnemonic = true;
121  }
122  if (SH <= 31 && MB == (32-SH) && ME == 31) {
123  O << "\tsrwi "; useSubstituteMnemonic = true;
124  SH = 32-SH;
125  }
126  if (useSubstituteMnemonic) {
127  printOperand(MI, 0, STI, O);
128  O << ", ";
129  printOperand(MI, 1, STI, O);
130  O << ", " << (unsigned int)SH;
131 
132  printAnnotation(O, Annot);
133  return;
134  }
135  }
136 
137  if (MI->getOpcode() == PPC::RLDICR ||
138  MI->getOpcode() == PPC::RLDICR_32) {
139  unsigned char SH = MI->getOperand(2).getImm();
140  unsigned char ME = MI->getOperand(3).getImm();
141  // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
142  if (63-SH == ME) {
143  O << "\tsldi ";
144  printOperand(MI, 0, STI, O);
145  O << ", ";
146  printOperand(MI, 1, STI, O);
147  O << ", " << (unsigned int)SH;
148  printAnnotation(O, Annot);
149  return;
150  }
151  }
152 
153  // dcbt[st] is printed manually here because:
154  // 1. The assembly syntax is different between embedded and server targets
155  // 2. We must print the short mnemonics for TH == 0 because the
156  // embedded/server syntax default will not be stable across assemblers
157  // The syntax for dcbt is:
158  // dcbt ra, rb, th [server]
159  // dcbt th, ra, rb [embedded]
160  // where th can be omitted when it is 0. dcbtst is the same.
161  // On AIX, only emit the extended mnemonics for dcbt and dcbtst if
162  // the "modern assembler" is available.
163  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
164  (!TT.isOSAIX() || STI.getFeatureBits()[PPC::FeatureModernAIXAs])) {
165  unsigned char TH = MI->getOperand(0).getImm();
166  O << "\tdcbt";
167  if (MI->getOpcode() == PPC::DCBTST)
168  O << "st";
169  if (TH == 16)
170  O << "t";
171  O << " ";
172 
173  bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
174  if (IsBookE && TH != 0 && TH != 16)
175  O << (unsigned int) TH << ", ";
176 
177  printOperand(MI, 1, STI, O);
178  O << ", ";
179  printOperand(MI, 2, STI, O);
180 
181  if (!IsBookE && TH != 0 && TH != 16)
182  O << ", " << (unsigned int) TH;
183 
184  printAnnotation(O, Annot);
185  return;
186  }
187 
188  if (MI->getOpcode() == PPC::DCBF) {
189  unsigned char L = MI->getOperand(0).getImm();
190  if (!L || L == 1 || L == 3 || L == 4 || L == 6) {
191  O << "\tdcb";
192  if (L != 6)
193  O << "f";
194  if (L == 1)
195  O << "l";
196  if (L == 3)
197  O << "lp";
198  if (L == 4)
199  O << "ps";
200  if (L == 6)
201  O << "stps";
202  O << " ";
203 
204  printOperand(MI, 1, STI, O);
205  O << ", ";
206  printOperand(MI, 2, STI, O);
207 
208  printAnnotation(O, Annot);
209  return;
210  }
211  }
212 
213  if (!printAliasInstr(MI, Address, STI, O))
214  printInstruction(MI, Address, STI, O);
215  printAnnotation(O, Annot);
216 }
217 
219  const MCSubtargetInfo &STI,
220  raw_ostream &O,
221  const char *Modifier) {
222  unsigned Code = MI->getOperand(OpNo).getImm();
223 
224  if (StringRef(Modifier) == "cc") {
225  switch ((PPC::Predicate)Code) {
226  case PPC::PRED_LT_MINUS:
227  case PPC::PRED_LT_PLUS:
228  case PPC::PRED_LT:
229  O << "lt";
230  return;
231  case PPC::PRED_LE_MINUS:
232  case PPC::PRED_LE_PLUS:
233  case PPC::PRED_LE:
234  O << "le";
235  return;
236  case PPC::PRED_EQ_MINUS:
237  case PPC::PRED_EQ_PLUS:
238  case PPC::PRED_EQ:
239  O << "eq";
240  return;
241  case PPC::PRED_GE_MINUS:
242  case PPC::PRED_GE_PLUS:
243  case PPC::PRED_GE:
244  O << "ge";
245  return;
246  case PPC::PRED_GT_MINUS:
247  case PPC::PRED_GT_PLUS:
248  case PPC::PRED_GT:
249  O << "gt";
250  return;
251  case PPC::PRED_NE_MINUS:
252  case PPC::PRED_NE_PLUS:
253  case PPC::PRED_NE:
254  O << "ne";
255  return;
256  case PPC::PRED_UN_MINUS:
257  case PPC::PRED_UN_PLUS:
258  case PPC::PRED_UN:
259  O << "un";
260  return;
261  case PPC::PRED_NU_MINUS:
262  case PPC::PRED_NU_PLUS:
263  case PPC::PRED_NU:
264  O << "nu";
265  return;
266  case PPC::PRED_BIT_SET:
267  case PPC::PRED_BIT_UNSET:
268  llvm_unreachable("Invalid use of bit predicate code");
269  }
270  llvm_unreachable("Invalid predicate code");
271  }
272 
273  if (StringRef(Modifier) == "pm") {
274  switch ((PPC::Predicate)Code) {
275  case PPC::PRED_LT:
276  case PPC::PRED_LE:
277  case PPC::PRED_EQ:
278  case PPC::PRED_GE:
279  case PPC::PRED_GT:
280  case PPC::PRED_NE:
281  case PPC::PRED_UN:
282  case PPC::PRED_NU:
283  return;
284  case PPC::PRED_LT_MINUS:
285  case PPC::PRED_LE_MINUS:
286  case PPC::PRED_EQ_MINUS:
287  case PPC::PRED_GE_MINUS:
288  case PPC::PRED_GT_MINUS:
289  case PPC::PRED_NE_MINUS:
290  case PPC::PRED_UN_MINUS:
291  case PPC::PRED_NU_MINUS:
292  O << "-";
293  return;
294  case PPC::PRED_LT_PLUS:
295  case PPC::PRED_LE_PLUS:
296  case PPC::PRED_EQ_PLUS:
297  case PPC::PRED_GE_PLUS:
298  case PPC::PRED_GT_PLUS:
299  case PPC::PRED_NE_PLUS:
300  case PPC::PRED_UN_PLUS:
301  case PPC::PRED_NU_PLUS:
302  O << "+";
303  return;
304  case PPC::PRED_BIT_SET:
305  case PPC::PRED_BIT_UNSET:
306  llvm_unreachable("Invalid use of bit predicate code");
307  }
308  llvm_unreachable("Invalid predicate code");
309  }
310 
311  assert(StringRef(Modifier) == "reg" &&
312  "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
313  printOperand(MI, OpNo + 1, STI, O);
314 }
315 
316 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
317  const MCSubtargetInfo &STI,
318  raw_ostream &O) {
319  unsigned Code = MI->getOperand(OpNo).getImm();
320  if (Code == 2)
321  O << "-";
322  else if (Code == 3)
323  O << "+";
324 }
325 
326 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
327  const MCSubtargetInfo &STI,
328  raw_ostream &O) {
329  unsigned int Value = MI->getOperand(OpNo).getImm();
330  assert(Value <= 1 && "Invalid u1imm argument!");
331  O << (unsigned int)Value;
332 }
333 
334 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
335  const MCSubtargetInfo &STI,
336  raw_ostream &O) {
337  unsigned int Value = MI->getOperand(OpNo).getImm();
338  assert(Value <= 3 && "Invalid u2imm argument!");
339  O << (unsigned int)Value;
340 }
341 
342 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
343  const MCSubtargetInfo &STI,
344  raw_ostream &O) {
345  unsigned int Value = MI->getOperand(OpNo).getImm();
346  assert(Value <= 8 && "Invalid u3imm argument!");
347  O << (unsigned int)Value;
348 }
349 
350 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
351  const MCSubtargetInfo &STI,
352  raw_ostream &O) {
353  unsigned int Value = MI->getOperand(OpNo).getImm();
354  assert(Value <= 15 && "Invalid u4imm argument!");
355  O << (unsigned int)Value;
356 }
357 
358 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
359  const MCSubtargetInfo &STI,
360  raw_ostream &O) {
361  int Value = MI->getOperand(OpNo).getImm();
362  Value = SignExtend32<5>(Value);
363  O << (int)Value;
364 }
365 
366 void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo,
367  const MCSubtargetInfo &STI,
368  raw_ostream &O) {
369  unsigned int Value = MI->getOperand(OpNo).getImm();
370  assert(Value == 0 && "Operand must be zero");
371  O << (unsigned int)Value;
372 }
373 
374 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
375  const MCSubtargetInfo &STI,
376  raw_ostream &O) {
377  unsigned int Value = MI->getOperand(OpNo).getImm();
378  assert(Value <= 31 && "Invalid u5imm argument!");
379  O << (unsigned int)Value;
380 }
381 
382 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
383  const MCSubtargetInfo &STI,
384  raw_ostream &O) {
385  unsigned int Value = MI->getOperand(OpNo).getImm();
386  assert(Value <= 63 && "Invalid u6imm argument!");
387  O << (unsigned int)Value;
388 }
389 
390 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
391  const MCSubtargetInfo &STI,
392  raw_ostream &O) {
393  unsigned int Value = MI->getOperand(OpNo).getImm();
394  assert(Value <= 127 && "Invalid u7imm argument!");
395  O << (unsigned int)Value;
396 }
397 
398 // Operands of BUILD_VECTOR are signed and we use this to print operands
399 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
400 // print as unsigned.
401 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
402  const MCSubtargetInfo &STI,
403  raw_ostream &O) {
404  unsigned char Value = MI->getOperand(OpNo).getImm();
405  O << (unsigned int)Value;
406 }
407 
408 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
409  const MCSubtargetInfo &STI,
410  raw_ostream &O) {
411  unsigned short Value = MI->getOperand(OpNo).getImm();
412  assert(Value <= 1023 && "Invalid u10imm argument!");
413  O << (unsigned short)Value;
414 }
415 
416 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
417  const MCSubtargetInfo &STI,
418  raw_ostream &O) {
419  unsigned short Value = MI->getOperand(OpNo).getImm();
420  assert(Value <= 4095 && "Invalid u12imm argument!");
421  O << (unsigned short)Value;
422 }
423 
424 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
425  const MCSubtargetInfo &STI,
426  raw_ostream &O) {
427  if (MI->getOperand(OpNo).isImm())
428  O << (short)MI->getOperand(OpNo).getImm();
429  else
430  printOperand(MI, OpNo, STI, O);
431 }
432 
433 void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
434  const MCSubtargetInfo &STI,
435  raw_ostream &O) {
436  if (MI->getOperand(OpNo).isImm()) {
437  long long Value = MI->getOperand(OpNo).getImm();
438  assert(isInt<34>(Value) && "Invalid s34imm argument!");
439  O << (long long)Value;
440  }
441  else
442  printOperand(MI, OpNo, STI, O);
443 }
444 
445 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
446  const MCSubtargetInfo &STI,
447  raw_ostream &O) {
448  if (MI->getOperand(OpNo).isImm())
449  O << (unsigned short)MI->getOperand(OpNo).getImm();
450  else
451  printOperand(MI, OpNo, STI, O);
452 }
453 
455  unsigned OpNo,
456  const MCSubtargetInfo &STI,
457  raw_ostream &O) {
458  if (!MI->getOperand(OpNo).isImm())
459  return printOperand(MI, OpNo, STI, O);
460  int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
462  uint64_t Target = Address + Imm;
463  if (!TT.isPPC64())
464  Target &= 0xffffffff;
465  O << formatHex(Target);
466  } else {
467  // Branches can take an immediate operand. This is used by the branch
468  // selection pass to print, for example `.+8` (for ELF) or `$+8` (for AIX)
469  // to express an eight byte displacement from the program counter.
470  if (!TT.isOSAIX())
471  O << ".";
472  else
473  O << "$";
474 
475  if (Imm >= 0)
476  O << "+";
477  O << Imm;
478  }
479 }
480 
482  const MCSubtargetInfo &STI,
483  raw_ostream &O) {
484  if (!MI->getOperand(OpNo).isImm())
485  return printOperand(MI, OpNo, STI, O);
486 
487  O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
488 }
489 
490 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
491  const MCSubtargetInfo &STI, raw_ostream &O) {
492  unsigned CCReg = MI->getOperand(OpNo).getReg();
493  unsigned RegNo;
494  switch (CCReg) {
495  default: llvm_unreachable("Unknown CR register");
496  case PPC::CR0: RegNo = 0; break;
497  case PPC::CR1: RegNo = 1; break;
498  case PPC::CR2: RegNo = 2; break;
499  case PPC::CR3: RegNo = 3; break;
500  case PPC::CR4: RegNo = 4; break;
501  case PPC::CR5: RegNo = 5; break;
502  case PPC::CR6: RegNo = 6; break;
503  case PPC::CR7: RegNo = 7; break;
504  }
505  O << (0x80 >> RegNo);
506 }
507 
508 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
509  const MCSubtargetInfo &STI,
510  raw_ostream &O) {
511  printS16ImmOperand(MI, OpNo, STI, O);
512  O << '(';
513  if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
514  O << "0";
515  else
516  printOperand(MI, OpNo + 1, STI, O);
517  O << ')';
518 }
519 
520 void PPCInstPrinter::printMemRegImmHash(const MCInst *MI, unsigned OpNo,
521  const MCSubtargetInfo &STI,
522  raw_ostream &O) {
523  O << MI->getOperand(OpNo).getImm();
524  O << '(';
525  printOperand(MI, OpNo + 1, STI, O);
526  O << ')';
527 }
528 
530  const MCSubtargetInfo &STI,
531  raw_ostream &O) {
532  printS34ImmOperand(MI, OpNo, STI, O);
533  O << '(';
534  printImmZeroOperand(MI, OpNo + 1, STI, O);
535  O << ')';
536 }
537 
538 void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo,
539  const MCSubtargetInfo &STI,
540  raw_ostream &O) {
541  printS34ImmOperand(MI, OpNo, STI, O);
542  O << '(';
543  printOperand(MI, OpNo + 1, STI, O);
544  O << ')';
545 }
546 
547 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
548  const MCSubtargetInfo &STI,
549  raw_ostream &O) {
550  // When used as the base register, r0 reads constant zero rather than
551  // the value contained in the register. For this reason, the darwin
552  // assembler requires that we print r0 as 0 (no r) when used as the base.
553  if (MI->getOperand(OpNo).getReg() == PPC::R0)
554  O << "0";
555  else
556  printOperand(MI, OpNo, STI, O);
557  O << ", ";
558  printOperand(MI, OpNo + 1, STI, O);
559 }
560 
561 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
562  const MCSubtargetInfo &STI, raw_ostream &O) {
563  // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
564  // come at the _end_ of the expression.
565  const MCOperand &Op = MI->getOperand(OpNo);
566  const MCSymbolRefExpr *RefExp = nullptr;
567  const MCConstantExpr *ConstExp = nullptr;
568  if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
569  RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
570  ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
571  } else
572  RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
573 
574  O << RefExp->getSymbol().getName();
575  // The variant kind VK_PPC_NOTOC needs to be handled as a special case
576  // because we do not want the assembly to print out the @notoc at the
577  // end like __tls_get_addr(x@tlsgd)@notoc. Instead we want it to look
578  // like __tls_get_addr@notoc(x@tlsgd).
579  if (RefExp->getKind() == MCSymbolRefExpr::VK_PPC_NOTOC)
580  O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
581  O << '(';
582  printOperand(MI, OpNo + 1, STI, O);
583  O << ')';
584  if (RefExp->getKind() != MCSymbolRefExpr::VK_None &&
586  O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
587  if (ConstExp != nullptr)
588  O << '+' << ConstExp->getValue();
589 }
590 
591 /// showRegistersWithPercentPrefix - Check if this register name should be
592 /// printed with a percentage symbol as prefix.
593 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
594  if (!FullRegNamesWithPercent || TT.getOS() == Triple::AIX)
595  return false;
596 
597  switch (RegName[0]) {
598  default:
599  return false;
600  case 'r':
601  case 'f':
602  case 'q':
603  case 'v':
604  case 'c':
605  return true;
606  }
607 }
608 
609 /// getVerboseConditionalRegName - This method expands the condition register
610 /// when requested explicitly or targetting Darwin.
611 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
612  unsigned RegEncoding)
613  const {
614  if (!FullRegNames)
615  return nullptr;
616  if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
617  return nullptr;
618  const char *CRBits[] = {
619  "lt", "gt", "eq", "un",
620  "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
621  "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
622  "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
623  "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
624  "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
625  "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
626  "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
627  };
628  return CRBits[RegEncoding];
629 }
630 
631 // showRegistersWithPrefix - This method determines whether registers
632 // should be number-only or include the prefix.
633 bool PPCInstPrinter::showRegistersWithPrefix() const {
635 }
636 
637 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
638  const MCSubtargetInfo &STI, raw_ostream &O) {
639  const MCOperand &Op = MI->getOperand(OpNo);
640  if (Op.isReg()) {
641  unsigned Reg = Op.getReg();
642  if (!ShowVSRNumsAsVR)
644  Reg, OpNo);
645 
646  const char *RegName;
647  RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
648  if (RegName == nullptr)
650  if (showRegistersWithPercentPrefix(RegName))
651  O << "%";
652  if (!showRegistersWithPrefix())
654 
655  O << RegName;
656  return;
657  }
658 
659  if (Op.isImm()) {
660  O << Op.getImm();
661  return;
662  }
663 
664  assert(Op.isExpr() && "unknown operand kind in printOperand");
665  Op.getExpr()->print(O, &MAI);
666 }
llvm::MCSymbolRefExpr::getKind
VariantKind getKind() const
Definition: MCExpr.h:401
llvm::PPCInstPrinter::printU6ImmOperand
void printU6ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:382
llvm::PPC::PRED_GT_PLUS
@ PRED_GT_PLUS
Definition: PPCPredicates.h:47
llvm::MCInstPrinter::MII
const MCInstrInfo & MII
Definition: MCInstPrinter.h:50
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::PPC::PRED_UN_PLUS
@ PRED_UN_PLUS
Definition: PPCPredicates.h:49
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::PPC::PRED_LT
@ PRED_LT
Definition: PPCPredicates.h:27
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::PPCInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo)
llvm::PPC::PRED_GE
@ PRED_GE
Definition: PPCPredicates.h:30
llvm::PPCInstPrinter::printU3ImmOperand
void printU3ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:342
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
ShowVSRNumsAsVR
static cl::opt< bool > ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false), cl::desc("Prints full register names with vs{31-63} as v{0-31}"))
llvm::PPCInstPrinter::printS16ImmOperand
void printS16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:424
llvm::PPC::PRED_LE_MINUS
@ PRED_LE_MINUS
Definition: PPCPredicates.h:36
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MCSymbolRefExpr::VK_PPC_PCREL_OPT
@ VK_PPC_PCREL_OPT
Definition: MCExpr.h:314
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Definition: MCRegisterInfo.h:553
llvm::PPCInstPrinter::printTLSCall
void printTLSCall(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:561
llvm::PPCInstPrinter::printImmZeroOperand
void printImmZeroOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:366
llvm::PPCInstPrinter::printU5ImmOperand
void printU5ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:374
llvm::PPC::PRED_NE_PLUS
@ PRED_NE_PLUS
Definition: PPCPredicates.h:48
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::PPC::PRED_GT
@ PRED_GT
Definition: PPCPredicates.h:31
llvm::MCBinaryExpr
Binary assembler expressions.
Definition: MCExpr.h:481
PPCMCTargetDesc.h
llvm::MCInstPrinter::PrintBranchImmAsAddress
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Definition: MCInstPrinter.h:69
llvm::PPC::PRED_UN_MINUS
@ PRED_UN_MINUS
Definition: PPCPredicates.h:41
PPCInstPrinter.h
llvm::MCInstPrinter::MRI
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:51
CommandLine.h
llvm::PPCInstPrinter::printU16ImmOperand
void printU16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:445
FullRegNamesWithPercent
static cl::opt< bool > FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden, cl::init(false), cl::desc("Prints full register names with percent"))
llvm::PPC::PRED_NU_MINUS
@ PRED_NU_MINUS
Definition: PPCPredicates.h:42
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::PPCInstPrinter::printU4ImmOperand
void printU4ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:350
MCInstrInfo.h
MCSymbol.h
MCInst.h
TargetOpcodes.h
llvm::PPCInstPrinter::printOperand
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:637
llvm::MCConstantExpr::getValue
int64_t getValue() const
Definition: MCExpr.h:173
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::PPC::PRED_BIT_SET
@ PRED_BIT_SET
Definition: PPCPredicates.h:57
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MCSymbolRefExpr::VK_PPC_NOTOC
@ VK_PPC_NOTOC
Definition: MCExpr.h:313
llvm::MCSymbolRefExpr::getSymbol
const MCSymbol & getSymbol() const
Definition: MCExpr.h:399
llvm::PPCInstPrinter::printU2ImmOperand
void printU2ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:334
llvm::PPCInstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition: PPCInstPrinter.cpp:55
llvm::PPCInstPrinter::printcrbitm
void printcrbitm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:490
llvm::PPC::PRED_LE_PLUS
@ PRED_LE_PLUS
Definition: PPCPredicates.h:44
llvm::PPC::PRED_GT_MINUS
@ PRED_GT_MINUS
Definition: PPCPredicates.h:39
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:198
llvm::PPC::PRED_BIT_UNSET
@ PRED_BIT_UNSET
Definition: PPCPredicates.h:58
llvm::PPC::PRED_LE
@ PRED_LE
Definition: PPCPredicates.h:28
llvm::Triple::isOSAIX
bool isOSAIX() const
Tests whether the OS is AIX.
Definition: Triple.h:630
llvm::MCInstPrinter::printAnnotation
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Definition: MCInstPrinter.cpp:49
llvm::PPCInstPrinter::printMemRegImm34
void printMemRegImm34(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:538
llvm::PPC::PRED_NU_PLUS
@ PRED_NU_PLUS
Definition: PPCPredicates.h:50
llvm::MCConstantExpr
Definition: MCExpr.h:144
llvm::PPCInstPrinter::printRegName
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
Definition: PPCInstPrinter.cpp:50
llvm::PPC::PRED_EQ
@ PRED_EQ
Definition: PPCPredicates.h:29
llvm::cl::opt< bool >
llvm::PPCInstPrinter::printBranchOperand
void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:454
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:206
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::PPC::PRED_GE_MINUS
@ PRED_GE_MINUS
Definition: PPCPredicates.h:38
llvm::PPCInstPrinter::printAliasInstr
bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS)
llvm::PPC::PRED_NE_MINUS
@ PRED_NE_MINUS
Definition: PPCPredicates.h:40
uint64_t
llvm::Triple::getOS
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:321
llvm::PPCInstPrinter::printS34ImmOperand
void printS34ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:433
PPCInstrInfo.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::MCInstPrinter::formatHex
format_object< int64_t > formatHex(int64_t Value) const
Definition: MCInstPrinter.cpp:197
MCRegisterInfo.h
llvm::PPC::PRED_GE_PLUS
@ PRED_GE_PLUS
Definition: PPCPredicates.h:46
llvm::HighlightColor::Address
@ Address
llvm::PPC::PRED_NE
@ PRED_NE
Definition: PPCPredicates.h:32
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::PPCInstPrinter::printU10ImmOperand
void printU10ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:408
llvm::PPCRegisterInfo::stripRegisterPrefix
static const char * stripRegisterPrefix(const char *RegName)
stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...
Definition: PPCRegisterInfo.h:168
llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
llvm::PPCInstPrinter::printU8ImmOperand
void printU8ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:401
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::PPCInstPrinter::printMemRegImm34PCRel
void printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:529
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::PPCInstPrinter::printMemRegImmHash
void printMemRegImmHash(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:520
llvm::PPC::PRED_NU
@ PRED_NU
Definition: PPCPredicates.h:34
llvm::PPCInstPrinter::printATBitsAsHint
void printATBitsAsHint(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:316
llvm::PPCInstPrinter::printInstruction
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
llvm::PPCInstPrinter::printU1ImmOperand
void printU1ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:326
llvm::PPC::PRED_EQ_PLUS
@ PRED_EQ_PLUS
Definition: PPCPredicates.h:45
llvm::PPCInstrInfo::getRegNumForOperand
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
Definition: PPCInstrInfo.h:662
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::PPC::PRED_LT_PLUS
@ PRED_LT_PLUS
Definition: PPCPredicates.h:43
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::Triple::AIX
@ AIX
Definition: Triple.h:192
FullRegNames
static cl::opt< bool > FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false), cl::desc("Use full register names when printing assembly"))
llvm::PPCInstPrinter::printPredicateOperand
void printPredicateOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier=nullptr)
Definition: PPCInstPrinter.cpp:218
llvm::MCSymbolRefExpr::getVariantKindName
static StringRef getVariantKindName(VariantKind Kind)
Definition: MCExpr.cpp:221
llvm::PPC::PRED_EQ_MINUS
@ PRED_EQ_MINUS
Definition: PPCPredicates.h:37
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::PPC::PRED_UN
@ PRED_UN
Definition: PPCPredicates.h:33
llvm::PPCInstPrinter::printS5ImmOperand
void printS5ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:358
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::MCInstPrinter::MAI
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:49
llvm::PPCInstPrinter::printMemRegImm
void printMemRegImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:508
llvm::PPCInstPrinter::printU7ImmOperand
void printU7ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:390
llvm::PPC::PRED_LT_MINUS
@ PRED_LT_MINUS
Definition: PPCPredicates.h:35
RegName
#define RegName(no)
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::cl::desc
Definition: CommandLine.h:412
raw_ostream.h
PPCPredicates.h
MCExpr.h
llvm::Triple::isPPC64
bool isPPC64() const
Tests whether the target is 64-bit PowerPC (little and big endian).
Definition: Triple.h:789
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::PPCInstPrinter::printAbsBranchOperand
void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:481
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::PPCInstPrinter::printMemRegReg
void printMemRegReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:547
llvm::PPCInstPrinter::printU12ImmOperand
void printU12ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: PPCInstPrinter.cpp:416