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28 #define DEBUG_TYPE "asm-printer"
34 cl::desc(
"Use full register names when printing assembly"));
39 cl::desc(
"Prints full register names with vs{31-63} as v{0-31}"));
45 cl::desc(
"Prints full register names with percent"));
47 #define PRINT_ALIAS_INSTR
48 #include "PPCGenAsmWriter.inc"
63 (
MI->getOpcode() == PPC::ADDIS8 ||
MI->getOpcode() == PPC::ADDIS) &&
64 MI->getOperand(2).isExpr()) {
65 assert((
MI->getOperand(0).isReg() &&
MI->getOperand(1).isReg()) &&
66 "The first and the second operand of an addis instruction"
67 " should be registers.");
69 assert(isa<MCSymbolRefExpr>(
MI->getOperand(2).getExpr()) &&
70 "The third operand of an addis instruction should be a symbol "
71 "reference expression if it is an expression at all.");
86 unsigned LastOp =
MI->getNumOperands() - 1;
87 if (
MI->getNumOperands() > 1) {
96 if (
MI->getOpcode() == PPC::PLDpc) {
105 O <<
"-8,R_PPC64_PCREL_OPT,.-(";
114 if (
MI->getOpcode() == PPC::RLWINM) {
115 unsigned char SH =
MI->getOperand(2).getImm();
116 unsigned char MB =
MI->getOperand(3).getImm();
117 unsigned char ME =
MI->getOperand(4).getImm();
118 bool useSubstituteMnemonic =
false;
119 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
120 O <<
"\tslwi "; useSubstituteMnemonic =
true;
122 if (SH <= 31 && MB == (32-SH) && ME == 31) {
123 O <<
"\tsrwi "; useSubstituteMnemonic =
true;
126 if (useSubstituteMnemonic) {
130 O <<
", " << (
unsigned int)SH;
137 if (
MI->getOpcode() == PPC::RLDICR ||
138 MI->getOpcode() == PPC::RLDICR_32) {
139 unsigned char SH =
MI->getOperand(2).getImm();
140 unsigned char ME =
MI->getOperand(3).getImm();
147 O <<
", " << (
unsigned int)SH;
163 if ((
MI->getOpcode() == PPC::DCBT ||
MI->getOpcode() == PPC::DCBTST) &&
165 unsigned char TH =
MI->getOperand(0).getImm();
167 if (
MI->getOpcode() == PPC::DCBTST)
174 if (IsBookE && TH != 0 && TH != 16)
175 O << (
unsigned int) TH <<
", ";
181 if (!IsBookE && TH != 0 && TH != 16)
182 O <<
", " << (
unsigned int) TH;
188 if (
MI->getOpcode() == PPC::DCBF) {
189 unsigned char L =
MI->getOperand(0).getImm();
190 if (!L || L == 1 || L == 3 || L == 4 || L == 6) {
221 const char *Modifier) {
222 unsigned Code =
MI->getOperand(OpNo).getImm();
312 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
319 unsigned Code =
MI->getOperand(OpNo).getImm();
329 unsigned int Value =
MI->getOperand(OpNo).getImm();
337 unsigned int Value =
MI->getOperand(OpNo).getImm();
345 unsigned int Value =
MI->getOperand(OpNo).getImm();
353 unsigned int Value =
MI->getOperand(OpNo).getImm();
361 int Value =
MI->getOperand(OpNo).getImm();
369 unsigned int Value =
MI->getOperand(OpNo).getImm();
377 unsigned int Value =
MI->getOperand(OpNo).getImm();
385 unsigned int Value =
MI->getOperand(OpNo).getImm();
393 unsigned int Value =
MI->getOperand(OpNo).getImm();
404 unsigned char Value =
MI->getOperand(OpNo).getImm();
411 unsigned short Value =
MI->getOperand(OpNo).getImm();
412 assert(
Value <= 1023 &&
"Invalid u10imm argument!");
413 O << (
unsigned short)
Value;
419 unsigned short Value =
MI->getOperand(OpNo).getImm();
420 assert(
Value <= 4095 &&
"Invalid u12imm argument!");
421 O << (
unsigned short)
Value;
427 if (
MI->getOperand(OpNo).isImm())
428 O << (short)
MI->getOperand(OpNo).getImm();
436 if (
MI->getOperand(OpNo).isImm()) {
437 long long Value =
MI->getOperand(OpNo).getImm();
438 assert(isInt<34>(
Value) &&
"Invalid s34imm argument!");
448 if (
MI->getOperand(OpNo).isImm())
449 O << (
unsigned short)
MI->getOperand(OpNo).getImm();
458 if (!
MI->getOperand(OpNo).isImm())
460 int32_t Imm = SignExtend32<32>((
unsigned)
MI->getOperand(OpNo).getImm() << 2);
484 if (!
MI->getOperand(OpNo).isImm())
487 O << SignExtend32<32>((
unsigned)
MI->getOperand(OpNo).getImm() << 2);
492 unsigned CCReg =
MI->getOperand(OpNo).getReg();
496 case PPC::CR0: RegNo = 0;
break;
497 case PPC::CR1: RegNo = 1;
break;
498 case PPC::CR2: RegNo = 2;
break;
499 case PPC::CR3: RegNo = 3;
break;
500 case PPC::CR4: RegNo = 4;
break;
501 case PPC::CR5: RegNo = 5;
break;
502 case PPC::CR6: RegNo = 6;
break;
503 case PPC::CR7: RegNo = 7;
break;
505 O << (0x80 >> RegNo);
513 if (
MI->getOperand(OpNo+1).getReg() == PPC::R0)
523 O <<
MI->getOperand(OpNo).getImm();
553 if (
MI->getOperand(OpNo).getReg() == PPC::R0)
568 if (
const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(
Op.getExpr())) {
569 RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
570 ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
572 RefExp = cast<MCSymbolRefExpr>(
Op.getExpr());
587 if (ConstExp !=
nullptr)
593 bool PPCInstPrinter::showRegistersWithPercentPrefix(
const char *
RegName)
const {
611 const char *PPCInstPrinter::getVerboseConditionRegName(
unsigned RegNum,
612 unsigned RegEncoding)
616 if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
618 const char *CRBits[] = {
619 "lt",
"gt",
"eq",
"un",
620 "4*cr1+lt",
"4*cr1+gt",
"4*cr1+eq",
"4*cr1+un",
621 "4*cr2+lt",
"4*cr2+gt",
"4*cr2+eq",
"4*cr2+un",
622 "4*cr3+lt",
"4*cr3+gt",
"4*cr3+eq",
"4*cr3+un",
623 "4*cr4+lt",
"4*cr4+gt",
"4*cr4+eq",
"4*cr4+un",
624 "4*cr5+lt",
"4*cr5+gt",
"4*cr5+eq",
"4*cr5+un",
625 "4*cr6+lt",
"4*cr6+gt",
"4*cr6+eq",
"4*cr6+un",
626 "4*cr7+lt",
"4*cr7+gt",
"4*cr7+eq",
"4*cr7+un"
628 return CRBits[RegEncoding];
633 bool PPCInstPrinter::showRegistersWithPrefix()
const {
641 unsigned Reg =
Op.getReg();
650 if (showRegistersWithPercentPrefix(
RegName))
652 if (!showRegistersWithPrefix())
664 assert(
Op.isExpr() &&
"unknown operand kind in printOperand");
665 Op.getExpr()->print(
O, &
MAI);
VariantKind getKind() const
void printU6ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
This is an optimization pass for GlobalISel generic memory operations.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static const char * getRegisterName(unsigned RegNo)
void printU3ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Target - Wrapper for Target specific information.
static cl::opt< bool > ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false), cl::desc("Prints full register names with vs{31-63} as v{0-31}"))
void printS16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Reg
All possible values of the reg field in the ModR/M byte.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
void printTLSCall(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmZeroOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU5ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Instances of this class represent a single low-level machine instruction.
Binary assembler expressions.
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
const MCRegisterInfo & MRI
void printU16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static cl::opt< bool > FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden, cl::init(false), cl::desc("Prints full register names with percent"))
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
void printU4ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
const FeatureBitset & getFeatureBits() const
This class implements an extremely fast bulk output stream that can only output to a stream.
const MCSymbol & getSymbol() const
void printU2ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printcrbitm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
StringRef getName() const
getName - Get the symbol name.
bool isOSAIX() const
Tests whether the OS is AIX.
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printMemRegImm34(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS)
OSType getOS() const
Get the parsed operating system type of this triple.
void printS34ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
initializer< Ty > init(const Ty &Val)
format_object< int64_t > formatHex(int64_t Value) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printU10ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * stripRegisterPrefix(const char *RegName)
stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...
Represent a reference to a symbol from inside an expression.
void printU8ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
StringRef - Represent a constant reference to a string, i.e.
void printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printMemRegImmHash(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printATBitsAsHint(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printU1ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
const MCExpr * getExpr() const
static cl::opt< bool > FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false), cl::desc("Use full register names when printing assembly"))
void printPredicateOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier=nullptr)
static StringRef getVariantKindName(VariantKind Kind)
void printS5ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemRegImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU7ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Instances of this class represent operands of the MCInst class.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
bool isPPC64() const
Tests whether the target is 64-bit PowerPC (little and big endian).
Generic base class for all target subtargets.
void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
LLVM Value Representation.
Base class for the full range of assembler expressions which are needed for parsing.
void printMemRegReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU12ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)