LLVM  12.0.0git
InstrEmitter.h
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1 //===- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG -*- C++ -*--==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This declares the Emit routines for the SelectionDAG class, which creates
10 // MachineInstrs based on the decisions of the SelectionDAG instruction
11 // selection.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H
16 #define LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H
17 
18 #include "llvm/ADT/DenseMap.h"
21 
22 namespace llvm {
23 
24 class MachineInstrBuilder;
25 class MCInstrDesc;
26 class SDDbgLabel;
27 class SDDbgValue;
28 class TargetLowering;
29 
31  MachineFunction *MF;
33  const TargetInstrInfo *TII;
34  const TargetRegisterInfo *TRI;
35  const TargetLowering *TLI;
36 
39 
40  /// Should we try to produce DBG_INSTR_REF instructions?
41  bool EmitDebugInstrRefs;
42 
43  /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
44  /// implicit physical register output.
45  void EmitCopyFromReg(SDNode *Node, unsigned ResNo,
46  bool IsClone, bool IsCloned,
47  Register SrcReg,
48  DenseMap<SDValue, Register> &VRBaseMap);
49 
50  void CreateVirtualRegisters(SDNode *Node,
52  const MCInstrDesc &II,
53  bool IsClone, bool IsCloned,
54  DenseMap<SDValue, Register> &VRBaseMap);
55 
56  /// getVR - Return the virtual register corresponding to the specified result
57  /// of the specified node.
58  Register getVR(SDValue Op,
59  DenseMap<SDValue, Register> &VRBaseMap);
60 
61  /// AddRegisterOperand - Add the specified register as an operand to the
62  /// specified machine instr. Insert register copies if the register is
63  /// not in the required register class.
64  void AddRegisterOperand(MachineInstrBuilder &MIB,
65  SDValue Op,
66  unsigned IIOpNum,
67  const MCInstrDesc *II,
68  DenseMap<SDValue, Register> &VRBaseMap,
69  bool IsDebug, bool IsClone, bool IsCloned);
70 
71  /// AddOperand - Add the specified operand to the specified machine instr. II
72  /// specifies the instruction information for the node, and IIOpNum is the
73  /// operand number (in the II) that we are adding. IIOpNum and II are used for
74  /// assertions only.
75  void AddOperand(MachineInstrBuilder &MIB,
76  SDValue Op,
77  unsigned IIOpNum,
78  const MCInstrDesc *II,
79  DenseMap<SDValue, Register> &VRBaseMap,
80  bool IsDebug, bool IsClone, bool IsCloned);
81 
82  /// ConstrainForSubReg - Try to constrain VReg to a register class that
83  /// supports SubIdx sub-registers. Emit a copy if that isn't possible.
84  /// Return the virtual register to use.
85  Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
86  bool isDivergent, const DebugLoc &DL);
87 
88  /// EmitSubregNode - Generate machine code for subreg nodes.
89  ///
90  void EmitSubregNode(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
91  bool IsClone, bool IsCloned);
92 
93  /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
94  /// COPY_TO_REGCLASS is just a normal copy, except that the destination
95  /// register is constrained to be in a particular register class.
96  ///
97  void EmitCopyToRegClassNode(SDNode *Node,
98  DenseMap<SDValue, Register> &VRBaseMap);
99 
100  /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
101  ///
102  void EmitRegSequence(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
103  bool IsClone, bool IsCloned);
104 public:
105  /// CountResults - The results of target nodes have register or immediate
106  /// operands first, then an optional chain, and optional flag operands
107  /// (which do not go into the machine instrs.)
108  static unsigned CountResults(SDNode *Node);
109 
110  /// EmitDbgValue - Generate machine instruction for a dbg_value node.
111  ///
112  MachineInstr *EmitDbgValue(SDDbgValue *SD,
113  DenseMap<SDValue, Register> &VRBaseMap);
114 
115  /// Attempt to emit a dbg_value as a DBG_INSTR_REF. May fail and return
116  /// nullptr, in which case we fall back to plain EmitDbgValue.
117  MachineInstr *EmitDbgInstrRef(SDDbgValue *SD,
118  DenseMap<SDValue, Register> &VRBaseMap);
119 
120  /// Generate machine instruction for a dbg_label node.
121  MachineInstr *EmitDbgLabel(SDDbgLabel *SD);
122 
123  /// EmitNode - Generate machine code for a node and needed dependencies.
124  ///
125  void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
126  DenseMap<SDValue, Register> &VRBaseMap) {
127  if (Node->isMachineOpcode())
128  EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap);
129  else
130  EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap);
131  }
132 
133  /// getBlock - Return the current basic block.
135 
136  /// getInsertPos - Return the current insertion position.
138 
139  /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
140  /// at the given position in the given block.
142  MachineBasicBlock::iterator insertpos);
143 
144 private:
145  void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
146  DenseMap<SDValue, Register> &VRBaseMap);
147  void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
148  DenseMap<SDValue, Register> &VRBaseMap);
149 };
150 
151 }
152 
153 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:187
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
MachineBasicBlock * getBlock()
getBlock - Return the current basic block.
Definition: InstrEmitter.h:134
MachineBasicBlock & MBB
const HexagonInstrInfo * TII
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned const MachineRegisterInfo * MRI
void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, DenseMap< SDValue, Register > &VRBaseMap)
EmitNode - Generate machine code for a node and needed dependencies.
Definition: InstrEmitter.h:125
Machine Value Type.
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library...
Definition: Compiler.h:130
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
Represents one node in the SelectionDAG.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:62
Holds the information from a dbg_label node through SDISel.
MachineBasicBlock::iterator getInsertPos()
getInsertPos - Return the current insertion position.
Definition: InstrEmitter.h:137
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:66
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Holds the information from a dbg_value node through SDISel.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL