41 unsigned Opc =
MI->getOpcode();
43 case TargetOpcode::COPY: {
46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg());
47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg());
51 if (
TRI.getMinimalPhysRegClass(DstR.
Reg) !=
52 TRI.getMinimalPhysRegClass(SrcR.
Reg))
54 EM.insert(std::make_pair(DstR, SrcR));
57 case TargetOpcode::REG_SEQUENCE:
64 CopyMap.insert(std::make_pair(SA.
Id, EM));
76 if (interpretAsCopy(SA.
Addr->getCode(), EM))
83 Changed |= scanBlock(
I->getBlock());
95 if (
NodeId RD =
RA.Addr->getReachingDef())
101bool CopyPropagation::run() {
102 scanBlock(&DFG.getMF().front());
105 dbgs() <<
"Copies:\n";
109 for (
auto J : CopyMap[
I])
116 bool Changed =
false;
118 bool HasLimit =
CpLimit.getNumOccurrences() > 0;
121 auto MinPhysReg = [
this] (
RegisterRef RR) ->
unsigned {
127 if (RR.Mask ==
TRI.getSubRegIndexLaneMask(S.getSubRegIndex()))
128 return S.getSubReg();
139 auto FS = CopyMap.find(SA.
Id);
140 if (FS == CopyMap.end())
146 auto FR = EM.find(DR);
153 NodeId AtCopy = getLocalReachingDef(SR, SA);
155 for (
NodeId N = DA.Addr->getReachedUse(), NextN;
N;
N = NextN) {
161 if (UA.Addr->getRegRef(DFG) != DR)
166 NodeId AtUse = getLocalReachingDef(SR, IA);
179 unsigned NewReg = MinPhysReg(SR);
182 DFG.unlinkUse(UA,
false);
184 UA.Addr->linkToDef(UA.Id, DFG.addr<
DefNode*>(AtCopy));
186 UA.Addr->setReachingDef(0);
187 UA.Addr->setSibling(0);
197 auto FC = CopyMap.find(IA.Id);
198 if (FC != CopyMap.end()) {
200 auto &M = FC->second;
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const TargetRegisterInfo * TRI
static cl::opt< unsigned > CpLimit("rdf-cp-limit", cl::init(0), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
Base class for the actual dominator tree node.
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices.
bool isValid() const
Returns true if this iterator is not yet at the end.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const LaneBitmask LaneMask
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
std::map< RegisterRef, RegisterRef > EqualityMap
NodeId getSibling() const