36#define DEBUG_TYPE "regalloc"
38STATISTIC(NumNewQueued,
"Number of new live ranges queued");
55void RegAllocBase::anchor() {}
71void RegAllocBase::seedLiveRegs() {
107 <<
':' << *VirtReg <<
" w=" << VirtReg->weight() <<
'\n');
111 VirtRegVec SplitVRegs;
114 if (AvailablePhysReg == ~0u) {
123 if (
MI->isInlineAsm())
129 if (AllocOrder.
empty())
131 else if (
MI &&
MI->isInlineAsm()) {
132 MI->emitError(
"inline assembly requires more registers than available");
135 MI->getParent()->getParent()->getMMI().getModule()->getContext();
143 }
else if (AvailablePhysReg)
152 assert(SplitVirtReg->
empty() &&
"Non-empty but used interval");
153 LLVM_DEBUG(
dbgs() <<
"not queueing unused " << *SplitVirtReg <<
'\n');
158 LLVM_DEBUG(
dbgs() <<
"queuing new interval: " << *SplitVirtReg <<
"\n");
160 "expect split value in virtual register");
171 DeadInst->eraseFromParent();
179 assert(Reg.isVirtual() &&
"Can only enqueue virtual registers");
190 <<
" in skipped register class\n");
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static cl::opt< bool, true > VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled), cl::Hidden, cl::desc("Verify during register allocation"))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
const T & front() const
front - Get the first element.
bool empty() const
empty - Check if the array is empty.
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasInterval(Register Reg) const
void RemoveMachineInstrFromMaps(MachineInstr &MI)
LiveInterval & getInterval(Register Reg)
void removeInterval(Register Reg)
Interval removal.
void invalidateVirtRegs()
Invalidate cached interference queries after modifying virtual register live ranges.
void assign(const LiveInterval &VirtReg, MCRegister PhysReg)
Assign VirtReg to PhysReg.
Wrapper class representing physical registers. Should be passed by value.
Representation of each machine instruction.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
reg_instr_iterator reg_instr_begin(Register RegNo) const
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
static reg_instr_iterator reg_instr_end()
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
virtual void aboutToRemoveInterval(const LiveInterval &LI)
Method called when the allocator is about to remove a LiveInterval.
virtual MCRegister selectOrSplit(const LiveInterval &VirtReg, SmallVectorImpl< Register > &splitLVRs)=0
void enqueue(const LiveInterval *LI)
enqueue - Add VirtReg to the priority queue of unassigned registers.
void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat)
SmallPtrSet< MachineInstr *, 32 > DeadRemats
Inst which is a def of an original reg and whose defs are already all dead after remat is saved in De...
virtual Spiller & spiller()=0
const TargetRegisterInfo * TRI
static const char TimerGroupName[]
static const char TimerGroupDescription[]
virtual const LiveInterval * dequeue()=0
dequeue - Return the next unassigned register, or NULL.
virtual void postOptimization()
RegisterClassInfo RegClassInfo
MachineRegisterInfo * MRI
virtual void enqueueImpl(const LiveInterval *LI)=0
enqueue - Add VirtReg to the priority queue of unassigned registers.
static bool VerifyEnabled
VerifyEnabled - True when -verify-regalloc is given.
const RegClassFilterFunc ShouldAllocateClass
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
virtual void postOptimization()
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
MachineRegisterInfo & getRegInfo() const
MachineFunction & getMachineFunction() const
bool hasPhys(Register virtReg) const
returns true if the specified virtual register is mapped to a physical register
const TargetRegisterInfo & getTargetRegInfo() const
void assignVirt2Phys(Register virtReg, MCPhysReg physReg)
creates a mapping for the specified virtual register to the specified physical register
LocationClass< Ty > location(Ty &L)
This is an optimization pass for GlobalISel generic memory operations.
bool TimePassesIsEnabled
If the user specifies the -time-passes argument on an LLVM tool command line then the value of this b...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This class is basically a combination of TimeRegion and Timer.