LLVM 20.0.0git
NVVMIntrinsicUtils.h
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1//===--- NVVMIntrinsicUtils.h -----------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file contains the definitions of the enumerations and flags
11/// associated with NVVM Intrinsics, along with some helper functions.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_IR_NVVMINTRINSICUTILS_H
16#define LLVM_IR_NVVMINTRINSICUTILS_H
17
18#include <stdint.h>
19
20#include "llvm/ADT/APFloat.h"
21#include "llvm/IR/Intrinsics.h"
22#include "llvm/IR/IntrinsicsNVPTX.h"
23
24namespace llvm {
25namespace nvvm {
26
27// Reduction Ops supported with TMA Copy from Shared
28// to Global Memory for the "cp.reduce.async.bulk.tensor.*"
29// family of PTX instructions.
30enum class TMAReductionOp : uint8_t {
31 ADD = 0,
32 MIN = 1,
33 MAX = 2,
34 INC = 3,
35 DEC = 4,
36 AND = 5,
37 OR = 6,
38 XOR = 7,
39};
40
41inline bool IntrinsicShouldFTZ(Intrinsic::ID IntrinsicID) {
42 switch (IntrinsicID) {
43 // Float to i32 / i64 conversion intrinsics:
44 case Intrinsic::nvvm_f2i_rm_ftz:
45 case Intrinsic::nvvm_f2i_rn_ftz:
46 case Intrinsic::nvvm_f2i_rp_ftz:
47 case Intrinsic::nvvm_f2i_rz_ftz:
48
49 case Intrinsic::nvvm_f2ui_rm_ftz:
50 case Intrinsic::nvvm_f2ui_rn_ftz:
51 case Intrinsic::nvvm_f2ui_rp_ftz:
52 case Intrinsic::nvvm_f2ui_rz_ftz:
53
54 case Intrinsic::nvvm_f2ll_rm_ftz:
55 case Intrinsic::nvvm_f2ll_rn_ftz:
56 case Intrinsic::nvvm_f2ll_rp_ftz:
57 case Intrinsic::nvvm_f2ll_rz_ftz:
58
59 case Intrinsic::nvvm_f2ull_rm_ftz:
60 case Intrinsic::nvvm_f2ull_rn_ftz:
61 case Intrinsic::nvvm_f2ull_rp_ftz:
62 case Intrinsic::nvvm_f2ull_rz_ftz:
63 return true;
64 }
65 return false;
66}
67
69 switch (IntrinsicID) {
70 // f2i
71 case Intrinsic::nvvm_f2i_rm:
72 case Intrinsic::nvvm_f2i_rm_ftz:
73 case Intrinsic::nvvm_f2i_rn:
74 case Intrinsic::nvvm_f2i_rn_ftz:
75 case Intrinsic::nvvm_f2i_rp:
76 case Intrinsic::nvvm_f2i_rp_ftz:
77 case Intrinsic::nvvm_f2i_rz:
78 case Intrinsic::nvvm_f2i_rz_ftz:
79 // d2i
80 case Intrinsic::nvvm_d2i_rm:
81 case Intrinsic::nvvm_d2i_rn:
82 case Intrinsic::nvvm_d2i_rp:
83 case Intrinsic::nvvm_d2i_rz:
84 // f2ll
85 case Intrinsic::nvvm_f2ll_rm:
86 case Intrinsic::nvvm_f2ll_rm_ftz:
87 case Intrinsic::nvvm_f2ll_rn:
88 case Intrinsic::nvvm_f2ll_rn_ftz:
89 case Intrinsic::nvvm_f2ll_rp:
90 case Intrinsic::nvvm_f2ll_rp_ftz:
91 case Intrinsic::nvvm_f2ll_rz:
92 case Intrinsic::nvvm_f2ll_rz_ftz:
93 // d2ll
94 case Intrinsic::nvvm_d2ll_rm:
95 case Intrinsic::nvvm_d2ll_rn:
96 case Intrinsic::nvvm_d2ll_rp:
97 case Intrinsic::nvvm_d2ll_rz:
98 return true;
99 }
100 return false;
101}
102
105 switch (IntrinsicID) {
106 // RM:
107 case Intrinsic::nvvm_f2i_rm:
108 case Intrinsic::nvvm_f2ui_rm:
109 case Intrinsic::nvvm_f2i_rm_ftz:
110 case Intrinsic::nvvm_f2ui_rm_ftz:
111 case Intrinsic::nvvm_d2i_rm:
112 case Intrinsic::nvvm_d2ui_rm:
113
114 case Intrinsic::nvvm_f2ll_rm:
115 case Intrinsic::nvvm_f2ull_rm:
116 case Intrinsic::nvvm_f2ll_rm_ftz:
117 case Intrinsic::nvvm_f2ull_rm_ftz:
118 case Intrinsic::nvvm_d2ll_rm:
119 case Intrinsic::nvvm_d2ull_rm:
121
122 // RN:
123 case Intrinsic::nvvm_f2i_rn:
124 case Intrinsic::nvvm_f2ui_rn:
125 case Intrinsic::nvvm_f2i_rn_ftz:
126 case Intrinsic::nvvm_f2ui_rn_ftz:
127 case Intrinsic::nvvm_d2i_rn:
128 case Intrinsic::nvvm_d2ui_rn:
129
130 case Intrinsic::nvvm_f2ll_rn:
131 case Intrinsic::nvvm_f2ull_rn:
132 case Intrinsic::nvvm_f2ll_rn_ftz:
133 case Intrinsic::nvvm_f2ull_rn_ftz:
134 case Intrinsic::nvvm_d2ll_rn:
135 case Intrinsic::nvvm_d2ull_rn:
137
138 // RP:
139 case Intrinsic::nvvm_f2i_rp:
140 case Intrinsic::nvvm_f2ui_rp:
141 case Intrinsic::nvvm_f2i_rp_ftz:
142 case Intrinsic::nvvm_f2ui_rp_ftz:
143 case Intrinsic::nvvm_d2i_rp:
144 case Intrinsic::nvvm_d2ui_rp:
145
146 case Intrinsic::nvvm_f2ll_rp:
147 case Intrinsic::nvvm_f2ull_rp:
148 case Intrinsic::nvvm_f2ll_rp_ftz:
149 case Intrinsic::nvvm_f2ull_rp_ftz:
150 case Intrinsic::nvvm_d2ll_rp:
151 case Intrinsic::nvvm_d2ull_rp:
153
154 // RZ:
155 case Intrinsic::nvvm_f2i_rz:
156 case Intrinsic::nvvm_f2ui_rz:
157 case Intrinsic::nvvm_f2i_rz_ftz:
158 case Intrinsic::nvvm_f2ui_rz_ftz:
159 case Intrinsic::nvvm_d2i_rz:
160 case Intrinsic::nvvm_d2ui_rz:
161
162 case Intrinsic::nvvm_f2ll_rz:
163 case Intrinsic::nvvm_f2ull_rz:
164 case Intrinsic::nvvm_f2ll_rz_ftz:
165 case Intrinsic::nvvm_f2ull_rz_ftz:
166 case Intrinsic::nvvm_d2ll_rz:
167 case Intrinsic::nvvm_d2ull_rz:
169 }
170 llvm_unreachable("Invalid f2i/d2i rounding mode intrinsic");
171 return APFloat::roundingMode::Invalid;
172}
173
174} // namespace nvvm
175} // namespace llvm
176#endif // LLVM_IR_NVVMINTRINSICUTILS_H
This file declares a class to represent arbitrary precision floating point values and provide a varie...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
APFloat::roundingMode IntrinsicGetRoundingMode(Intrinsic::ID IntrinsicID)
bool IntrinsicShouldFTZ(Intrinsic::ID IntrinsicID)
bool IntrinsicConvertsToSignedInteger(Intrinsic::ID IntrinsicID)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
RoundingMode
Rounding mode.
static constexpr roundingMode rmTowardNegative
Definition: APFloat.h:305
static constexpr roundingMode rmNearestTiesToEven
Definition: APFloat.h:302
static constexpr roundingMode rmTowardZero
Definition: APFloat.h:306
static constexpr roundingMode rmTowardPositive
Definition: APFloat.h:304