| AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool StreamingSVEMode=false, bool StreamingCompatibleSVEMode=false, bool HasMinSize=false) | llvm::AArch64Subtarget | |
| addrSinkUsingGEPs() const override | llvm::AArch64Subtarget | inline |
| adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override | llvm::AArch64Subtarget | |
| ARMProcFamily | llvm::AArch64Subtarget | protected |
| ARMProcFamilyEnum enum name | llvm::AArch64Subtarget | |
| CacheLineSize | llvm::AArch64Subtarget | protected |
| CallLoweringInfo | llvm::AArch64Subtarget | protected |
| classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const | llvm::AArch64Subtarget | |
| classifyGlobalFunctionReference(const GlobalValue *GV) const override | llvm::AArch64Subtarget | inline |
| ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const | llvm::AArch64Subtarget | |
| CustomCallSavedXRegs | llvm::AArch64Subtarget | protected |
| DefaultSVETFOpts | llvm::AArch64Subtarget | protected |
| enableEarlyIfConversion() const override | llvm::AArch64Subtarget | |
| enableMachinePipeliner() const override | llvm::AArch64Subtarget | |
| enableMachineScheduler() const override | llvm::AArch64Subtarget | inline |
| enablePostRAScheduler() const override | llvm::AArch64Subtarget | inline |
| FrameLowering | llvm::AArch64Subtarget | protected |
| getAddressCheckPSV() const | llvm::AArch64Subtarget | inline |
| getAuthenticatedLRCheckMethod() const | llvm::AArch64Subtarget | |
| getCacheLineSize() const override | llvm::AArch64Subtarget | inline |
| getCallLowering() const override | llvm::AArch64Subtarget | |
| getChkStkName() const | llvm::AArch64Subtarget | inline |
| getCustomPBQPConstraints() const override | llvm::AArch64Subtarget | |
| getFrameLowering() const override | llvm::AArch64Subtarget | inline |
| getInlineAsmLowering() const override | llvm::AArch64Subtarget | |
| getInstrInfo() const override | llvm::AArch64Subtarget | inline |
| getInstructionSelector() const override | llvm::AArch64Subtarget | |
| getLegalizerInfo() const override | llvm::AArch64Subtarget | |
| getMaxBytesForLoopAlignment() const | llvm::AArch64Subtarget | inline |
| getMaximumJumpTableSize() const | llvm::AArch64Subtarget | inline |
| getMaxInterleaveFactor() const | llvm::AArch64Subtarget | inline |
| getMaxPrefetchIterationsAhead() const override | llvm::AArch64Subtarget | inline |
| getMaxSVEVectorSizeInBits() const | llvm::AArch64Subtarget | inline |
| getMinimumJumpTableEntries() const | llvm::AArch64Subtarget | inline |
| getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override | llvm::AArch64Subtarget | inline |
| getMinSVEVectorSizeInBits() const | llvm::AArch64Subtarget | inline |
| getMinVectorRegisterBitWidth() const | llvm::AArch64Subtarget | inline |
| getNumXRegisterReserved() const | llvm::AArch64Subtarget | inline |
| getPrefetchDistance() const override | llvm::AArch64Subtarget | inline |
| getPrefFunctionAlignment() const | llvm::AArch64Subtarget | inline |
| getPrefLoopAlignment() const | llvm::AArch64Subtarget | inline |
| getProcFamily() const | llvm::AArch64Subtarget | inline |
| getRegBankInfo() const override | llvm::AArch64Subtarget | |
| getRegisterInfo() const override | llvm::AArch64Subtarget | inline |
| getSecurityCheckCookieName() const | llvm::AArch64Subtarget | inline |
| getSelectionDAGInfo() const override | llvm::AArch64Subtarget | inline |
| getSVETailFoldingDefaultOpts() const | llvm::AArch64Subtarget | inline |
| getTargetLowering() const override | llvm::AArch64Subtarget | inline |
| getTargetTriple() const | llvm::AArch64Subtarget | inline |
| getVectorInsertExtractBaseCost() const | llvm::AArch64Subtarget | |
| getVScaleForTuning() const | llvm::AArch64Subtarget | inline |
| hasCustomCallingConv() const | llvm::AArch64Subtarget | inline |
| hasFusion() const | llvm::AArch64Subtarget | inline |
| hasSVE2orSME() const | llvm::AArch64Subtarget | inline |
| hasSVEorSME() const | llvm::AArch64Subtarget | inline |
| InlineAsmLoweringInfo | llvm::AArch64Subtarget | protected |
| InstrInfo | llvm::AArch64Subtarget | protected |
| InstSelector | llvm::AArch64Subtarget | protected |
| isCallingConvWin64(CallingConv::ID CC) const | llvm::AArch64Subtarget | inline |
| IsLittle | llvm::AArch64Subtarget | protected |
| isLittleEndian() const | llvm::AArch64Subtarget | inline |
| isNeonAvailable() const | llvm::AArch64Subtarget | |
| isStreaming() const | llvm::AArch64Subtarget | inline |
| isStreamingCompatible() const | llvm::AArch64Subtarget | |
| isSVEAvailable() const | llvm::AArch64Subtarget | |
| isTargetAndroid() const | llvm::AArch64Subtarget | inline |
| isTargetCOFF() const | llvm::AArch64Subtarget | inline |
| isTargetDarwin() const | llvm::AArch64Subtarget | inline |
| isTargetELF() const | llvm::AArch64Subtarget | inline |
| isTargetFuchsia() const | llvm::AArch64Subtarget | inline |
| isTargetILP32() const | llvm::AArch64Subtarget | inline |
| isTargetIOS() const | llvm::AArch64Subtarget | inline |
| isTargetLinux() const | llvm::AArch64Subtarget | inline |
| isTargetMachO() const | llvm::AArch64Subtarget | inline |
| isTargetWindows() const | llvm::AArch64Subtarget | inline |
| isWindowsArm64EC() const | llvm::AArch64Subtarget | inline |
| isXRaySupported() const override | llvm::AArch64Subtarget | inline |
| isXRegCustomCalleeSaved(size_t i) const | llvm::AArch64Subtarget | inline |
| isXRegisterReserved(size_t i) const | llvm::AArch64Subtarget | inline |
| isXRegisterReservedForRA(size_t i) const | llvm::AArch64Subtarget | inline |
| Legalizer | llvm::AArch64Subtarget | protected |
| MaxBytesForLoopAlignment | llvm::AArch64Subtarget | protected |
| MaxInterleaveFactor | llvm::AArch64Subtarget | protected |
| MaxJumpTableSize | llvm::AArch64Subtarget | protected |
| MaxPrefetchIterationsAhead | llvm::AArch64Subtarget | protected |
| MaxSVEVectorSizeInBits | llvm::AArch64Subtarget | protected |
| MinimumJumpTableEntries | llvm::AArch64Subtarget | protected |
| MinPrefetchStride | llvm::AArch64Subtarget | protected |
| MinSVEVectorSizeInBits | llvm::AArch64Subtarget | protected |
| MinVectorRegisterBitWidth | llvm::AArch64Subtarget | protected |
| mirFileLoaded(MachineFunction &MF) const override | llvm::AArch64Subtarget | |
| Others enum value | llvm::AArch64Subtarget | |
| overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override | llvm::AArch64Subtarget | |
| ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) | llvm::AArch64Subtarget | |
| PrefetchDistance | llvm::AArch64Subtarget | protected |
| PrefFunctionAlignment | llvm::AArch64Subtarget | protected |
| PrefLoopAlignment | llvm::AArch64Subtarget | protected |
| RegBankInfo | llvm::AArch64Subtarget | protected |
| ReserveXRegister | llvm::AArch64Subtarget | protected |
| ReserveXRegisterForRA | llvm::AArch64Subtarget | protected |
| StreamingCompatibleSVEMode | llvm::AArch64Subtarget | protected |
| StreamingSVEMode | llvm::AArch64Subtarget | protected |
| supportsAddressTopByteIgnored() const | llvm::AArch64Subtarget | |
| swiftAsyncContextIsDynamicallySet() const | llvm::AArch64Subtarget | inline |
| TargetTriple | llvm::AArch64Subtarget | protected |
| TLInfo | llvm::AArch64Subtarget | protected |
| TSInfo | llvm::AArch64Subtarget | protected |
| useAA() const override | llvm::AArch64Subtarget | |
| useDFAforSMS() const override | llvm::AArch64Subtarget | inline |
| useSmallAddressing() const | llvm::AArch64Subtarget | inline |
| useSVEForFixedLengthVectors() const | llvm::AArch64Subtarget | inline |
| useSVEForFixedLengthVectors(EVT VT) const | llvm::AArch64Subtarget | inline |
| VectorInsertExtractBaseCost | llvm::AArch64Subtarget | protected |
| VScaleForTuning | llvm::AArch64Subtarget | protected |
