| addImplicitDefUseOperands(MachineFunction &MF) | llvm::MachineInstr | |
| addMemOperand(MachineFunction &MF, MachineMemOperand *MO) | llvm::MachineInstr | |
| addOperand(MachineFunction &MF, const MachineOperand &Op) | llvm::MachineInstr | |
| addOperand(const MachineOperand &Op) | llvm::MachineInstr | |
| addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false) | llvm::MachineInstr | |
| addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr) | llvm::MachineInstr | |
| addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false) | llvm::MachineInstr | |
| all_defs() | llvm::MachineInstr | inline |
| all_defs() const | llvm::MachineInstr | inline |
| all_uses() | llvm::MachineInstr | inline |
| all_uses() const | llvm::MachineInstr | inline |
| allDefsAreDead() const | llvm::MachineInstr | |
| allImplicitDefsAreDead() const | llvm::MachineInstr | |
| AllInBundle enum value | llvm::MachineInstr | |
| AnyInBundle enum value | llvm::MachineInstr | |
| BundledPred enum value | llvm::MachineInstr | |
| BundledSucc enum value | llvm::MachineInstr | |
| bundleWithPred() | llvm::MachineInstr | |
| bundleWithSucc() | llvm::MachineInstr | |
| canFoldAsLoad(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| changeDebugValuesDefReg(Register Reg) | llvm::MachineInstr | |
| CheckDefs enum value | llvm::MachineInstr | |
| CheckKillDead enum value | llvm::MachineInstr | |
| classof(const MachineInstr *MI) | llvm::GAddSubCarryInOut | inlinestatic |
| clearAsmPrinterFlag(CommentFlag Flag) | llvm::MachineInstr | inline |
| clearAsmPrinterFlags() | llvm::MachineInstr | inline |
| clearFlag(MIFlag Flag) | llvm::MachineInstr | inline |
| clearFlags(unsigned flags) | llvm::MachineInstr | inline |
| clearKillInfo() | llvm::MachineInstr | |
| clearRegisterDeads(Register Reg) | llvm::MachineInstr | |
| clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo) | llvm::MachineInstr | |
| cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI) | llvm::MachineInstr | |
| cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) | llvm::MachineInstr | |
| cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs) | llvm::MachineInstr | |
| collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues) | llvm::MachineInstr | |
| CommentFlag enum name | llvm::MachineInstr | |
| const_mop_iterator typedef | llvm::MachineInstr | |
| const_reverse_self_iterator typedef | llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type > | protected |
| const_self_iterator typedef | llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type > | protected |
| copyFlagsFromInstruction(const Instruction &I) | llvm::MachineInstr | static |
| copyImplicitOps(MachineFunction &MF, const MachineInstr &MI) | llvm::MachineInstr | |
| copyIRFlags(const Instruction &I) | llvm::MachineInstr | |
| debug_operands() | llvm::MachineInstr | inline |
| debug_operands() const | llvm::MachineInstr | inline |
| definesRegister(Register Reg, const TargetRegisterInfo *TRI) const | llvm::MachineInstr | inline |
| defs() | llvm::MachineInstr | inline |
| defs() const | llvm::MachineInstr | inline |
| Disjoint enum value | llvm::MachineInstr | |
| dropDebugNumber() | llvm::MachineInstr | inline |
| dropMemRefs(MachineFunction &MF) | llvm::MachineInstr | |
| dropPoisonGeneratingFlags() | llvm::GenericMachineInstr | inline |
| dump() const | llvm::MachineInstr | |
| dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const | llvm::MachineInstr | |
| emitError(StringRef Msg) const | llvm::MachineInstr | |
| eraseFromBundle() | llvm::MachineInstr | |
| eraseFromParent() | llvm::MachineInstr | |
| explicit_operands() | llvm::MachineInstr | inline |
| explicit_operands() const | llvm::MachineInstr | inline |
| explicit_uses() | llvm::MachineInstr | inline |
| explicit_uses() const | llvm::MachineInstr | inline |
| filtered_const_mop_iterator typedef | llvm::MachineInstr | |
| filtered_mop_iterator typedef | llvm::MachineInstr | |
| findFirstPredOperandIdx() const | llvm::MachineInstr | |
| findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const | llvm::MachineInstr | |
| findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) | llvm::MachineInstr | inline |
| findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const | llvm::MachineInstr | inline |
| findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const | llvm::MachineInstr | |
| findRegisterUseOperand(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) | llvm::MachineInstr | inline |
| findRegisterUseOperand(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const | llvm::MachineInstr | inline |
| findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const | llvm::MachineInstr | |
| findTiedOperandIdx(unsigned OpIdx) const | llvm::MachineInstr | |
| FmAfn enum value | llvm::MachineInstr | |
| FmArcp enum value | llvm::MachineInstr | |
| FmContract enum value | llvm::MachineInstr | |
| FmNoInfs enum value | llvm::MachineInstr | |
| FmNoNans enum value | llvm::MachineInstr | |
| FmNsz enum value | llvm::MachineInstr | |
| FmReassoc enum value | llvm::MachineInstr | |
| FrameDestroy enum value | llvm::MachineInstr | |
| FrameSetup enum value | llvm::MachineInstr | |
| GenericMachineInstr()=delete | llvm::GenericMachineInstr | |
| getAsmPrinterFlag(CommentFlag Flag) const | llvm::MachineInstr | inline |
| getAsmPrinterFlags() const | llvm::MachineInstr | inline |
| getBundleSize() const | llvm::MachineInstr | |
| getCarryInReg() const | llvm::GAddSubCarryInOut | inline |
| getCarryOutReg() const | llvm::GBinOpCarryOut | inline |
| getCFIType() const | llvm::MachineInstr | inline |
| getDebugExpression() const | llvm::MachineInstr | |
| getDebugExpressionOp() const | llvm::MachineInstr | |
| getDebugExpressionOp() | llvm::MachineInstr | |
| getDebugInstrNum() | llvm::MachineInstr | |
| getDebugInstrNum(MachineFunction &MF) | llvm::MachineInstr | |
| getDebugLabel() const | llvm::MachineInstr | |
| getDebugLoc() const | llvm::MachineInstr | inline |
| getDebugOffset() const | llvm::MachineInstr | inline |
| getDebugOffset() | llvm::MachineInstr | inline |
| getDebugOperand(unsigned Index) | llvm::MachineInstr | inline |
| getDebugOperand(unsigned Index) const | llvm::MachineInstr | inline |
| getDebugOperandIndex(const MachineOperand *Op) const | llvm::MachineInstr | inline |
| getDebugOperandsForReg(Instruction *MI, Register Reg) | llvm::MachineInstr | inlinestatic |
| getDebugOperandsForReg(Register Reg) const | llvm::MachineInstr | inline |
| getDebugOperandsForReg(Register Reg) | llvm::MachineInstr | inline |
| getDebugVariable() const | llvm::MachineInstr | |
| getDebugVariableOp() const | llvm::MachineInstr | |
| getDebugVariableOp() | llvm::MachineInstr | |
| getDesc() const | llvm::MachineInstr | inline |
| getDstReg() const | llvm::GBinOpCarryOut | inline |
| getFirst2LLTs() const | llvm::MachineInstr | |
| getFirst2RegLLTs() const | llvm::MachineInstr | |
| getFirst2Regs() const | llvm::MachineInstr | inline |
| getFirst3LLTs() const | llvm::MachineInstr | |
| getFirst3RegLLTs() const | llvm::MachineInstr | |
| getFirst3Regs() const | llvm::MachineInstr | inline |
| getFirst4LLTs() const | llvm::MachineInstr | |
| getFirst4RegLLTs() const | llvm::MachineInstr | |
| getFirst4Regs() const | llvm::MachineInstr | inline |
| getFirst5LLTs() const | llvm::MachineInstr | |
| getFirst5RegLLTs() const | llvm::MachineInstr | |
| getFirst5Regs() const | llvm::MachineInstr | inline |
| getFlag(MIFlag Flag) const | llvm::MachineInstr | inline |
| getFlags() const | llvm::MachineInstr | inline |
| getFoldedRestoreSize(const TargetInstrInfo *TII) const | llvm::MachineInstr | |
| getFoldedSpillSize(const TargetInstrInfo *TII) const | llvm::MachineInstr | |
| getHeapAllocMarker() const | llvm::MachineInstr | inline |
| getInlineAsmDialect() const | llvm::MachineInstr | |
| getIterator() | llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type > | inline |
| getIterator() const | llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type > | inline |
| getLHS() | llvm::GBinOpCarryOut | inline |
| getLHSReg() const | llvm::GBinOpCarryOut | inline |
| getMF() const | llvm::MachineInstr | |
| getMF() | llvm::MachineInstr | inline |
| getMMRAMetadata() const | llvm::MachineInstr | inline |
| getNextNode() | llvm::ilist_node_with_parent< MachineInstr, MachineBasicBlock, ilist_sentinel_tracking< true > > | inline |
| getNextNode() const | llvm::ilist_node_with_parent< MachineInstr, MachineBasicBlock, ilist_sentinel_tracking< true > > | inline |
| getNumDebugOperands() const | llvm::MachineInstr | inline |
| getNumDefs() const | llvm::MachineInstr | inline |
| getNumExplicitDefs() const | llvm::MachineInstr | |
| getNumExplicitOperands() const | llvm::MachineInstr | |
| getNumImplicitOperands() const | llvm::MachineInstr | inline |
| getNumMemOperands() const | llvm::MachineInstr | inline |
| getNumOperands() const | llvm::MachineInstr | inline |
| getOpcode() const | llvm::MachineInstr | inline |
| getOperand(unsigned i) const | llvm::MachineInstr | inline |
| getOperand(unsigned i) | llvm::MachineInstr | inline |
| getOperandNo(const_mop_iterator I) const | llvm::MachineInstr | inline |
| getParent() const | llvm::MachineInstr | inline |
| getParent() | llvm::MachineInstr | inline |
| getPCSections() const | llvm::MachineInstr | inline |
| getPostInstrSymbol() const | llvm::MachineInstr | inline |
| getPreInstrSymbol() const | llvm::MachineInstr | inline |
| getPrevNode() | llvm::ilist_node_with_parent< MachineInstr, MachineBasicBlock, ilist_sentinel_tracking< true > > | inline |
| getPrevNode() const | llvm::ilist_node_with_parent< MachineInstr, MachineBasicBlock, ilist_sentinel_tracking< true > > | inline |
| getReg(unsigned Idx) const | llvm::GenericMachineInstr | inline |
| getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const | llvm::MachineInstr | |
| getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const | llvm::MachineInstr | |
| getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const | llvm::MachineInstr | |
| getRestoreSize(const TargetInstrInfo *TII) const | llvm::MachineInstr | |
| getReverseIterator() | llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type > | inline |
| getReverseIterator() const | llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type > | inline |
| getRHS() | llvm::GBinOpCarryOut | inline |
| getRHSReg() const | llvm::GBinOpCarryOut | inline |
| getSpillSize(const TargetInstrInfo *TII) const | llvm::MachineInstr | |
| getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const | llvm::MachineInstr | |
| hasComplexRegisterTies() const | llvm::MachineInstr | |
| hasDebugOperandForReg(Register Reg) const | llvm::MachineInstr | inline |
| hasDelaySlot(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| hasImplicitDef() const | llvm::MachineInstr | inline |
| hasOneMemOperand() const | llvm::MachineInstr | inline |
| hasOptionalDef(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| hasOrderedMemoryRef() const | llvm::MachineInstr | |
| hasPoisonGeneratingFlags() const | llvm::GenericMachineInstr | inline |
| hasPostISelHook(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| hasRegisterImplicitUseOperand(Register Reg) const | llvm::MachineInstr | |
| hasUnmodeledSideEffects() const | llvm::MachineInstr | |
| IgnoreBundle enum value | llvm::MachineInstr | |
| IgnoreDefs enum value | llvm::MachineInstr | |
| IgnoreVRegDefs enum value | llvm::MachineInstr | |
| ilist_node_impl()=default | llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type > | protected |
| ilist_node_with_parent()=default | llvm::ilist_node_with_parent< MachineInstr, MachineBasicBlock, ilist_sentinel_tracking< true > > | protected |
| implicit_operands() | llvm::MachineInstr | inline |
| implicit_operands() const | llvm::MachineInstr | inline |
| insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops) | llvm::MachineInstr | |
| isAdd() const | llvm::GAddSubCarryOut | inline |
| isAnnotationLabel() const | llvm::MachineInstr | inline |
| isAsCheapAsAMove(QueryType Type=AllInBundle) const | llvm::MachineInstr | inline |
| isBarrier(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| isBitcast(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isBranch(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| isBundle() const | llvm::MachineInstr | inline |
| isBundled() const | llvm::MachineInstr | inline |
| isBundledWithPred() const | llvm::MachineInstr | inline |
| isBundledWithSucc() const | llvm::MachineInstr | inline |
| isCall(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | |
| isCFIInstruction() const | llvm::MachineInstr | inline |
| isCommutable(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isCompare(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isConditionalBranch(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| isConstantValuePHI() const | llvm::MachineInstr | |
| isConvergent(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isCopy() const | llvm::MachineInstr | inline |
| isCopyLike() const | llvm::MachineInstr | inline |
| isDebugEntryValue() const | llvm::MachineInstr | |
| isDebugInstr() const | llvm::MachineInstr | inline |
| isDebugLabel() const | llvm::MachineInstr | inline |
| isDebugOffsetImm() const | llvm::MachineInstr | inline |
| isDebugOperand(const MachineOperand *Op) const | llvm::MachineInstr | inline |
| isDebugOrPseudoInstr() const | llvm::MachineInstr | inline |
| isDebugPHI() const | llvm::MachineInstr | inline |
| isDebugRef() const | llvm::MachineInstr | inline |
| isDebugValue() const | llvm::MachineInstr | inline |
| isDebugValueLike() const | llvm::MachineInstr | inline |
| isDebugValueList() const | llvm::MachineInstr | inline |
| isDereferenceableInvariantLoad() const | llvm::MachineInstr | |
| isEHLabel() const | llvm::MachineInstr | inline |
| isEHScopeReturn(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| isEquivalentDbgInstr(const MachineInstr &Other) const | llvm::MachineInstr | |
| IsExact enum value | llvm::MachineInstr | |
| isExtractSubreg() const | llvm::MachineInstr | inline |
| isExtractSubregLike(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isFullCopy() const | llvm::MachineInstr | inline |
| isGCLabel() const | llvm::MachineInstr | inline |
| isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const | llvm::MachineInstr | |
| isIdentityCopy() const | llvm::MachineInstr | inline |
| isImplicitDef() const | llvm::MachineInstr | inline |
| isIndirectBranch(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| isIndirectDebugValue() const | llvm::MachineInstr | inline |
| isInlineAsm() const | llvm::MachineInstr | inline |
| isInsertSubreg() const | llvm::MachineInstr | inline |
| isInsertSubregLike(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isInsideBundle() const | llvm::MachineInstr | inline |
| isJumpTableDebugInfo() const | llvm::MachineInstr | inline |
| isKill() const | llvm::MachineInstr | inline |
| isLabel() const | llvm::MachineInstr | inline |
| isLoadFoldBarrier() const | llvm::MachineInstr | |
| isMetaInstruction(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isMoveImmediate(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isMoveReg(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isNonListDebugValue() const | llvm::MachineInstr | inline |
| isNotDuplicable(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| isOperandSubregIdx(unsigned OpIdx) const | llvm::MachineInstr | inline |
| isPHI() const | llvm::MachineInstr | inline |
| isPosition() const | llvm::MachineInstr | inline |
| isPredicable(QueryType Type=AllInBundle) const | llvm::MachineInstr | inline |
| isPreISelOpcode(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isPseudo(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isPseudoProbe() const | llvm::MachineInstr | inline |
| isRegSequence() const | llvm::MachineInstr | inline |
| isRegSequenceLike(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const | llvm::MachineInstr | inline |
| isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const | llvm::MachineInstr | inline |
| isRematerializable(QueryType Type=AllInBundle) const | llvm::MachineInstr | inline |
| isReturn(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| isSafeToMove(bool &SawStore) const | llvm::MachineInstr | |
| isSelect(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| isSentinel() const | llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type > | inline |
| isSigned() const | llvm::GAddSubCarryOut | inline |
| isStackAligningInlineAsm() const | llvm::MachineInstr | |
| isSub() const | llvm::GAddSubCarryOut | inline |
| isSubregToReg() const | llvm::MachineInstr | inline |
| isTerminator(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| isTransient() const | llvm::MachineInstr | inline |
| isUnconditionalBranch(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| isUndefDebugValue() const | llvm::MachineInstr | inline |
| isUnsigned() const | llvm::GAddSubCarryOut | inline |
| isVariadic(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| killsRegister(Register Reg, const TargetRegisterInfo *TRI) const | llvm::MachineInstr | inline |
| MachineInstr(const MachineInstr &)=delete | llvm::MachineInstr | |
| mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const | llvm::MachineInstr | |
| mayFoldInlineAsmRegOp(unsigned OpId) const | llvm::MachineInstr | |
| mayLoad(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| mayLoadOrStore(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| mayRaiseFPException() const | llvm::MachineInstr | inline |
| mayStore(QueryType Type=AnyInBundle) const | llvm::MachineInstr | inline |
| memoperands() const | llvm::MachineInstr | inline |
| memoperands_begin() const | llvm::MachineInstr | inline |
| memoperands_empty() const | llvm::MachineInstr | inline |
| memoperands_end() const | llvm::MachineInstr | inline |
| mergeFlagsWith(const MachineInstr &Other) const | llvm::MachineInstr | |
| MICheckType enum name | llvm::MachineInstr | |
| MIFlag enum name | llvm::MachineInstr | |
| mmo_iterator typedef | llvm::MachineInstr | |
| modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const | llvm::MachineInstr | inline |
| mop_iterator typedef | llvm::MachineInstr | |
| moveBefore(MachineInstr *MovePos) | llvm::MachineInstr | |
| NoConvergent enum value | llvm::MachineInstr | |
| NoFlags enum value | llvm::MachineInstr | |
| NoFPExcept enum value | llvm::MachineInstr | |
| NoMerge enum value | llvm::MachineInstr | |
| NonNeg enum value | llvm::MachineInstr | |
| NoSchedComment enum value | llvm::MachineInstr | |
| NoSWrap enum value | llvm::MachineInstr | |
| NoUSWrap enum value | llvm::MachineInstr | |
| NoUWrap enum value | llvm::MachineInstr | |
| operands() | llvm::MachineInstr | inline |
| operands() const | llvm::MachineInstr | inline |
| operands_begin() | llvm::MachineInstr | inline |
| operands_begin() const | llvm::MachineInstr | inline |
| operands_end() | llvm::MachineInstr | inline |
| operands_end() const | llvm::MachineInstr | inline |
| operator=(const MachineInstr &)=delete | llvm::MachineInstr | |
| peekDebugInstrNum() const | llvm::MachineInstr | inline |
| print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const | llvm::MachineInstr | |
| print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const | llvm::MachineInstr | |
| QueryType enum name | llvm::MachineInstr | |
| readsRegister(Register Reg, const TargetRegisterInfo *TRI) const | llvm::MachineInstr | inline |
| readsVirtualRegister(Register Reg) const | llvm::MachineInstr | inline |
| readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const | llvm::MachineInstr | |
| registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const | llvm::MachineInstr | inline |
| ReloadReuse enum value | llvm::MachineInstr | |
| removeFromBundle() | llvm::MachineInstr | |
| removeFromParent() | llvm::MachineInstr | |
| removeOperand(unsigned OpNo) | llvm::MachineInstr | |
| reverse_self_iterator typedef | llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type > | protected |
| self_iterator typedef | llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type > | protected |
| setAsmPrinterFlag(uint8_t Flag) | llvm::MachineInstr | inline |
| setCFIType(MachineFunction &MF, uint32_t Type) | llvm::MachineInstr | |
| setDebugInstrNum(unsigned Num) | llvm::MachineInstr | inline |
| setDebugLoc(DebugLoc DL) | llvm::MachineInstr | inline |
| setDebugValueUndef() | llvm::MachineInstr | inline |
| setDesc(const MCInstrDesc &TID) | llvm::MachineInstr | |
| setFlag(MIFlag Flag) | llvm::MachineInstr | inline |
| setFlags(unsigned flags) | llvm::MachineInstr | inline |
| setHeapAllocMarker(MachineFunction &MF, MDNode *MD) | llvm::MachineInstr | |
| setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs) | llvm::MachineInstr | |
| setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs) | llvm::MachineInstr | |
| ilist_node_with_parent< MachineInstr, MachineBasicBlock, ilist_sentinel_tracking< true > >::setParent(ParentTy *Parent) | llvm::ilist_detail::node_parent_access< NodeTy, ParentTy > | inline |
| setPCSections(MachineFunction &MF, MDNode *MD) | llvm::MachineInstr | |
| setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI) | llvm::MachineInstr | |
| setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) | llvm::MachineInstr | |
| setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) | llvm::MachineInstr | |
| setRegisterDefReadUndef(Register Reg, bool IsUndef=true) | llvm::MachineInstr | |
| shouldUpdateCallSiteInfo() const | llvm::MachineInstr | |
| substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo) | llvm::MachineInstr | |
| TAsmComments enum value | llvm::MachineInstr | |
| tieOperands(unsigned DefIdx, unsigned UseIdx) | llvm::MachineInstr | |
| unbundleFromPred() | llvm::MachineInstr | |
| unbundleFromSucc() | llvm::MachineInstr | |
| Unpredictable enum value | llvm::MachineInstr | |
| untieRegOperand(unsigned OpIdx) | llvm::MachineInstr | inline |
| uses() | llvm::MachineInstr | inline |
| uses() const | llvm::MachineInstr | inline |
| usesCustomInsertionHook(QueryType Type=IgnoreBundle) const | llvm::MachineInstr | inline |
| ~MachineInstr()=delete | llvm::MachineInstr | |
