LLVM 20.0.0git
llvm::SIMachineFunctionInfo Member List

This is the complete list of members for llvm::SIMachineFunctionInfo, including all inherited members.

addDispatchID(const SIRegisterInfo &TRI)llvm::SIMachineFunctionInfo
addDispatchPtr(const SIRegisterInfo &TRI)llvm::SIMachineFunctionInfo
addFlatScratchInit(const SIRegisterInfo &TRI)llvm::SIMachineFunctionInfo
addImplicitBufferPtr(const SIRegisterInfo &TRI)llvm::SIMachineFunctionInfo
addKernargSegmentPtr(const SIRegisterInfo &TRI)llvm::SIMachineFunctionInfo
addLDSKernelId()llvm::SIMachineFunctionInfo
addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC, unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs)llvm::SIMachineFunctionInfo
addPrivateSegmentBuffer(const SIRegisterInfo &TRI)llvm::SIMachineFunctionInfo
addPrivateSegmentSize(const SIRegisterInfo &TRI)llvm::SIMachineFunctionInfo
addPrivateSegmentWaveByteOffset()llvm::SIMachineFunctionInfoinline
addQueuePtr(const SIRegisterInfo &TRI)llvm::SIMachineFunctionInfo
addReservedUserSGPR()llvm::SIMachineFunctionInfoinline
addToPrologEpilogSGPRSpills(Register Reg, PrologEpilogSGPRSaveRestoreInfo SI)llvm::SIMachineFunctionInfoinline
addToSpilledSGPRs(unsigned num)llvm::SIMachineFunctionInfoinline
addToSpilledVGPRs(unsigned num)llvm::SIMachineFunctionInfoinline
addWorkGroupIDX()llvm::SIMachineFunctionInfoinline
addWorkGroupIDY()llvm::SIMachineFunctionInfoinline
addWorkGroupIDZ()llvm::SIMachineFunctionInfoinline
addWorkGroupInfo()llvm::SIMachineFunctionInfoinline
allocateLDSGlobal(const DataLayout &DL, const GlobalVariable &GV)llvm::AMDGPUMachineFunctioninline
allocateLDSGlobal(const DataLayout &DL, const GlobalVariable &GV, Align Trailing)llvm::AMDGPUMachineFunction
allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, bool SpillToPhysVGPRLane=false, bool IsPrologEpilog=false)llvm::SIMachineFunctionInfo
allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)llvm::SIMachineFunctionInfo
allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4))llvm::SIMachineFunctionInfo
AMDGPUMachineFunction(const Function &F, const AMDGPUSubtarget &ST)llvm::AMDGPUMachineFunction
checkFlag(Register Reg, uint8_t Flag) constllvm::SIMachineFunctionInfoinline
checkIndexInPrologEpilogSGPRSpills(int FI) constllvm::SIMachineFunctionInfoinline
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const overridellvm::SIMachineFunctionInfovirtual
create(BumpPtrAllocator &Allocator, const Function &F, const SubtargetTy *STI)llvm::MachineFunctionInfoinlinestatic
create(BumpPtrAllocator &Allocator, const Ty &MFI)llvm::MachineFunctionInfoinlinestatic
DynLDSAlignllvm::AMDGPUMachineFunctionprotected
ExplicitKernArgSizellvm::AMDGPUMachineFunctionprotected
GCNTargetMachinellvm::SIMachineFunctionInfofriend
GDSSizellvm::AMDGPUMachineFunctionprotected
get32BitAddressHighBits() constllvm::SIMachineFunctionInfoinline
getAGPRSpillVGPRs() constllvm::SIMachineFunctionInfoinline
getAllScratchSGPRCopyDstRegs(SmallVectorImpl< Register > &Regs) constllvm::SIMachineFunctionInfoinline
getArgInfo()llvm::SIMachineFunctionInfoinline
getArgInfo() constllvm::SIMachineFunctionInfoinline
getBytesInStackArgArea() constllvm::SIMachineFunctionInfoinline
getDynLDSAlign() constllvm::AMDGPUMachineFunctioninline
getExplicitKernArgSize() constllvm::AMDGPUMachineFunctioninline
getFlatWorkGroupSizes() constllvm::SIMachineFunctionInfoinline
getFrameOffsetReg() constllvm::SIMachineFunctionInfoinline
getGDSSize() constllvm::AMDGPUMachineFunctioninline
getGITPtrHigh() constllvm::SIMachineFunctionInfoinline
getGITPtrLoReg(const MachineFunction &MF) constllvm::SIMachineFunctionInfo
getGWSPSV(const AMDGPUTargetMachine &TM)llvm::SIMachineFunctionInfoinline
getImplicitBufferPtrUserSGPR() constllvm::SIMachineFunctionInfoinline
getLDSAbsoluteAddress(const GlobalValue &GV)llvm::AMDGPUMachineFunctionstatic
getLDSKernelIdMetadata(const Function &F)llvm::AMDGPUMachineFunctionstatic
getLDSSize() constllvm::AMDGPUMachineFunctioninline
getLongBranchReservedReg() constllvm::SIMachineFunctionInfoinline
getMaxFlatWorkGroupSize() constllvm::SIMachineFunctionInfoinline
getMaxKernArgAlign() constllvm::AMDGPUMachineFunctioninline
getMaxNumWorkGroups() constllvm::SIMachineFunctionInfoinline
getMaxNumWorkGroupsX() constllvm::SIMachineFunctionInfoinline
getMaxNumWorkGroupsY() constllvm::SIMachineFunctionInfoinline
getMaxNumWorkGroupsZ() constllvm::SIMachineFunctionInfoinline
getMaxWavesPerEU() constllvm::SIMachineFunctionInfoinline
getMinAllowedOccupancy() constllvm::SIMachineFunctionInfoinline
getMinFlatWorkGroupSize() constllvm::SIMachineFunctionInfoinline
getMinWavesPerEU() constllvm::SIMachineFunctionInfoinline
getMode() constllvm::SIMachineFunctionInfoinline
getNumKernargPreloadedSGPRs() constllvm::SIMachineFunctionInfoinline
getNumPreloadedSGPRs() constllvm::SIMachineFunctionInfoinline
getNumSpilledSGPRs() constllvm::SIMachineFunctionInfoinline
getNumSpilledVGPRs() constllvm::SIMachineFunctionInfoinline
getNumUserSGPRs() constllvm::SIMachineFunctionInfoinline
getOccupancy() constllvm::SIMachineFunctionInfoinline
getOptionalScavengeFI() constllvm::SIMachineFunctionInfoinline
getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) constllvm::SIMachineFunctionInfoinline
getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) constllvm::SIMachineFunctionInfoinline
getPrivateSegmentWaveByteOffsetSystemSGPR() constllvm::SIMachineFunctionInfoinline
getPrologEpilogSGPRSaveRestoreInfo(Register Reg) constllvm::SIMachineFunctionInfoinline
getPrologEpilogSGPRSpills() constllvm::SIMachineFunctionInfoinline
getPSInputAddr() constllvm::SIMachineFunctionInfoinline
getPSInputEnable() constllvm::SIMachineFunctionInfoinline
getQueuePtrUserSGPR() constllvm::SIMachineFunctionInfoinline
getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)llvm::SIMachineFunctionInfo
getScratchRSrcReg() constllvm::SIMachineFunctionInfoinline
getScratchSGPRCopyDstReg(Register Reg) constllvm::SIMachineFunctionInfoinline
getSGPRForEXECCopy() constllvm::SIMachineFunctionInfoinline
getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) constllvm::SIMachineFunctionInfoinline
getSGPRSpillToVirtualVGPRLanes(int FrameIndex) constllvm::SIMachineFunctionInfoinline
getSGPRSpillVGPRs() constllvm::SIMachineFunctionInfoinline
getStackPtrOffsetReg() constllvm::SIMachineFunctionInfoinline
getUserSGPRInfo()llvm::SIMachineFunctionInfoinline
getUserSGPRInfo() constllvm::SIMachineFunctionInfoinline
getVGPRForAGPRCopy() constllvm::SIMachineFunctionInfoinline
getVGPRSpillAGPRs() constllvm::SIMachineFunctionInfoinline
getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) constllvm::SIMachineFunctionInfoinline
getWavesPerEU() constllvm::SIMachineFunctionInfoinline
getWWMReservedRegs() constllvm::SIMachineFunctionInfoinline
getWWMSpills() constllvm::SIMachineFunctionInfoinline
hasImplicitArgPtr() constllvm::SIMachineFunctionInfoinline
hasLDSKernelId() constllvm::SIMachineFunctionInfoinline
hasNonSpillStackObjects() constllvm::SIMachineFunctionInfoinline
hasNoSignedZerosFPMath() constllvm::AMDGPUMachineFunctioninline
hasPrivateSegmentWaveByteOffset() constllvm::SIMachineFunctionInfoinline
hasPrologEpilogSGPRSpillEntry(Register Reg) constllvm::SIMachineFunctionInfoinline
hasSpilledSGPRs() constllvm::SIMachineFunctionInfoinline
hasSpilledVGPRs() constllvm::SIMachineFunctionInfoinline
hasVRegFlags()llvm::SIMachineFunctionInfoinline
hasWorkGroupIDX() constllvm::SIMachineFunctionInfoinline
hasWorkGroupIDY() constllvm::SIMachineFunctionInfoinline
hasWorkGroupIDZ() constllvm::SIMachineFunctionInfoinline
hasWorkGroupInfo() constllvm::SIMachineFunctionInfoinline
hasWorkItemIDX() constllvm::SIMachineFunctionInfoinline
hasWorkItemIDY() constllvm::SIMachineFunctionInfoinline
hasWorkItemIDZ() constllvm::SIMachineFunctionInfoinline
increaseOccupancy(const MachineFunction &MF, unsigned Limit)llvm::SIMachineFunctionInfoinline
initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)llvm::SIMachineFunctionInfo
isBottomOfStack() constllvm::AMDGPUMachineFunctioninline
isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) constllvm::SIMachineFunctionInfo
IsChainFunctionllvm::AMDGPUMachineFunctionprotected
isChainFunction() constllvm::AMDGPUMachineFunctioninline
isDynamicLDSUsed() constllvm::AMDGPUMachineFunction
isEntryFunction() constllvm::AMDGPUMachineFunctioninline
IsEntryFunctionllvm::AMDGPUMachineFunctionprotected
isMemoryBound() constllvm::AMDGPUMachineFunctioninline
IsModuleEntryFunctionllvm::AMDGPUMachineFunctionprotected
isModuleEntryFunction() constllvm::AMDGPUMachineFunctioninline
isPSInputAllocated(unsigned Index) constllvm::SIMachineFunctionInfoinline
isStackRealigned() constllvm::SIMachineFunctionInfoinline
LDSSizellvm::AMDGPUMachineFunctionprotected
limitOccupancy(const MachineFunction &MF)llvm::SIMachineFunctionInfo
limitOccupancy(unsigned Limit)llvm::SIMachineFunctionInfoinline
markPSInputAllocated(unsigned Index)llvm::SIMachineFunctionInfoinline
markPSInputEnabled(unsigned Index)llvm::SIMachineFunctionInfoinline
MaxKernArgAlignllvm::AMDGPUMachineFunctionprotected
mayNeedAGPRs() constllvm::SIMachineFunctionInfoinline
mayUseAGPRs(const Function &F) constllvm::SIMachineFunctionInfo
MemoryBoundllvm::AMDGPUMachineFunctionprotected
needsWaveLimiter() constllvm::AMDGPUMachineFunctioninline
NoSignedZerosFPMathllvm::AMDGPUMachineFunctionprotected
removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)llvm::SIMachineFunctionInfo
reserveWWMRegister(Register Reg)llvm::SIMachineFunctionInfoinline
returnsVoid() constllvm::SIMachineFunctionInfoinline
setBytesInStackArgArea(unsigned Bytes)llvm::SIMachineFunctionInfoinline
setDynLDSAlign(const Function &F, const GlobalVariable &GV)llvm::AMDGPUMachineFunction
setFlag(Register Reg, uint8_t Flag)llvm::SIMachineFunctionInfoinline
setFrameOffsetReg(Register Reg)llvm::SIMachineFunctionInfoinline
setHasNonSpillStackObjects(bool StackObject=true)llvm::SIMachineFunctionInfoinline
setHasSpilledSGPRs(bool Spill=true)llvm::SIMachineFunctionInfoinline
setHasSpilledVGPRs(bool Spill=true)llvm::SIMachineFunctionInfoinline
setIfReturnsVoid(bool Value)llvm::SIMachineFunctionInfoinline
setIsStackRealigned(bool Realigned=true)llvm::SIMachineFunctionInfoinline
setLongBranchReservedReg(Register Reg)llvm::SIMachineFunctionInfoinline
setPrivateSegmentWaveByteOffset(Register Reg)llvm::SIMachineFunctionInfoinline
setScratchRSrcReg(Register Reg)llvm::SIMachineFunctionInfoinline
setSGPRForEXECCopy(Register Reg)llvm::SIMachineFunctionInfoinline
setStackPtrOffsetReg(Register Reg)llvm::SIMachineFunctionInfoinline
setUsesDynamicLDS(bool DynLDS)llvm::AMDGPUMachineFunction
setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy)llvm::SIMachineFunctionInfoinline
setVGPRToAGPRSpillDead(int FrameIndex)llvm::SIMachineFunctionInfoinline
setWorkItemIDX(ArgDescriptor Arg)llvm::SIMachineFunctionInfoinline
setWorkItemIDY(ArgDescriptor Arg)llvm::SIMachineFunctionInfoinline
setWorkItemIDZ(ArgDescriptor Arg)llvm::SIMachineFunctionInfoinline
shiftSpillPhysVGPRsToLowestRange(MachineFunction &MF)llvm::SIMachineFunctionInfo
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI)=defaultllvm::SIMachineFunctionInfo
SIMachineFunctionInfo(const Function &F, const GCNSubtarget *STI)llvm::SIMachineFunctionInfo
splitWWMSpillRegisters(MachineFunction &MF, SmallVectorImpl< std::pair< Register, int > > &CalleeSavedRegs, SmallVectorImpl< std::pair< Register, int > > &ScratchRegs) constllvm::SIMachineFunctionInfo
StaticGDSSizellvm::AMDGPUMachineFunctionprotected
StaticLDSSizellvm::AMDGPUMachineFunctionprotected
usesAGPRs(const MachineFunction &MF) constllvm::SIMachineFunctionInfo
UsesDynamicLDSllvm::AMDGPUMachineFunctionprotected
WaveLimiterllvm::AMDGPUMachineFunctionprotected
~MachineFunctionInfo()llvm::MachineFunctionInfovirtual