addDispatchID(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addDispatchPtr(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addFlatScratchInit(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addImplicitBufferPtr(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addKernargSegmentPtr(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addLDSKernelId() | llvm::SIMachineFunctionInfo | |
addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC, unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs) | llvm::SIMachineFunctionInfo | |
addPrivateSegmentBuffer(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addPrivateSegmentSize(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addPrivateSegmentWaveByteOffset() | llvm::SIMachineFunctionInfo | inline |
addQueuePtr(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addReservedUserSGPR() | llvm::SIMachineFunctionInfo | inline |
addToPrologEpilogSGPRSpills(Register Reg, PrologEpilogSGPRSaveRestoreInfo SI) | llvm::SIMachineFunctionInfo | inline |
addToSpilledSGPRs(unsigned num) | llvm::SIMachineFunctionInfo | inline |
addToSpilledVGPRs(unsigned num) | llvm::SIMachineFunctionInfo | inline |
addWorkGroupIDX() | llvm::SIMachineFunctionInfo | inline |
addWorkGroupIDY() | llvm::SIMachineFunctionInfo | inline |
addWorkGroupIDZ() | llvm::SIMachineFunctionInfo | inline |
addWorkGroupInfo() | llvm::SIMachineFunctionInfo | inline |
allocateLDSGlobal(const DataLayout &DL, const GlobalVariable &GV) | llvm::AMDGPUMachineFunction | inline |
allocateLDSGlobal(const DataLayout &DL, const GlobalVariable &GV, Align Trailing) | llvm::AMDGPUMachineFunction | |
allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, bool SpillToPhysVGPRLane=false, bool IsPrologEpilog=false) | llvm::SIMachineFunctionInfo | |
allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR) | llvm::SIMachineFunctionInfo | |
allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4)) | llvm::SIMachineFunctionInfo | |
AMDGPUMachineFunction(const Function &F, const AMDGPUSubtarget &ST) | llvm::AMDGPUMachineFunction | |
checkFlag(Register Reg, uint8_t Flag) const | llvm::SIMachineFunctionInfo | inline |
checkIndexInPrologEpilogSGPRSpills(int FI) const | llvm::SIMachineFunctionInfo | inline |
clearNonWWMRegAllocMask() | llvm::SIMachineFunctionInfo | inline |
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override | llvm::SIMachineFunctionInfo | virtual |
create(BumpPtrAllocator &Allocator, const Function &F, const SubtargetTy *STI) | llvm::MachineFunctionInfo | inlinestatic |
create(BumpPtrAllocator &Allocator, const Ty &MFI) | llvm::MachineFunctionInfo | inlinestatic |
DynLDSAlign | llvm::AMDGPUMachineFunction | protected |
ExplicitKernArgSize | llvm::AMDGPUMachineFunction | protected |
GCNTargetMachine | llvm::SIMachineFunctionInfo | friend |
GDSSize | llvm::AMDGPUMachineFunction | protected |
get32BitAddressHighBits() const | llvm::SIMachineFunctionInfo | inline |
getAGPRSpillVGPRs() const | llvm::SIMachineFunctionInfo | inline |
getAllScratchSGPRCopyDstRegs(SmallVectorImpl< Register > &Regs) const | llvm::SIMachineFunctionInfo | inline |
getArgInfo() | llvm::SIMachineFunctionInfo | inline |
getArgInfo() const | llvm::SIMachineFunctionInfo | inline |
getBytesInStackArgArea() const | llvm::SIMachineFunctionInfo | inline |
getDynLDSAlign() const | llvm::AMDGPUMachineFunction | inline |
getExplicitKernArgSize() const | llvm::AMDGPUMachineFunction | inline |
getFlatWorkGroupSizes() const | llvm::SIMachineFunctionInfo | inline |
getFrameOffsetReg() const | llvm::SIMachineFunctionInfo | inline |
getGDSSize() const | llvm::AMDGPUMachineFunction | inline |
getGITPtrHigh() const | llvm::SIMachineFunctionInfo | inline |
getGITPtrLoReg(const MachineFunction &MF) const | llvm::SIMachineFunctionInfo | |
getGWSPSV(const AMDGPUTargetMachine &TM) | llvm::SIMachineFunctionInfo | inline |
getImplicitBufferPtrUserSGPR() const | llvm::SIMachineFunctionInfo | inline |
getLDSAbsoluteAddress(const GlobalValue &GV) | llvm::AMDGPUMachineFunction | static |
getLDSKernelIdMetadata(const Function &F) | llvm::AMDGPUMachineFunction | static |
getLDSSize() const | llvm::AMDGPUMachineFunction | inline |
getLongBranchReservedReg() const | llvm::SIMachineFunctionInfo | inline |
getMaxFlatWorkGroupSize() const | llvm::SIMachineFunctionInfo | inline |
getMaxKernArgAlign() const | llvm::AMDGPUMachineFunction | inline |
getMaxMemoryClusterDWords() const | llvm::SIMachineFunctionInfo | inline |
getMaxNumWorkGroups() const | llvm::SIMachineFunctionInfo | inline |
getMaxNumWorkGroupsX() const | llvm::SIMachineFunctionInfo | inline |
getMaxNumWorkGroupsY() const | llvm::SIMachineFunctionInfo | inline |
getMaxNumWorkGroupsZ() const | llvm::SIMachineFunctionInfo | inline |
getMaxWavesPerEU() const | llvm::SIMachineFunctionInfo | inline |
getMinAllowedOccupancy() const | llvm::SIMachineFunctionInfo | inline |
getMinFlatWorkGroupSize() const | llvm::SIMachineFunctionInfo | inline |
getMinWavesPerEU() const | llvm::SIMachineFunctionInfo | inline |
getMode() const | llvm::SIMachineFunctionInfo | inline |
getNonWWMRegMask() const | llvm::SIMachineFunctionInfo | inline |
getNumKernargPreloadedSGPRs() const | llvm::SIMachineFunctionInfo | inline |
getNumPreloadedSGPRs() const | llvm::SIMachineFunctionInfo | inline |
getNumSpilledSGPRs() const | llvm::SIMachineFunctionInfo | inline |
getNumSpilledVGPRs() const | llvm::SIMachineFunctionInfo | inline |
getNumUserSGPRs() const | llvm::SIMachineFunctionInfo | inline |
getOccupancy() const | llvm::SIMachineFunctionInfo | inline |
getOptionalScavengeFI() const | llvm::SIMachineFunctionInfo | inline |
getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const | llvm::SIMachineFunctionInfo | inline |
getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const | llvm::SIMachineFunctionInfo | inline |
getPrivateSegmentWaveByteOffsetSystemSGPR() const | llvm::SIMachineFunctionInfo | inline |
getPrologEpilogSGPRSaveRestoreInfo(Register Reg) const | llvm::SIMachineFunctionInfo | inline |
getPrologEpilogSGPRSpills() const | llvm::SIMachineFunctionInfo | inline |
getPSInputAddr() const | llvm::SIMachineFunctionInfo | inline |
getPSInputEnable() const | llvm::SIMachineFunctionInfo | inline |
getQueuePtrUserSGPR() const | llvm::SIMachineFunctionInfo | inline |
getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
getScratchRSrcReg() const | llvm::SIMachineFunctionInfo | inline |
getScratchSGPRCopyDstReg(Register Reg) const | llvm::SIMachineFunctionInfo | inline |
getSGPRForEXECCopy() const | llvm::SIMachineFunctionInfo | inline |
getSGPRSpillPhysVGPRs() const | llvm::SIMachineFunctionInfo | inline |
getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const | llvm::SIMachineFunctionInfo | inline |
getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const | llvm::SIMachineFunctionInfo | inline |
getSGPRSpillVGPRs() const | llvm::SIMachineFunctionInfo | inline |
getStackPtrOffsetReg() const | llvm::SIMachineFunctionInfo | inline |
getUserSGPRInfo() | llvm::SIMachineFunctionInfo | inline |
getUserSGPRInfo() const | llvm::SIMachineFunctionInfo | inline |
getVGPRForAGPRCopy() const | llvm::SIMachineFunctionInfo | inline |
getVGPRSpillAGPRs() const | llvm::SIMachineFunctionInfo | inline |
getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const | llvm::SIMachineFunctionInfo | inline |
getWavesPerEU() const | llvm::SIMachineFunctionInfo | inline |
getWWMReservedRegs() const | llvm::SIMachineFunctionInfo | inline |
getWWMSpills() const | llvm::SIMachineFunctionInfo | inline |
hasImplicitArgPtr() const | llvm::SIMachineFunctionInfo | inline |
HasInitWholeWave | llvm::AMDGPUMachineFunction | protected |
hasInitWholeWave() const | llvm::AMDGPUMachineFunction | inline |
hasLDSKernelId() const | llvm::SIMachineFunctionInfo | inline |
hasNonSpillStackObjects() const | llvm::SIMachineFunctionInfo | inline |
hasNoSignedZerosFPMath() const | llvm::AMDGPUMachineFunction | inline |
hasPrivateSegmentWaveByteOffset() const | llvm::SIMachineFunctionInfo | inline |
hasPrologEpilogSGPRSpillEntry(Register Reg) const | llvm::SIMachineFunctionInfo | inline |
hasSpilledSGPRs() const | llvm::SIMachineFunctionInfo | inline |
hasSpilledVGPRs() const | llvm::SIMachineFunctionInfo | inline |
hasVRegFlags() | llvm::SIMachineFunctionInfo | inline |
hasWorkGroupIDX() const | llvm::SIMachineFunctionInfo | inline |
hasWorkGroupIDY() const | llvm::SIMachineFunctionInfo | inline |
hasWorkGroupIDZ() const | llvm::SIMachineFunctionInfo | inline |
hasWorkGroupInfo() const | llvm::SIMachineFunctionInfo | inline |
hasWorkItemIDX() const | llvm::SIMachineFunctionInfo | inline |
hasWorkItemIDY() const | llvm::SIMachineFunctionInfo | inline |
hasWorkItemIDZ() const | llvm::SIMachineFunctionInfo | inline |
increaseOccupancy(const MachineFunction &MF, unsigned Limit) | llvm::SIMachineFunctionInfo | inline |
initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) | llvm::SIMachineFunctionInfo | |
isBottomOfStack() const | llvm::AMDGPUMachineFunction | inline |
isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const | llvm::SIMachineFunctionInfo | |
isChainFunction() const | llvm::AMDGPUMachineFunction | inline |
IsChainFunction | llvm::AMDGPUMachineFunction | protected |
isDynamicLDSUsed() const | llvm::AMDGPUMachineFunction | |
isEntryFunction() const | llvm::AMDGPUMachineFunction | inline |
IsEntryFunction | llvm::AMDGPUMachineFunction | protected |
isMemoryBound() const | llvm::AMDGPUMachineFunction | inline |
isModuleEntryFunction() const | llvm::AMDGPUMachineFunction | inline |
IsModuleEntryFunction | llvm::AMDGPUMachineFunction | protected |
isPSInputAllocated(unsigned Index) const | llvm::SIMachineFunctionInfo | inline |
isStackRealigned() const | llvm::SIMachineFunctionInfo | inline |
isWWMReg(Register Reg) const | llvm::SIMachineFunctionInfo | inline |
LDSSize | llvm::AMDGPUMachineFunction | protected |
limitOccupancy(const MachineFunction &MF) | llvm::SIMachineFunctionInfo | |
limitOccupancy(unsigned Limit) | llvm::SIMachineFunctionInfo | inline |
markPSInputAllocated(unsigned Index) | llvm::SIMachineFunctionInfo | inline |
markPSInputEnabled(unsigned Index) | llvm::SIMachineFunctionInfo | inline |
MaxKernArgAlign | llvm::AMDGPUMachineFunction | protected |
mayNeedAGPRs() const | llvm::SIMachineFunctionInfo | inline |
mayUseAGPRs(const Function &F) const | llvm::SIMachineFunctionInfo | |
MemoryBound | llvm::AMDGPUMachineFunction | protected |
needsWaveLimiter() const | llvm::AMDGPUMachineFunction | inline |
NoSignedZerosFPMath | llvm::AMDGPUMachineFunction | protected |
removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) | llvm::SIMachineFunctionInfo | |
reserveWWMRegister(Register Reg) | llvm::SIMachineFunctionInfo | inline |
returnsVoid() const | llvm::SIMachineFunctionInfo | inline |
setBytesInStackArgArea(unsigned Bytes) | llvm::SIMachineFunctionInfo | inline |
setDynLDSAlign(const Function &F, const GlobalVariable &GV) | llvm::AMDGPUMachineFunction | |
setFlag(Register Reg, uint8_t Flag) | llvm::SIMachineFunctionInfo | inline |
setFrameOffsetReg(Register Reg) | llvm::SIMachineFunctionInfo | inline |
setHasNonSpillStackObjects(bool StackObject=true) | llvm::SIMachineFunctionInfo | inline |
setHasSpilledSGPRs(bool Spill=true) | llvm::SIMachineFunctionInfo | inline |
setHasSpilledVGPRs(bool Spill=true) | llvm::SIMachineFunctionInfo | inline |
setIfReturnsVoid(bool Value) | llvm::SIMachineFunctionInfo | inline |
setInitWholeWave() | llvm::AMDGPUMachineFunction | inline |
setIsStackRealigned(bool Realigned=true) | llvm::SIMachineFunctionInfo | inline |
setLongBranchReservedReg(Register Reg) | llvm::SIMachineFunctionInfo | inline |
setPrivateSegmentWaveByteOffset(Register Reg) | llvm::SIMachineFunctionInfo | inline |
setScratchRSrcReg(Register Reg) | llvm::SIMachineFunctionInfo | inline |
setSGPRForEXECCopy(Register Reg) | llvm::SIMachineFunctionInfo | inline |
setStackPtrOffsetReg(Register Reg) | llvm::SIMachineFunctionInfo | inline |
setUsesDynamicLDS(bool DynLDS) | llvm::AMDGPUMachineFunction | |
setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) | llvm::SIMachineFunctionInfo | inline |
setVGPRToAGPRSpillDead(int FrameIndex) | llvm::SIMachineFunctionInfo | inline |
setWorkItemIDX(ArgDescriptor Arg) | llvm::SIMachineFunctionInfo | inline |
setWorkItemIDY(ArgDescriptor Arg) | llvm::SIMachineFunctionInfo | inline |
setWorkItemIDZ(ArgDescriptor Arg) | llvm::SIMachineFunctionInfo | inline |
shiftWwmVGPRsToLowestRange(MachineFunction &MF, SmallVectorImpl< Register > &WWMVGPRs, BitVector &SavedVGPRs) | llvm::SIMachineFunctionInfo | |
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI)=default | llvm::SIMachineFunctionInfo | |
SIMachineFunctionInfo(const Function &F, const GCNSubtarget *STI) | llvm::SIMachineFunctionInfo | |
splitWWMSpillRegisters(MachineFunction &MF, SmallVectorImpl< std::pair< Register, int > > &CalleeSavedRegs, SmallVectorImpl< std::pair< Register, int > > &ScratchRegs) const | llvm::SIMachineFunctionInfo | |
StaticGDSSize | llvm::AMDGPUMachineFunction | protected |
StaticLDSSize | llvm::AMDGPUMachineFunction | protected |
updateNonWWMRegMask(BitVector &RegMask) | llvm::SIMachineFunctionInfo | inline |
usesAGPRs(const MachineFunction &MF) const | llvm::SIMachineFunctionInfo | |
UsesDynamicLDS | llvm::AMDGPUMachineFunction | protected |
WaveLimiter | llvm::AMDGPUMachineFunction | protected |
~MachineFunctionInfo() | llvm::MachineFunctionInfo | virtual |