LLVM 19.0.0git
llvm::RISCVRegisterInfo Member List

This is the complete list of members for llvm::RISCVRegisterInfo, including all inherited members.

adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) constllvm::RISCVRegisterInfo
doesRegClassHavePseudoInitUndef(const TargetRegisterClass *RC) const overridellvm::RISCVRegisterInfoinline
eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const overridellvm::RISCVRegisterInfo
getCalleeSavedRegs(const MachineFunction *MF) const overridellvm::RISCVRegisterInfo
getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const overridellvm::RISCVRegisterInfo
getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const overridellvm::RISCVRegisterInfo
getFrameRegister(const MachineFunction &MF) const overridellvm::RISCVRegisterInfo
getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const overridellvm::RISCVRegisterInfo
getLargestSuperClass(const TargetRegisterClass *RC) const overridellvm::RISCVRegisterInfoinline
getNoPreservedMask() const overridellvm::RISCVRegisterInfo
getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const overridellvm::RISCVRegisterInfo
getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const overridellvm::RISCVRegisterInfoinline
getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const overridellvm::RISCVRegisterInfo
getRegisterCostTableIndex(const MachineFunction &MF) const overridellvm::RISCVRegisterInfo
getReservedRegs(const MachineFunction &MF) const overridellvm::RISCVRegisterInfo
isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const overridellvm::RISCVRegisterInfo
isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const overridellvm::RISCVRegisterInfo
lowerVRELOAD(MachineBasicBlock::iterator II) constllvm::RISCVRegisterInfo
lowerVSPILL(MachineBasicBlock::iterator II) constllvm::RISCVRegisterInfo
materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const overridellvm::RISCVRegisterInfo
needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const overridellvm::RISCVRegisterInfo
requiresFrameIndexScavenging(const MachineFunction &MF) const overridellvm::RISCVRegisterInfoinline
requiresRegisterScavenging(const MachineFunction &MF) const overridellvm::RISCVRegisterInfoinline
requiresVirtualBaseRegisters(const MachineFunction &MF) const overridellvm::RISCVRegisterInfo
resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const overridellvm::RISCVRegisterInfo
RISCVRegisterInfo(unsigned HwMode)llvm::RISCVRegisterInfo