LLVM  16.0.0git
llvm::RISCVRegisterInfo Member List

This is the complete list of members for llvm::RISCVRegisterInfo, including all inherited members.

adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DestReg, Register SrcReg, int64_t Val, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) constllvm::RISCVRegisterInfo
adjustReg(MachineBasicBlock::iterator II, Register DestReg, Register SrcReg, StackOffset Offset) constllvm::RISCVRegisterInfo
eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const overridellvm::RISCVRegisterInfo
getCalleeSavedRegs(const MachineFunction *MF) const overridellvm::RISCVRegisterInfo
getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const overridellvm::RISCVRegisterInfo
getFrameRegister(const MachineFunction &MF) const overridellvm::RISCVRegisterInfo
getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const overridellvm::RISCVRegisterInfo
getNoPreservedMask() const overridellvm::RISCVRegisterInfo
getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const overridellvm::RISCVRegisterInfo
getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const overridellvm::RISCVRegisterInfoinline
getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const overridellvm::RISCVRegisterInfo
getRegisterCostTableIndex(const MachineFunction &MF) const overridellvm::RISCVRegisterInfo
getReservedRegs(const MachineFunction &MF) const overridellvm::RISCVRegisterInfo
hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const overridellvm::RISCVRegisterInfo
isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const overridellvm::RISCVRegisterInfo
requiresFrameIndexScavenging(const MachineFunction &MF) const overridellvm::RISCVRegisterInfoinline
requiresRegisterScavenging(const MachineFunction &MF) const overridellvm::RISCVRegisterInfoinline
RISCVRegisterInfo(unsigned HwMode)llvm::RISCVRegisterInfo