Line data Source code
1 : //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : /// \file
11 : /// This file implements the InstructionSelector class.
12 : //
13 : //===----------------------------------------------------------------------===//
14 :
15 : #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
16 : #include "llvm/CodeGen/GlobalISel/Utils.h"
17 : #include "llvm/CodeGen/MachineBasicBlock.h"
18 : #include "llvm/CodeGen/MachineFunction.h"
19 : #include "llvm/CodeGen/MachineInstr.h"
20 : #include "llvm/CodeGen/MachineOperand.h"
21 : #include "llvm/CodeGen/MachineRegisterInfo.h"
22 : #include "llvm/CodeGen/TargetRegisterInfo.h"
23 : #include "llvm/MC/MCInstrDesc.h"
24 : #include "llvm/Support/Debug.h"
25 : #include "llvm/Support/raw_ostream.h"
26 : #include <cassert>
27 :
28 : #define DEBUG_TYPE "instructionselector"
29 :
30 : using namespace llvm;
31 :
32 35702 : InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers)
33 35702 : : Renderers(MaxRenderers), MIs() {}
34 :
35 : InstructionSelector::InstructionSelector() = default;
36 :
37 308 : bool InstructionSelector::constrainOperandRegToRegClass(
38 : MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
39 : const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
40 : const RegisterBankInfo &RBI) const {
41 308 : MachineBasicBlock &MBB = *I.getParent();
42 308 : MachineFunction &MF = *MBB.getParent();
43 308 : MachineRegisterInfo &MRI = MF.getRegInfo();
44 :
45 : return
46 616 : constrainRegToClass(MRI, TII, RBI, I, I.getOperand(OpIdx).getReg(), RC);
47 : }
48 :
49 492 : bool InstructionSelector::isOperandImmEqual(
50 : const MachineOperand &MO, int64_t Value,
51 : const MachineRegisterInfo &MRI) const {
52 492 : if (MO.isReg() && MO.getReg())
53 492 : if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
54 210 : return *VRegVal == Value;
55 : return false;
56 : }
57 :
58 365 : bool InstructionSelector::isBaseWithConstantOffset(
59 : const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
60 365 : if (!Root.isReg())
61 : return false;
62 :
63 365 : MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
64 730 : if (RootI->getOpcode() != TargetOpcode::G_GEP)
65 : return false;
66 :
67 189 : MachineOperand &RHS = RootI->getOperand(2);
68 189 : MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
69 378 : if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT)
70 0 : return false;
71 :
72 : return true;
73 : }
74 :
75 240 : bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI,
76 : MachineInstr &IntoMI) const {
77 : // Immediate neighbours are already folded.
78 480 : if (MI.getParent() == IntoMI.getParent() &&
79 240 : std::next(MI.getIterator()) == IntoMI.getIterator())
80 : return true;
81 :
82 230 : return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
83 : MI.implicit_operands().begin() == MI.implicit_operands().end();
84 : }
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