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1 : //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file contains small standalone helper functions and enum definitions for
11 : // the AArch64 target useful for the compiler back-end and the MC libraries.
12 : // As such, it deliberately does not include references to LLVM core
13 : // code gen types, passes, etc..
14 : //
15 : //===----------------------------------------------------------------------===//
16 :
17 : #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18 : #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
19 :
20 : // FIXME: Is it easiest to fix this layering violation by moving the .inc
21 : // #includes from AArch64MCTargetDesc.h to here?
22 : #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
23 : #include "llvm/ADT/STLExtras.h"
24 : #include "llvm/ADT/StringSwitch.h"
25 : #include "llvm/MC/SubtargetFeature.h"
26 : #include "llvm/Support/ErrorHandling.h"
27 :
28 : namespace llvm {
29 :
30 463 : inline static unsigned getWRegFromXReg(unsigned Reg) {
31 463 : switch (Reg) {
32 : case AArch64::X0: return AArch64::W0;
33 26 : case AArch64::X1: return AArch64::W1;
34 7 : case AArch64::X2: return AArch64::W2;
35 6 : case AArch64::X3: return AArch64::W3;
36 0 : case AArch64::X4: return AArch64::W4;
37 2 : case AArch64::X5: return AArch64::W5;
38 0 : case AArch64::X6: return AArch64::W6;
39 0 : case AArch64::X7: return AArch64::W7;
40 14 : case AArch64::X8: return AArch64::W8;
41 4 : case AArch64::X9: return AArch64::W9;
42 0 : case AArch64::X10: return AArch64::W10;
43 0 : case AArch64::X11: return AArch64::W11;
44 0 : case AArch64::X12: return AArch64::W12;
45 0 : case AArch64::X13: return AArch64::W13;
46 0 : case AArch64::X14: return AArch64::W14;
47 0 : case AArch64::X15: return AArch64::W15;
48 0 : case AArch64::X16: return AArch64::W16;
49 0 : case AArch64::X17: return AArch64::W17;
50 0 : case AArch64::X18: return AArch64::W18;
51 0 : case AArch64::X19: return AArch64::W19;
52 0 : case AArch64::X20: return AArch64::W20;
53 0 : case AArch64::X21: return AArch64::W21;
54 1 : case AArch64::X22: return AArch64::W22;
55 0 : case AArch64::X23: return AArch64::W23;
56 0 : case AArch64::X24: return AArch64::W24;
57 0 : case AArch64::X25: return AArch64::W25;
58 0 : case AArch64::X26: return AArch64::W26;
59 0 : case AArch64::X27: return AArch64::W27;
60 0 : case AArch64::X28: return AArch64::W28;
61 0 : case AArch64::FP: return AArch64::W29;
62 5 : case AArch64::LR: return AArch64::W30;
63 1 : case AArch64::SP: return AArch64::WSP;
64 18 : case AArch64::XZR: return AArch64::WZR;
65 : }
66 : // For anything else, return it unchanged.
67 266 : return Reg;
68 : }
69 :
70 256 : inline static unsigned getXRegFromWReg(unsigned Reg) {
71 256 : switch (Reg) {
72 : case AArch64::W0: return AArch64::X0;
73 21 : case AArch64::W1: return AArch64::X1;
74 4 : case AArch64::W2: return AArch64::X2;
75 1 : case AArch64::W3: return AArch64::X3;
76 0 : case AArch64::W4: return AArch64::X4;
77 0 : case AArch64::W5: return AArch64::X5;
78 0 : case AArch64::W6: return AArch64::X6;
79 0 : case AArch64::W7: return AArch64::X7;
80 3 : case AArch64::W8: return AArch64::X8;
81 0 : case AArch64::W9: return AArch64::X9;
82 2 : case AArch64::W10: return AArch64::X10;
83 0 : case AArch64::W11: return AArch64::X11;
84 0 : case AArch64::W12: return AArch64::X12;
85 0 : case AArch64::W13: return AArch64::X13;
86 0 : case AArch64::W14: return AArch64::X14;
87 0 : case AArch64::W15: return AArch64::X15;
88 0 : case AArch64::W16: return AArch64::X16;
89 0 : case AArch64::W17: return AArch64::X17;
90 0 : case AArch64::W18: return AArch64::X18;
91 2 : case AArch64::W19: return AArch64::X19;
92 2 : case AArch64::W20: return AArch64::X20;
93 1 : case AArch64::W21: return AArch64::X21;
94 1 : case AArch64::W22: return AArch64::X22;
95 1 : case AArch64::W23: return AArch64::X23;
96 1 : case AArch64::W24: return AArch64::X24;
97 1 : case AArch64::W25: return AArch64::X25;
98 1 : case AArch64::W26: return AArch64::X26;
99 2 : case AArch64::W27: return AArch64::X27;
100 2 : case AArch64::W28: return AArch64::X28;
101 9 : case AArch64::W29: return AArch64::FP;
102 3 : case AArch64::W30: return AArch64::LR;
103 0 : case AArch64::WSP: return AArch64::SP;
104 28 : case AArch64::WZR: return AArch64::XZR;
105 : }
106 : // For anything else, return it unchanged.
107 23 : return Reg;
108 : }
109 :
110 : static inline unsigned getBRegFromDReg(unsigned Reg) {
111 : switch (Reg) {
112 : case AArch64::D0: return AArch64::B0;
113 : case AArch64::D1: return AArch64::B1;
114 : case AArch64::D2: return AArch64::B2;
115 : case AArch64::D3: return AArch64::B3;
116 : case AArch64::D4: return AArch64::B4;
117 : case AArch64::D5: return AArch64::B5;
118 : case AArch64::D6: return AArch64::B6;
119 : case AArch64::D7: return AArch64::B7;
120 : case AArch64::D8: return AArch64::B8;
121 : case AArch64::D9: return AArch64::B9;
122 : case AArch64::D10: return AArch64::B10;
123 : case AArch64::D11: return AArch64::B11;
124 : case AArch64::D12: return AArch64::B12;
125 : case AArch64::D13: return AArch64::B13;
126 : case AArch64::D14: return AArch64::B14;
127 : case AArch64::D15: return AArch64::B15;
128 : case AArch64::D16: return AArch64::B16;
129 : case AArch64::D17: return AArch64::B17;
130 : case AArch64::D18: return AArch64::B18;
131 : case AArch64::D19: return AArch64::B19;
132 : case AArch64::D20: return AArch64::B20;
133 : case AArch64::D21: return AArch64::B21;
134 : case AArch64::D22: return AArch64::B22;
135 : case AArch64::D23: return AArch64::B23;
136 : case AArch64::D24: return AArch64::B24;
137 : case AArch64::D25: return AArch64::B25;
138 : case AArch64::D26: return AArch64::B26;
139 : case AArch64::D27: return AArch64::B27;
140 : case AArch64::D28: return AArch64::B28;
141 : case AArch64::D29: return AArch64::B29;
142 : case AArch64::D30: return AArch64::B30;
143 : case AArch64::D31: return AArch64::B31;
144 : }
145 : // For anything else, return it unchanged.
146 : return Reg;
147 : }
148 :
149 :
150 : static inline unsigned getDRegFromBReg(unsigned Reg) {
151 : switch (Reg) {
152 : case AArch64::B0: return AArch64::D0;
153 : case AArch64::B1: return AArch64::D1;
154 : case AArch64::B2: return AArch64::D2;
155 : case AArch64::B3: return AArch64::D3;
156 : case AArch64::B4: return AArch64::D4;
157 : case AArch64::B5: return AArch64::D5;
158 : case AArch64::B6: return AArch64::D6;
159 : case AArch64::B7: return AArch64::D7;
160 : case AArch64::B8: return AArch64::D8;
161 : case AArch64::B9: return AArch64::D9;
162 : case AArch64::B10: return AArch64::D10;
163 : case AArch64::B11: return AArch64::D11;
164 : case AArch64::B12: return AArch64::D12;
165 : case AArch64::B13: return AArch64::D13;
166 : case AArch64::B14: return AArch64::D14;
167 : case AArch64::B15: return AArch64::D15;
168 : case AArch64::B16: return AArch64::D16;
169 : case AArch64::B17: return AArch64::D17;
170 : case AArch64::B18: return AArch64::D18;
171 : case AArch64::B19: return AArch64::D19;
172 : case AArch64::B20: return AArch64::D20;
173 : case AArch64::B21: return AArch64::D21;
174 : case AArch64::B22: return AArch64::D22;
175 : case AArch64::B23: return AArch64::D23;
176 : case AArch64::B24: return AArch64::D24;
177 : case AArch64::B25: return AArch64::D25;
178 : case AArch64::B26: return AArch64::D26;
179 : case AArch64::B27: return AArch64::D27;
180 : case AArch64::B28: return AArch64::D28;
181 : case AArch64::B29: return AArch64::D29;
182 : case AArch64::B30: return AArch64::D30;
183 : case AArch64::B31: return AArch64::D31;
184 : }
185 : // For anything else, return it unchanged.
186 : return Reg;
187 : }
188 :
189 : namespace AArch64CC {
190 :
191 : // The CondCodes constants map directly to the 4-bit encoding of the condition
192 : // field for predicated instructions.
193 : enum CondCode { // Meaning (integer) Meaning (floating-point)
194 : EQ = 0x0, // Equal Equal
195 : NE = 0x1, // Not equal Not equal, or unordered
196 : HS = 0x2, // Unsigned higher or same >, ==, or unordered
197 : LO = 0x3, // Unsigned lower Less than
198 : MI = 0x4, // Minus, negative Less than
199 : PL = 0x5, // Plus, positive or zero >, ==, or unordered
200 : VS = 0x6, // Overflow Unordered
201 : VC = 0x7, // No overflow Not unordered
202 : HI = 0x8, // Unsigned higher Greater than, or unordered
203 : LS = 0x9, // Unsigned lower or same Less than or equal
204 : GE = 0xa, // Greater than or equal Greater than or equal
205 : LT = 0xb, // Less than Less than, or unordered
206 : GT = 0xc, // Greater than Greater than
207 : LE = 0xd, // Less than or equal <, ==, or unordered
208 : AL = 0xe, // Always (unconditional) Always (unconditional)
209 : NV = 0xf, // Always (unconditional) Always (unconditional)
210 : // Note the NV exists purely to disassemble 0b1111. Execution is "always".
211 : Invalid
212 : };
213 :
214 2487 : inline static const char *getCondCodeName(CondCode Code) {
215 2487 : switch (Code) {
216 0 : default: llvm_unreachable("Unknown condition code");
217 : case EQ: return "eq";
218 490 : case NE: return "ne";
219 122 : case HS: return "hs";
220 122 : case LO: return "lo";
221 130 : case MI: return "mi";
222 56 : case PL: return "pl";
223 81 : case VS: return "vs";
224 77 : case VC: return "vc";
225 110 : case HI: return "hi";
226 86 : case LS: return "ls";
227 125 : case GE: return "ge";
228 216 : case LT: return "lt";
229 215 : case GT: return "gt";
230 176 : case LE: return "le";
231 21 : case AL: return "al";
232 20 : case NV: return "nv";
233 : }
234 : }
235 :
236 : inline static CondCode getInvertedCondCode(CondCode Code) {
237 : // To reverse a condition it's necessary to only invert the low bit:
238 :
239 2943 : return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
240 : }
241 :
242 : /// Given a condition code, return NZCV flags that would satisfy that condition.
243 : /// The flag bits are in the format expected by the ccmp instructions.
244 : /// Note that many different flag settings can satisfy a given condition code,
245 : /// this function just returns one of them.
246 : inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
247 : // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
248 : enum { N = 8, Z = 4, C = 2, V = 1 };
249 : switch (Code) {
250 0 : default: llvm_unreachable("Unknown condition code");
251 : case EQ: return Z; // Z == 1
252 : case NE: return 0; // Z == 0
253 : case HS: return C; // C == 1
254 : case LO: return 0; // C == 0
255 : case MI: return N; // N == 1
256 : case PL: return 0; // N == 0
257 : case VS: return V; // V == 1
258 : case VC: return 0; // V == 0
259 : case HI: return C; // C == 1 && Z == 0
260 : case LS: return 0; // C == 0 || Z == 1
261 : case GE: return 0; // N == V
262 : case LT: return N; // N != V
263 : case GT: return 0; // Z == 0 && N == V
264 : case LE: return Z; // Z == 1 || N != V
265 : }
266 : }
267 : } // end namespace AArch64CC
268 :
269 : struct SysAlias {
270 : const char *Name;
271 : uint16_t Encoding;
272 : FeatureBitset FeaturesRequired;
273 :
274 : SysAlias (const char *N, uint16_t E) : Name(N), Encoding(E) {};
275 : SysAlias (const char *N, uint16_t E, FeatureBitset F) :
276 : Name(N), Encoding(E), FeaturesRequired(F) {};
277 :
278 : bool haveFeatures(FeatureBitset ActiveFeatures) const {
279 915 : return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
280 : }
281 :
282 93 : FeatureBitset getRequiredFeatures() const { return FeaturesRequired; }
283 : };
284 :
285 : struct SysAliasReg : SysAlias {
286 : bool NeedsReg;
287 : SysAliasReg(const char *N, uint16_t E, bool R) : SysAlias(N, E), NeedsReg(R) {};
288 : SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F) : SysAlias(N, E, F),
289 : NeedsReg(R) {};
290 : };
291 :
292 : namespace AArch64AT{
293 : struct AT : SysAlias {
294 : using SysAlias::SysAlias;
295 : };
296 : #define GET_AT_DECL
297 : #include "AArch64GenSystemOperands.inc"
298 : }
299 :
300 : namespace AArch64DB {
301 : struct DB : SysAlias {
302 : using SysAlias::SysAlias;
303 : };
304 : #define GET_DB_DECL
305 : #include "AArch64GenSystemOperands.inc"
306 : }
307 :
308 : namespace AArch64DC {
309 : struct DC : SysAlias {
310 : using SysAlias::SysAlias;
311 : };
312 : #define GET_DC_DECL
313 : #include "AArch64GenSystemOperands.inc"
314 : }
315 :
316 : namespace AArch64IC {
317 : struct IC : SysAliasReg {
318 : using SysAliasReg::SysAliasReg;
319 : };
320 : #define GET_IC_DECL
321 : #include "AArch64GenSystemOperands.inc"
322 : }
323 :
324 : namespace AArch64ISB {
325 : struct ISB : SysAlias {
326 : using SysAlias::SysAlias;
327 : };
328 : #define GET_ISB_DECL
329 : #include "AArch64GenSystemOperands.inc"
330 : }
331 :
332 : namespace AArch64TSB {
333 : struct TSB : SysAlias {
334 : using SysAlias::SysAlias;
335 : };
336 : #define GET_TSB_DECL
337 : #include "AArch64GenSystemOperands.inc"
338 : }
339 :
340 : namespace AArch64PRFM {
341 : struct PRFM : SysAlias {
342 : using SysAlias::SysAlias;
343 : };
344 : #define GET_PRFM_DECL
345 : #include "AArch64GenSystemOperands.inc"
346 : }
347 :
348 : namespace AArch64SVEPRFM {
349 : struct SVEPRFM : SysAlias {
350 : using SysAlias::SysAlias;
351 : };
352 : #define GET_SVEPRFM_DECL
353 : #include "AArch64GenSystemOperands.inc"
354 : }
355 :
356 : namespace AArch64SVEPredPattern {
357 : struct SVEPREDPAT {
358 : const char *Name;
359 : uint16_t Encoding;
360 : };
361 : #define GET_SVEPREDPAT_DECL
362 : #include "AArch64GenSystemOperands.inc"
363 : }
364 :
365 : namespace AArch64ExactFPImm {
366 : struct ExactFPImm {
367 : const char *Name;
368 : int Enum;
369 : const char *Repr;
370 : };
371 : #define GET_EXACTFPIMM_DECL
372 : #include "AArch64GenSystemOperands.inc"
373 : }
374 :
375 : namespace AArch64PState {
376 : struct PState : SysAlias{
377 : using SysAlias::SysAlias;
378 : };
379 : #define GET_PSTATE_DECL
380 : #include "AArch64GenSystemOperands.inc"
381 : }
382 :
383 : namespace AArch64PSBHint {
384 : struct PSB : SysAlias {
385 : using SysAlias::SysAlias;
386 : };
387 : #define GET_PSB_DECL
388 : #include "AArch64GenSystemOperands.inc"
389 : }
390 :
391 : namespace AArch64BTIHint {
392 : struct BTI : SysAlias {
393 : using SysAlias::SysAlias;
394 : };
395 : #define GET_BTI_DECL
396 : #include "AArch64GenSystemOperands.inc"
397 : }
398 :
399 : namespace AArch64SE {
400 : enum ShiftExtSpecifiers {
401 : Invalid = -1,
402 : LSL,
403 : MSL,
404 : LSR,
405 : ASR,
406 : ROR,
407 :
408 : UXTB,
409 : UXTH,
410 : UXTW,
411 : UXTX,
412 :
413 : SXTB,
414 : SXTH,
415 : SXTW,
416 : SXTX
417 : };
418 : }
419 :
420 : namespace AArch64Layout {
421 : enum VectorLayout {
422 : Invalid = -1,
423 : VL_8B,
424 : VL_4H,
425 : VL_2S,
426 : VL_1D,
427 :
428 : VL_16B,
429 : VL_8H,
430 : VL_4S,
431 : VL_2D,
432 :
433 : // Bare layout for the 128-bit vector
434 : // (only show ".b", ".h", ".s", ".d" without vector number)
435 : VL_B,
436 : VL_H,
437 : VL_S,
438 : VL_D
439 : };
440 : }
441 :
442 : inline static const char *
443 : AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
444 : switch (Layout) {
445 : case AArch64Layout::VL_8B: return ".8b";
446 : case AArch64Layout::VL_4H: return ".4h";
447 : case AArch64Layout::VL_2S: return ".2s";
448 : case AArch64Layout::VL_1D: return ".1d";
449 : case AArch64Layout::VL_16B: return ".16b";
450 : case AArch64Layout::VL_8H: return ".8h";
451 : case AArch64Layout::VL_4S: return ".4s";
452 : case AArch64Layout::VL_2D: return ".2d";
453 : case AArch64Layout::VL_B: return ".b";
454 : case AArch64Layout::VL_H: return ".h";
455 : case AArch64Layout::VL_S: return ".s";
456 : case AArch64Layout::VL_D: return ".d";
457 : default: llvm_unreachable("Unknown Vector Layout");
458 : }
459 : }
460 :
461 : inline static AArch64Layout::VectorLayout
462 : AArch64StringToVectorLayout(StringRef LayoutStr) {
463 : return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
464 : .Case(".8b", AArch64Layout::VL_8B)
465 : .Case(".4h", AArch64Layout::VL_4H)
466 : .Case(".2s", AArch64Layout::VL_2S)
467 : .Case(".1d", AArch64Layout::VL_1D)
468 : .Case(".16b", AArch64Layout::VL_16B)
469 : .Case(".8h", AArch64Layout::VL_8H)
470 : .Case(".4s", AArch64Layout::VL_4S)
471 : .Case(".2d", AArch64Layout::VL_2D)
472 : .Case(".b", AArch64Layout::VL_B)
473 : .Case(".h", AArch64Layout::VL_H)
474 : .Case(".s", AArch64Layout::VL_S)
475 : .Case(".d", AArch64Layout::VL_D)
476 : .Default(AArch64Layout::Invalid);
477 : }
478 :
479 : namespace AArch64SysReg {
480 : struct SysReg {
481 : const char *Name;
482 : unsigned Encoding;
483 : bool Readable;
484 : bool Writeable;
485 : FeatureBitset FeaturesRequired;
486 :
487 : bool haveFeatures(FeatureBitset ActiveFeatures) const {
488 8137 : return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
489 : }
490 : };
491 :
492 : #define GET_SYSREG_DECL
493 : #include "AArch64GenSystemOperands.inc"
494 :
495 : const SysReg *lookupSysRegByName(StringRef);
496 : const SysReg *lookupSysRegByEncoding(uint16_t);
497 :
498 : uint32_t parseGenericRegister(StringRef Name);
499 : std::string genericRegisterString(uint32_t Bits);
500 : }
501 :
502 : namespace AArch64TLBI {
503 : struct TLBI : SysAliasReg {
504 : using SysAliasReg::SysAliasReg;
505 : };
506 : #define GET_TLBI_DECL
507 : #include "AArch64GenSystemOperands.inc"
508 : }
509 :
510 : namespace AArch64PRCTX {
511 : struct PRCTX : SysAliasReg {
512 : using SysAliasReg::SysAliasReg;
513 : };
514 : #define GET_PRCTX_DECL
515 : #include "AArch64GenSystemOperands.inc"
516 : }
517 :
518 : namespace AArch64II {
519 : /// Target Operand Flag enum.
520 : enum TOF {
521 : //===------------------------------------------------------------------===//
522 : // AArch64 Specific MachineOperand flags.
523 :
524 : MO_NO_FLAG,
525 :
526 : MO_FRAGMENT = 0x7,
527 :
528 : /// MO_PAGE - A symbol operand with this flag represents the pc-relative
529 : /// offset of the 4K page containing the symbol. This is used with the
530 : /// ADRP instruction.
531 : MO_PAGE = 1,
532 :
533 : /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
534 : /// that symbol within a 4K page. This offset is added to the page address
535 : /// to produce the complete address.
536 : MO_PAGEOFF = 2,
537 :
538 : /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
539 : /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
540 : MO_G3 = 3,
541 :
542 : /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
543 : /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
544 : MO_G2 = 4,
545 :
546 : /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
547 : /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
548 : MO_G1 = 5,
549 :
550 : /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
551 : /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
552 : MO_G0 = 6,
553 :
554 : /// MO_HI12 - This flag indicates that a symbol operand represents the bits
555 : /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
556 : /// by-12-bits instruction.
557 : MO_HI12 = 7,
558 :
559 : /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
560 : /// reference is actually to the ".refptrp.FOO" symbol. This is used for
561 : /// stub symbols on windows.
562 : MO_COFFSTUB = 0x8,
563 :
564 : /// MO_GOT - This flag indicates that a symbol operand represents the
565 : /// address of the GOT entry for the symbol, rather than the address of
566 : /// the symbol itself.
567 : MO_GOT = 0x10,
568 :
569 : /// MO_NC - Indicates whether the linker is expected to check the symbol
570 : /// reference for overflow. For example in an ADRP/ADD pair of relocations
571 : /// the ADRP usually does check, but not the ADD.
572 : MO_NC = 0x20,
573 :
574 : /// MO_TLS - Indicates that the operand being accessed is some kind of
575 : /// thread-local symbol. On Darwin, only one type of thread-local access
576 : /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
577 : /// referee will affect interpretation.
578 : MO_TLS = 0x40,
579 :
580 : /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
581 : /// to the symbol is for an import stub. This is used for DLL import
582 : /// storage class indication on Windows.
583 : MO_DLLIMPORT = 0x80,
584 : };
585 : } // end namespace AArch64II
586 :
587 : } // end namespace llvm
588 :
589 : #endif
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