24#define DEBUG_TYPE "CopyHoist"
59 void collectCopyInst();
68 std::vector<DenseMap<std::pair<Register, Register>,
MachineInstr *>>
74char HexagonCopyHoisting::ID = 0;
101 if (BB->pred_size() != 1)
103 auto &BBCopyInst = CopyMIList[BB->getNumber()];
104 if (BBCopyInst.size() > 0)
105 Changed |= analyzeCopy(*BB->pred_begin());
113 SI->runOnMachineFunction(Fn);
115 LIS.runOnMachineFunction(Fn);
123void HexagonCopyHoisting::collectCopyInst() {
126 auto &BBCopyInst = CopyMIList[BB.getNumber()];
131 if (
MI.getOpcode() == TargetOpcode::COPY)
132 addMItoCopyList(&
MI);
134 LLVM_DEBUG(
dbgs() <<
"\tNumber of copies: " << BBCopyInst.size() <<
"\n");
139 unsigned BBNum =
MI->getParent()->getNumber();
140 auto &BBCopyInst = CopyMIList[BBNum];
146 MRI->getRegClass(DstReg) != &Hexagon::IntRegsRegClass ||
147 MRI->getRegClass(SrcReg) != &Hexagon::IntRegsRegClass)
150 BBCopyInst.insert(std::pair(std::pair(SrcReg, DstReg),
MI));
153 for (
auto II : BBCopyInst) {
167 bool Changed =
false;
172 if (SB->pred_size() != 1 || SB->isEHPad() || SB->hasAddressTaken())
177 auto &BBCopyInst1 = CopyMIList[SBB1->
getNumber()];
179 for (
auto II : BBCopyInst1) {
180 std::pair<Register, Register>
Key = II.getFirst();
182 bool IsSafetoMove =
true;
184 auto &SuccBBCopyInst = CopyMIList[SuccBB->getNumber()];
185 if (!SuccBBCopyInst.count(Key)) {
187 IsSafetoMove =
false;
193 if (!isSafetoMove(SuccMI)) {
194 IsSafetoMove =
false;
203 moveCopyInstr(BB, Key,
MI);
210 auto &BBCopyInst = CopyMIList[BB->
getNumber()];
211 for (
auto II : BBCopyInst) {
219bool HexagonCopyHoisting::isSafetoMove(
MachineInstr *CandMI) {
229 for (MII = BB->
begin(), MIE = CandMI; MII != MIE; ++MII) {
232 if (Mo.isReg() && Mo.getReg() == DefR)
236 for (MII = BB->
begin(), MIE = CandMI; MII != MIE; ++MII) {
239 if (Mo.isReg() && Mo.isDef() && Mo.getReg() == UseR)
246 std::pair<Register, Register> Key,
256 auto &BBCopyInst = CopyMIList[SuccBB->
getNumber()];
259 BBCopyInst.erase(Key);
268 "Hexagon move phi copy",
false,
false)
271 return new HexagonCopyHoisting();
unsigned const MachineRegisterInfo * MRI
This file defines the DenseMap class.
static cl::opt< std::string > CPHoistFn("cphoistfn", cl::Hidden, cl::desc(""), cl::init(""))
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME, false, false) char RISCVCoalesceVSETVLI const LiveIntervals * LIS
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
FunctionPass class - This class is used to implement most global optimizations.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
succ_iterator succ_begin()
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned succ_size() const
iterator_range< succ_iterator > successors()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
Representation of each machine instruction.
const MachineBasicBlock * getParent() const
iterator_range< mop_iterator > operands()
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
A global registry used in conjunction with static constructors to make pluggable components (like tar...
StringRef - Represent a constant reference to a string, i.e.
StringRef getName() const
Return a constant reference to the value's name.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createHexagonCopyHoisting()
iterator_range< po_iterator< T > > post_order(const T &G)
void initializeHexagonCopyHoistingPass(PassRegistry &Registry)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
char & HexagonCopyHoistingID