LLVM API Documentation
00001 //===-- LiveIntervalUnion.cpp - Live interval union data structure --------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // LiveIntervalUnion represents a coalesced set of live intervals. This may be 00011 // used during coalescing to represent a congruence class, or during register 00012 // allocation to model liveness of a physical register. 00013 // 00014 //===----------------------------------------------------------------------===// 00015 00016 #define DEBUG_TYPE "regalloc" 00017 #include "llvm/CodeGen/LiveIntervalUnion.h" 00018 #include "llvm/ADT/SparseBitVector.h" 00019 #include "llvm/Support/Debug.h" 00020 #include "llvm/Support/raw_ostream.h" 00021 #include "llvm/Target/TargetRegisterInfo.h" 00022 #include <algorithm> 00023 00024 using namespace llvm; 00025 00026 00027 // Merge a LiveInterval's segments. Guarantee no overlaps. 00028 void LiveIntervalUnion::unify(LiveInterval &VirtReg) { 00029 if (VirtReg.empty()) 00030 return; 00031 ++Tag; 00032 00033 // Insert each of the virtual register's live segments into the map. 00034 LiveInterval::iterator RegPos = VirtReg.begin(); 00035 LiveInterval::iterator RegEnd = VirtReg.end(); 00036 SegmentIter SegPos = Segments.find(RegPos->start); 00037 00038 while (SegPos.valid()) { 00039 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); 00040 if (++RegPos == RegEnd) 00041 return; 00042 SegPos.advanceTo(RegPos->start); 00043 } 00044 00045 // We have reached the end of Segments, so it is no longer necessary to search 00046 // for the insertion position. 00047 // It is faster to insert the end first. 00048 --RegEnd; 00049 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); 00050 for (; RegPos != RegEnd; ++RegPos, ++SegPos) 00051 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); 00052 } 00053 00054 // Remove a live virtual register's segments from this union. 00055 void LiveIntervalUnion::extract(LiveInterval &VirtReg) { 00056 if (VirtReg.empty()) 00057 return; 00058 ++Tag; 00059 00060 // Remove each of the virtual register's live segments from the map. 00061 LiveInterval::iterator RegPos = VirtReg.begin(); 00062 LiveInterval::iterator RegEnd = VirtReg.end(); 00063 SegmentIter SegPos = Segments.find(RegPos->start); 00064 00065 for (;;) { 00066 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); 00067 SegPos.erase(); 00068 if (!SegPos.valid()) 00069 return; 00070 00071 // Skip all segments that may have been coalesced. 00072 RegPos = VirtReg.advanceTo(RegPos, SegPos.start()); 00073 if (RegPos == RegEnd) 00074 return; 00075 00076 SegPos.advanceTo(RegPos->start); 00077 } 00078 } 00079 00080 void 00081 LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const { 00082 if (empty()) { 00083 OS << " empty\n"; 00084 return; 00085 } 00086 for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) { 00087 OS << " [" << SI.start() << ' ' << SI.stop() << "):" 00088 << PrintReg(SI.value()->reg, TRI); 00089 } 00090 OS << '\n'; 00091 } 00092 00093 #ifndef NDEBUG 00094 // Verify the live intervals in this union and add them to the visited set. 00095 void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) { 00096 for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI) 00097 VisitedVRegs.set(SI.value()->reg); 00098 } 00099 #endif //!NDEBUG 00100 00101 // Scan the vector of interfering virtual registers in this union. Assume it's 00102 // quite small. 00103 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { 00104 SmallVectorImpl<LiveInterval*>::const_iterator I = 00105 std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg); 00106 return I != InterferingVRegs.end(); 00107 } 00108 00109 // Collect virtual registers in this union that interfere with this 00110 // query's live virtual register. 00111 // 00112 // The query state is one of: 00113 // 00114 // 1. CheckedFirstInterference == false: Iterators are uninitialized. 00115 // 2. SeenAllInterferences == true: InterferingVRegs complete, iterators unused. 00116 // 3. Iterators left at the last seen intersection. 00117 // 00118 unsigned LiveIntervalUnion::Query:: 00119 collectInterferingVRegs(unsigned MaxInterferingRegs) { 00120 // Fast path return if we already have the desired information. 00121 if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs) 00122 return InterferingVRegs.size(); 00123 00124 // Set up iterators on the first call. 00125 if (!CheckedFirstInterference) { 00126 CheckedFirstInterference = true; 00127 00128 // Quickly skip interference check for empty sets. 00129 if (VirtReg->empty() || LiveUnion->empty()) { 00130 SeenAllInterferences = true; 00131 return 0; 00132 } 00133 00134 // In most cases, the union will start before VirtReg. 00135 VirtRegI = VirtReg->begin(); 00136 LiveUnionI.setMap(LiveUnion->getMap()); 00137 LiveUnionI.find(VirtRegI->start); 00138 } 00139 00140 LiveInterval::iterator VirtRegEnd = VirtReg->end(); 00141 LiveInterval *RecentReg = 0; 00142 while (LiveUnionI.valid()) { 00143 assert(VirtRegI != VirtRegEnd && "Reached end of VirtReg"); 00144 00145 // Check for overlapping interference. 00146 while (VirtRegI->start < LiveUnionI.stop() && 00147 VirtRegI->end > LiveUnionI.start()) { 00148 // This is an overlap, record the interfering register. 00149 LiveInterval *VReg = LiveUnionI.value(); 00150 if (VReg != RecentReg && !isSeenInterference(VReg)) { 00151 RecentReg = VReg; 00152 InterferingVRegs.push_back(VReg); 00153 if (InterferingVRegs.size() >= MaxInterferingRegs) 00154 return InterferingVRegs.size(); 00155 } 00156 // This LiveUnion segment is no longer interesting. 00157 if (!(++LiveUnionI).valid()) { 00158 SeenAllInterferences = true; 00159 return InterferingVRegs.size(); 00160 } 00161 } 00162 00163 // The iterators are now not overlapping, LiveUnionI has been advanced 00164 // beyond VirtRegI. 00165 assert(VirtRegI->end <= LiveUnionI.start() && "Expected non-overlap"); 00166 00167 // Advance the iterator that ends first. 00168 VirtRegI = VirtReg->advanceTo(VirtRegI, LiveUnionI.start()); 00169 if (VirtRegI == VirtRegEnd) 00170 break; 00171 00172 // Detect overlap, handle above. 00173 if (VirtRegI->start < LiveUnionI.stop()) 00174 continue; 00175 00176 // Still not overlapping. Catch up LiveUnionI. 00177 LiveUnionI.advanceTo(VirtRegI->start); 00178 } 00179 SeenAllInterferences = true; 00180 return InterferingVRegs.size(); 00181 } 00182 00183 void LiveIntervalUnion::Array::init(LiveIntervalUnion::Allocator &Alloc, 00184 unsigned NSize) { 00185 // Reuse existing allocation. 00186 if (NSize == Size) 00187 return; 00188 clear(); 00189 Size = NSize; 00190 LIUs = static_cast<LiveIntervalUnion*>( 00191 malloc(sizeof(LiveIntervalUnion)*NSize)); 00192 for (unsigned i = 0; i != Size; ++i) 00193 new(LIUs + i) LiveIntervalUnion(Alloc); 00194 } 00195 00196 void LiveIntervalUnion::Array::clear() { 00197 if (!LIUs) 00198 return; 00199 for (unsigned i = 0; i != Size; ++i) 00200 LIUs[i].~LiveIntervalUnion(); 00201 free(LIUs); 00202 Size = 0; 00203 LIUs = 0; 00204 }