LLVM  9.0.0svn
llvm::ARMTargetLowering Member List

This is the complete list of members for llvm::ARMTargetLowering, including all inherited members.

addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)llvm::TargetLoweringBaseinlineprotected
AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
addRegisterClass(MVT VT, const TargetRegisterClass *RC)llvm::TargetLoweringBaseinlineprotected
AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const overridellvm::ARMTargetLoweringvirtual
aggressivelyPreferBuildVectorSources(EVT VecVT) constllvm::TargetLoweringBaseinlinevirtual
alignLoopsWithOptSize() const overridellvm::ARMTargetLoweringvirtual
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) constllvm::TargetLoweringBase
allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, bool *Fast) const overridellvm::ARMTargetLoweringvirtual
allowTruncateForTailCall(Type *Ty1, Type *Ty2) const overridellvm::ARMTargetLoweringvirtual
areJTsAllowed(const Function *Fn) constllvm::TargetLoweringBaseinlinevirtual
ArgListTy typedefllvm::TargetLoweringBase
ARMTargetLowering(const TargetMachine &TM, const ARMSubtarget &STI)llvm::ARMTargetLoweringexplicit
AsmOperandInfoVector typedefllvm::TargetLowering
AtomicExpansionKind enum namellvm::TargetLoweringBase
BooleanContent enum namellvm::TargetLoweringBase
BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode *> &Created) constllvm::TargetLowering
BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode *> &Created) constllvm::TargetLowering
C_Memory enum valuellvm::TargetLowering
C_Other enum valuellvm::TargetLowering
C_Register enum valuellvm::TargetLowering
C_RegisterClass enum valuellvm::TargetLowering
C_Unknown enum valuellvm::TargetLowering
canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const overridellvm::ARMTargetLoweringvirtual
canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const overridellvm::ARMTargetLoweringinlinevirtual
canOpTrap(unsigned Op, EVT VT) constllvm::TargetLoweringBasevirtual
CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) constllvm::ARMTargetLowering
CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) constllvm::ARMTargetLowering
combineRepeatedFPDivisors() constllvm::TargetLoweringinlinevirtual
ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) constllvm::TargetLoweringvirtual
computeKnownBitsForFrameIndex(const SDValue FIOp, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLoweringvirtual
computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const overridellvm::ARMTargetLoweringvirtual
ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLoweringvirtual
computeRegisterProperties(const TargetRegisterInfo *TRI)llvm::TargetLoweringBaseprotected
ConstraintType enum namellvm::TargetLowering
ConstraintWeight enum namellvm::TargetLowering
convertSelectOfConstantsToMath(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
convertSetCCLogicToBitwiseLogic(EVT VT) const overridellvm::ARMTargetLoweringinlinevirtual
createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const overridellvm::ARMTargetLoweringvirtual
Custom enum valuellvm::TargetLoweringBase
CW_Best enum valuellvm::TargetLowering
CW_Better enum valuellvm::TargetLowering
CW_Constant enum valuellvm::TargetLowering
CW_Default enum valuellvm::TargetLowering
CW_Good enum valuellvm::TargetLowering
CW_Invalid enum valuellvm::TargetLowering
CW_Memory enum valuellvm::TargetLowering
CW_Okay enum valuellvm::TargetLowering
CW_Register enum valuellvm::TargetLowering
CW_SpecificReg enum valuellvm::TargetLowering
decomposeMulByConstant(EVT VT, SDValue C) constllvm::TargetLoweringBaseinlinevirtual
Disabled enum valuellvm::TargetLoweringBase
emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const overridellvm::ARMTargetLoweringvirtual
EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const overridellvm::ARMTargetLoweringvirtual
emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const overridellvm::ARMTargetLoweringvirtual
emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const overridellvm::ARMTargetLoweringvirtual
emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) constllvm::TargetLoweringBaseprotected
emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) constllvm::TargetLoweringinlinevirtual
emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const overridellvm::ARMTargetLoweringvirtual
emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const overridellvm::ARMTargetLoweringvirtual
emitXRayCustomEvent(MachineInstr &MI, MachineBasicBlock *MBB) constllvm::TargetLoweringBaseprotected
emitXRayTypedEvent(MachineInstr &MI, MachineBasicBlock *MBB) constllvm::TargetLoweringBaseprotected
enableAggressiveFMAFusion(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
Enabled enum valuellvm::TargetLoweringBase
EnableExtLdPromotionllvm::TargetLoweringBaseprotected
enableExtLdPromotion() constllvm::TargetLoweringBaseinline
Expand enum valuellvm::TargetLoweringBase
expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandAddSubSat(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_UINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) constllvm::TargetLoweringinlinevirtual
ExpandInlineAsm(CallInst *CI) const overridellvm::ARMTargetLoweringvirtual
expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) constllvm::TargetLowering
expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) constllvm::TargetLowering
expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) constllvm::TargetLowering
expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) constllvm::TargetLowering
expandVecReduce(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
finalizeLowering(MachineFunction &MF) const overridellvm::ARMTargetLoweringvirtual
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const overridellvm::ARMTargetLoweringprotectedvirtual
functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const overridellvm::ARMTargetLoweringvirtual
GatherAllAliasesMaxDepthllvm::TargetLoweringBaseprotected
getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const overridellvm::ARMTargetLoweringvirtual
getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) constllvm::TargetLoweringBaseinlinevirtual
getBooleanContents(bool isVec, bool isFloat) constllvm::TargetLoweringBaseinline
getBooleanContents(EVT Type) constllvm::TargetLoweringBaseinline
getBypassSlowDivWidths() constllvm::TargetLoweringBaseinline
getByValTypeAlignment(Type *Ty, const DataLayout &DL) constllvm::TargetLoweringBasevirtual
getClearCacheBuiltinName() constllvm::TargetLoweringinlinevirtual
getCmpLibcallCC(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getCmpLibcallReturnType() constllvm::TargetLoweringBasevirtual
getCondCodeAction(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
getConstraintType(StringRef Constraint) const overridellvm::ARMTargetLoweringvirtual
getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, bool UseTLS) constllvm::TargetLoweringBaseprotected
getDivRefinementSteps(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getExceptionPointerRegister(const Constant *PersonalityFn) const overridellvm::ARMTargetLoweringvirtual
getExceptionSelectorRegister(const Constant *PersonalityFn) const overridellvm::ARMTargetLoweringvirtual
getExtendForAtomicOps() constllvm::TargetLoweringBaseinlinevirtual
getExtendForContent(BooleanContent Content)llvm::TargetLoweringBaseinlinestatic
getFenceOperandTy(const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) constllvm::TargetLoweringBaseinline
getFrameIndexTy(const DataLayout &DL) constllvm::TargetLoweringBaseinline
getGatherAllAliasesMaxDepth() constllvm::TargetLoweringBaseinline
getIndexedLoadAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getIndexedStoreAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getInlineAsmMemConstraint(StringRef ConstraintCode) const overridellvm::ARMTargetLoweringinlinevirtual
getIRStackGuard(IRBuilder<> &IRB) constllvm::TargetLoweringBasevirtual
getJumpBufAlignment() constllvm::TargetLoweringBaseinline
getJumpBufSize() constllvm::TargetLoweringBaseinline
getJumpTableEncoding() const overridellvm::ARMTargetLoweringvirtual
getLibcallCallingConv(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getLibcallName(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
getMaxAtomicSizeInBitsSupported() constllvm::TargetLoweringBaseinline
getMaxExpandSizeMemcmp(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxGluedStoresPerMemcpy() constllvm::TargetLoweringBaseinlinevirtual
getMaximumJumpTableSize() constllvm::TargetLoweringBase
getMaxStoresPerMemcpy(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxStoresPerMemmove(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxStoresPerMemset(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxSupportedInterleaveFactor() const overridellvm::ARMTargetLoweringinlinevirtual
getMemcmpEqZeroLoadsPerBlock() constllvm::TargetLoweringBaseinlinevirtual
getMinCmpXchgSizeInBits() constllvm::TargetLoweringBaseinline
getMinFunctionAlignment() constllvm::TargetLoweringBaseinline
getMinimumJumpTableDensity(bool OptForSize) constllvm::TargetLoweringBase
getMinimumJumpTableEntries() constllvm::TargetLoweringBasevirtual
getMinStackArgumentAlignment() constllvm::TargetLoweringBaseinline
getMMOFlags(const Instruction &I) constllvm::TargetLoweringinlinevirtual
getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) constllvm::TargetLoweringvirtual
getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL) constllvm::ARMTargetLowering
getNumRegisters(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
getOperationAction(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const overridellvm::ARMTargetLoweringvirtual
getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) constllvm::TargetLoweringvirtual
getPointerTy(const DataLayout &DL, uint32_t AS=0) constllvm::TargetLoweringBaseinline
getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const overridellvm::ARMTargetLoweringvirtual
getPredictableBranchThreshold() constllvm::TargetLoweringBasevirtual
getPreferredVectorAction(MVT VT) constllvm::TargetLoweringBaseinlinevirtual
getPrefFunctionAlignment() constllvm::TargetLoweringBaseinline
getPrefLoopAlignment(MachineLoop *ML=nullptr) constllvm::TargetLoweringBaseinlinevirtual
getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const overridellvm::ARMTargetLoweringvirtual
getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) constllvm::TargetLoweringinlinevirtual
getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getRegClassFor(MVT VT) const overridellvm::ARMTargetLoweringvirtual
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const overridellvm::ARMTargetLoweringvirtual
getRegisterType(MVT VT) constllvm::TargetLoweringBaseinline
getRegisterType(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
getRepRegClassCostFor(MVT VT) constllvm::TargetLoweringBaseinlinevirtual
getRepRegClassFor(MVT VT) constllvm::TargetLoweringBaseinlinevirtual
getSafeStackPointerLocation(IRBuilder<> &IRB) constllvm::TargetLoweringBasevirtual
getScalarShiftAmountTy(const DataLayout &, EVT) constllvm::TargetLoweringBasevirtual
getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const overridellvm::ARMTargetLoweringvirtual
getSchedulingPreference(SDNode *N) const overridellvm::ARMTargetLoweringvirtual
llvm::TargetLowering::getSchedulingPreference() constllvm::TargetLoweringBaseinline
getScratchRegisters(CallingConv::ID CC) constllvm::TargetLoweringinlinevirtual
getSDagStackGuard(const Module &M) constllvm::TargetLoweringBasevirtual
getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const overridellvm::ARMTargetLoweringvirtual
getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) constllvm::TargetLoweringBase
getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const overridellvm::ARMTargetLoweringvirtual
getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) constllvm::TargetLoweringinlinevirtual
getSqrtRefinementSteps(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getSSPStackGuardCheck(const Module &M) constllvm::TargetLoweringBasevirtual
getStackPointerRegisterToSaveRestore() constllvm::TargetLoweringBaseinline
getStackProbeSymbolName(MachineFunction &MF) constllvm::TargetLoweringBaseinlinevirtual
getStrictFPOperationAction(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
getSubtarget() constllvm::ARMTargetLoweringinline
getTargetMachine() constllvm::TargetLoweringBaseinline
getTargetNodeName(unsigned Opcode) const overridellvm::ARMTargetLoweringvirtual
getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const overridellvm::ARMTargetLoweringvirtual
getTruncStoreAction(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
getTypeAction(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getTypeAction(MVT VT) constllvm::TargetLoweringBaseinline
getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) constllvm::TargetLoweringinlinevirtual
getTypeLegalizationCost(const DataLayout &DL, Type *Ty) constllvm::TargetLoweringBase
getTypeToExpandTo(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getTypeToPromoteTo(unsigned Op, MVT VT) constllvm::TargetLoweringBaseinline
getTypeToTransformTo(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getVaListSizeInBits(const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getValueTypeActions() constllvm::TargetLoweringBaseinline
getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) constllvm::TargetLowering
getVectorIdxTy(const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) constllvm::TargetLoweringBase
getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) constllvm::TargetLoweringBaseinlinevirtual
hasAndNot(SDValue X) constllvm::TargetLoweringBaseinlinevirtual
hasAndNotCompare(SDValue Y) constllvm::TargetLoweringBaseinlinevirtual
hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) constllvm::TargetLoweringBaseinline
hasBitPreservingFPLogic(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
hasExtractBitsInsn() constllvm::TargetLoweringBaseinline
hasFastEqualityCompare(unsigned NumBits) constllvm::TargetLoweringBaseinlinevirtual
hasFloatingPointExceptions() constllvm::TargetLoweringBaseinline
hasMultipleConditionRegisters() constllvm::TargetLoweringBaseinline
hasPairedLoad(EVT, unsigned &) constllvm::TargetLoweringBaseinlinevirtual
hasStandaloneRem(EVT VT) const overridellvm::ARMTargetLoweringinlinevirtual
hasTargetDAGCombine(ISD::NodeType NT) constllvm::TargetLoweringBaseinline
hasVectorBlend() constllvm::TargetLoweringBaseinlinevirtual
IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) constllvm::TargetLowering
initActions()llvm::TargetLoweringBaseprotected
insertSSPDeclarations(Module &M) constllvm::TargetLoweringBasevirtual
InstructionOpcodeToISD(unsigned Opcode) constllvm::TargetLoweringBase
isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) constllvm::TargetLoweringBaseinlinevirtual
isCheapToSpeculateCtlz() const overridellvm::ARMTargetLoweringvirtual
isCheapToSpeculateCttz() const overridellvm::ARMTargetLoweringvirtual
isCommutativeBinOp(unsigned Opcode) constllvm::TargetLoweringBaseinlinevirtual
isCondCodeLegal(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
isConstFalseVal(const SDNode *N) constllvm::TargetLowering
isConstTrueVal(const SDNode *N) constllvm::TargetLowering
isCtlzFast() constllvm::TargetLoweringBaseinlinevirtual
isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) constllvm::TargetLoweringinlinevirtual
isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const overridellvm::ARMTargetLoweringvirtual
IsDesirableToPromoteOp(SDValue, EVT &) constllvm::TargetLoweringinlinevirtual
isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const overridellvm::ARMTargetLoweringvirtual
isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) constllvm::TargetLowering
isExtFree(const Instruction *I) constllvm::TargetLoweringBaseinline
isExtFreeImpl(const Instruction *I) constllvm::TargetLoweringBaseinlineprotectedvirtual
isExtLoad(const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) constllvm::TargetLoweringBaseinline
isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const overridellvm::ARMTargetLoweringvirtual
isFAbsFree(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
isFNegFree(EVT VT) const overridellvm::ARMTargetLoweringvirtual
isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) constllvm::TargetLoweringBaseinlinevirtual
isFPExtFree(EVT DestVT, EVT SrcVT) constllvm::TargetLoweringBaseinlinevirtual
isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize=false) const overridellvm::ARMTargetLoweringvirtual
isFsqrtCheap(SDValue X, SelectionDAG &DAG) constllvm::TargetLoweringBaseinlinevirtual
isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) constllvm::TargetLoweringvirtual
isIndexedLoadLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexedStoreLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) constllvm::TargetLowering
isIntDivCheap(EVT VT, AttributeList Attr) constllvm::TargetLoweringBaseinlinevirtual
isJumpExpensive() constllvm::TargetLoweringBaseinline
isJumpTableRelative() constllvm::TargetLoweringBaseinlinevirtual
isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) constllvm::TargetLoweringvirtual
isLegalAddImmediate(int64_t Imm) const overridellvm::ARMTargetLoweringvirtual
isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const overridellvm::ARMTargetLoweringvirtual
isLegalICmpImmediate(int64_t Imm) const overridellvm::ARMTargetLoweringvirtual
isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL) constllvm::ARMTargetLowering
isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) constllvm::TargetLoweringBaseprotected
isLegalStoreImmediate(int64_t Value) constllvm::TargetLoweringBaseinlinevirtual
isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) constllvm::ARMTargetLowering
isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) constllvm::ARMTargetLowering
isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) constllvm::TargetLoweringBaseinlinevirtual
isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) constllvm::TargetLoweringBaseinlinevirtual
isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) constllvm::TargetLoweringBaseinlinevirtual
isNarrowingProfitable(EVT, EVT) constllvm::TargetLoweringBaseinlinevirtual
isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const overridellvm::ARMTargetLoweringinlinevirtual
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const overridellvm::ARMTargetLoweringvirtual
isOperationCustom(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationExpand(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegal(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegalOrCustom(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegalOrPromote(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isPositionIndependent() constllvm::TargetLowering
isPredictableSelectExpensive() constllvm::TargetLoweringBaseinline
isProfitableToCombineMinNumMaxNum(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
isProfitableToHoist(Instruction *I) constllvm::TargetLoweringBaseinlinevirtual
isReadOnly(const GlobalValue *GV) constllvm::ARMTargetLowering
isSafeMemOpType(MVT) constllvm::TargetLoweringBaseinlinevirtual
isSDNodeAlwaysUniform(const SDNode *N) constllvm::TargetLoweringinlinevirtual
isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) constllvm::TargetLoweringinlinevirtual
isSelectSupported(SelectSupportKind Kind) const overridellvm::ARMTargetLoweringinlinevirtual
isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) constllvm::TargetLoweringBaseinlinevirtual
isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const overridellvm::ARMTargetLoweringvirtual
isSlowDivBypassed() constllvm::TargetLoweringBaseinline
isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) constllvm::TargetLoweringBaseinlinevirtual
isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) constllvm::TargetLoweringBaseinline
isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) constllvm::TargetLoweringBaseinlinevirtual
isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) constllvm::TargetLoweringBaseinlinevirtual
isTruncateFree(Type *SrcTy, Type *DstTy) const overridellvm::ARMTargetLoweringvirtual
isTruncateFree(EVT SrcVT, EVT DstVT) const overridellvm::ARMTargetLoweringvirtual
isTruncStoreLegal(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isTypeDesirableForOp(unsigned, EVT VT) constllvm::TargetLoweringinlinevirtual
isTypeLegal(EVT VT) constllvm::TargetLoweringBaseinline
isVectorClearMaskLegal(ArrayRef< int >, EVT) constllvm::TargetLoweringBaseinlinevirtual
isVectorLoadExtDesirable(SDValue ExtVal) const overridellvm::ARMTargetLoweringvirtual
isVectorShiftByScalarCheap(Type *Ty) constllvm::TargetLoweringBaseinlinevirtual
isZExtFree(SDValue Val, EVT VT2) const overridellvm::ARMTargetLoweringvirtual
llvm::TargetLowering::isZExtFree(Type *FromTy, Type *ToTy) constllvm::TargetLoweringBaseinlinevirtual
llvm::TargetLowering::isZExtFree(EVT FromTy, EVT ToTy) constllvm::TargetLoweringBaseinlinevirtual
Legal enum valuellvm::TargetLoweringBase
LegalizeAction enum namellvm::TargetLoweringBase
LegalizeKind typedefllvm::TargetLoweringBase
LegalizeTypeAction enum namellvm::TargetLoweringBase
LibCall enum valuellvm::TargetLoweringBase
LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const overridellvm::ARMTargetLoweringvirtual
LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, SDLoc DL, const AsmOperandInfo &OpInfo, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
LowerCallTo(CallLoweringInfo &CLI) constllvm::TargetLowering
lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) constllvm::TargetLowering
LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) constllvm::TargetLoweringinlinevirtual
lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) constllvm::TargetLoweringBaseinlinevirtual
lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const overridellvm::ARMTargetLoweringvirtual
lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const overridellvm::ARMTargetLoweringvirtual
LowerOperation(SDValue Op, SelectionDAG &DAG) const overridellvm::ARMTargetLoweringvirtual
LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
LowerXConstraint(EVT ConstraintVT) const overridellvm::ARMTargetLoweringvirtual
makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) constllvm::ARMTargetLowering
makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true, bool isPostTypeLegalization=false) constllvm::TargetLowering
markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) constllvm::TargetLoweringBaseinlinevirtual
MaxGluedStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxLoadsPerMemcmpllvm::TargetLoweringBaseprotected
MaxLoadsPerMemcmpOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemmovellvm::TargetLoweringBaseprotected
MaxStoresPerMemmoveOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemsetllvm::TargetLoweringBaseprotected
MaxStoresPerMemsetOptSizellvm::TargetLoweringBaseprotected
mergeStoresAfterLegalization() constllvm::TargetLoweringBaseinlinevirtual
MulExpansionKind enum namellvm::TargetLoweringBase
needsFixedCatchObjects() constllvm::TargetLoweringBaseinlinevirtual
operator=(const TargetLowering &)=deletellvm::TargetLowering
llvm::TargetLoweringBase::operator=(const TargetLoweringBase &)=deletellvm::TargetLoweringBase
parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) constllvm::TargetLowering
ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) constllvm::TargetLoweringvirtual
PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) constllvm::ARMTargetLowering
PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) constllvm::ARMTargetLowering
PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) constllvm::ARMTargetLowering
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const overridellvm::ARMTargetLoweringvirtual
PredictableSelectIsExpensivellvm::TargetLoweringBaseprotected
preferShiftsToClearExtremeBits(SDValue X) constllvm::TargetLoweringBaseinlinevirtual
prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) constllvm::TargetLoweringinlinevirtual
Promote enum valuellvm::TargetLoweringBase
rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) constllvm::TargetLoweringBaseinline
ReciprocalEstimate enum namellvm::TargetLoweringBase
reduceSelectOfFPConstantLoads(bool IsFPSetCC) constllvm::TargetLoweringBaseinlinevirtual
ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const overridellvm::ARMTargetLoweringvirtual
ScalarCondVectorVal enum valuellvm::TargetLoweringBase
scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) constllvm::TargetLowering
scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) constllvm::TargetLowering
ScalarValSelect enum valuellvm::TargetLoweringBase
SelectSupportKind enum namellvm::TargetLoweringBase
setBooleanContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)llvm::TargetLoweringBaseinlineprotected
setBooleanVectorContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)llvm::TargetLoweringBaseinline
setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setHasExtractBitsInsn(bool hasExtractInsn=true)llvm::TargetLoweringBaseinlineprotected
setHasFloatingPointExceptions(bool FPExceptions=true)llvm::TargetLoweringBaseinlineprotected
setHasMultipleConditionRegisters(bool hasManyRegs=true)llvm::TargetLoweringBaseinlineprotected
setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setJumpBufAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setJumpBufSize(unsigned Size)llvm::TargetLoweringBaseinlineprotected
setJumpIsExpensive(bool isExpensive=true)llvm::TargetLoweringBaseprotected
setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)llvm::TargetLoweringBaseinline
setLibcallName(RTLIB::Libcall Call, const char *Name)llvm::TargetLoweringBaseinline
setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMaximumJumpTableSize(unsigned)llvm::TargetLoweringBaseprotected
setMinCmpXchgSizeInBits(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMinFunctionAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setMinimumJumpTableEntries(unsigned Val)llvm::TargetLoweringBaseprotected
setMinStackArgumentAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
setPrefFunctionAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setPrefLoopAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setSchedulingPreference(Sched::Preference Pref)llvm::TargetLoweringBaseinlineprotected
setStackPointerRegisterToSaveRestore(unsigned R)llvm::TargetLoweringBaseinlineprotected
setSupportsUnalignedAtomics(bool UnalignedSupported)llvm::TargetLoweringBaseinlineprotected
setTargetDAGCombine(ISD::NodeType NT)llvm::TargetLoweringBaseinlineprotected
setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setUseUnderscoreLongJmp(bool Val)llvm::TargetLoweringBaseinlineprotected
setUseUnderscoreSetJmp(bool Val)llvm::TargetLoweringBaseinlineprotected
shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, unsigned &PrefAlign) const overridellvm::ARMTargetLoweringvirtual
shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const overridellvm::ARMTargetLoweringvirtual
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const overridellvm::ARMTargetLoweringvirtual
shouldExpandAtomicLoadInIR(LoadInst *LI) const overridellvm::ARMTargetLoweringvirtual
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const overridellvm::ARMTargetLoweringvirtual
shouldExpandAtomicStoreInIR(StoreInst *SI) const overridellvm::ARMTargetLoweringvirtual
shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandShift(SelectionDAG &DAG, SDNode *N) const overridellvm::ARMTargetLoweringvirtual
shouldFoldShiftPairToMask(const SDNode *N, CombineLevel Level) const overridellvm::ARMTargetLoweringvirtual
shouldFormOverflowOp(unsigned Opcode, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldInsertFencesForAtomic(const Instruction *I) const overridellvm::ARMTargetLoweringvirtual
shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) constllvm::TargetLoweringBaseinlinevirtual
shouldScalarizeBinop(SDValue VecOp) constllvm::TargetLoweringBaseinlinevirtual
ShouldShrinkFPConstant(EVT) constllvm::TargetLoweringBaseinlinevirtual
shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) constllvm::TargetLoweringBaseinlinevirtual
shouldSinkOperands(Instruction *I, SmallVectorImpl< Use *> &Ops) const overridellvm::ARMTargetLoweringvirtual
shouldSplatInsEltVarIndex(EVT) constllvm::TargetLoweringBaseinlinevirtual
shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) constllvm::TargetLoweringBaseinlinevirtual
shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) constllvm::TargetLoweringBaseinlinevirtual
ShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) constllvm::TargetLowering
ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, TargetLoweringOpt &TLO) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, DAGCombinerInfo &DCI) constllvm::TargetLowering
SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0) constllvm::TargetLoweringvirtual
SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, DAGCombinerInfo &DCI) constllvm::TargetLowering
SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) constllvm::TargetLoweringvirtual
SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) constllvm::TargetLowering
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) constllvm::TargetLowering
storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) constllvm::TargetLoweringBaseinlinevirtual
supportsUnalignedAtomics() constllvm::TargetLoweringBaseinline
supportSwiftError() const overridellvm::ARMTargetLoweringinlinevirtual
TargetLowering(const TargetLowering &)=deletellvm::TargetLowering
TargetLowering(const TargetMachine &TM)llvm::TargetLoweringexplicit
TargetLoweringBase(const TargetMachine &TM)llvm::TargetLoweringBaseexplicit
TargetLoweringBase(const TargetLoweringBase &)=deletellvm::TargetLoweringBase
targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const overridellvm::ARMTargetLoweringvirtual
TypeExpandFloat enum valuellvm::TargetLoweringBase
TypeExpandInteger enum valuellvm::TargetLoweringBase
TypeLegal enum valuellvm::TargetLoweringBase
TypePromoteFloat enum valuellvm::TargetLoweringBase
TypePromoteInteger enum valuellvm::TargetLoweringBase
TypeScalarizeVector enum valuellvm::TargetLoweringBase
TypeSoftenFloat enum valuellvm::TargetLoweringBase
TypeSplitVector enum valuellvm::TargetLoweringBase
TypeWidenVector enum valuellvm::TargetLoweringBase
UndefinedBooleanContent enum valuellvm::TargetLoweringBase
Unspecified enum valuellvm::TargetLoweringBase
unwrapAddress(SDValue N) constllvm::TargetLoweringinlinevirtual
useLoadStackGuardNode() const overridellvm::ARMTargetLoweringvirtual
useSoftFloat() const overridellvm::ARMTargetLoweringvirtual
useStackGuardXorFP() constllvm::TargetLoweringBaseinlinevirtual
usesUnderscoreLongJmp() constllvm::TargetLoweringBaseinline
usesUnderscoreSetJmp() constllvm::TargetLoweringBaseinline
ValueTypeActionsllvm::TargetLoweringBaseprotected
VectorMaskSelect enum valuellvm::TargetLoweringBase
verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) constllvm::TargetLowering
ZeroOrNegativeOneBooleanContent enum valuellvm::TargetLoweringBase
ZeroOrOneBooleanContent enum valuellvm::TargetLoweringBase
~TargetLoweringBase()=defaultllvm::TargetLoweringBasevirtual