LLVM 19.0.0git
Enumerations
llvm::RISCVISD Namespace Reference

Enumerations

enum  NodeType : unsigned {
  FIRST_NUMBER = ISD::BUILTIN_OP_END , RET_GLUE , SRET_GLUE , MRET_GLUE ,
  CALL , SELECT_CC , BR_CC , BuildPairF64 ,
  SplitF64 , TAIL , ADD_LO , HI ,
  LLA , ADD_TPREL , MULHSU , SLLW ,
  SRAW , SRLW , DIVW , DIVUW ,
  REMUW , ROLW , RORW , CLZW ,
  CTZW , ABSW , FMV_H_X , FMV_X_ANYEXTH ,
  FMV_X_SIGNEXTH , FMV_W_X_RV64 , FMV_X_ANYEXTW_RV64 , FCVT_X ,
  FCVT_XU , FCVT_W_RV64 , FCVT_WU_RV64 , FP_ROUND_BF16 ,
  FP_EXTEND_BF16 , FROUND , FCLASS , FMAX ,
  FMIN , READ_COUNTER_WIDE , BREV8 , ORC_B ,
  ZIP , UNZIP , CLMUL , CLMULH ,
  CLMULR , SHA256SIG0 , SHA256SIG1 , SHA256SUM0 ,
  SHA256SUM1 , SM4KS , SM4ED , SM3P0 ,
  SM3P1 , MOPR , MOPRR , FIRST_VL_VECTOR_OP ,
  VMV_V_V_VL = FIRST_VL_VECTOR_OP , VMV_V_X_VL , VFMV_V_F_VL , VMV_X_S ,
  VMV_S_X_VL , VFMV_S_F_VL , SPLAT_VECTOR_SPLIT_I64_VL , TRUNCATE_VECTOR_VL ,
  VSLIDEUP_VL , VSLIDEDOWN_VL , VSLIDE1UP_VL , VSLIDE1DOWN_VL ,
  VFSLIDE1UP_VL , VFSLIDE1DOWN_VL , VID_VL , VFNCVT_ROD_VL ,
  VECREDUCE_ADD_VL , VECREDUCE_UMAX_VL , VECREDUCE_SMAX_VL , VECREDUCE_UMIN_VL ,
  VECREDUCE_SMIN_VL , VECREDUCE_AND_VL , VECREDUCE_OR_VL , VECREDUCE_XOR_VL ,
  VECREDUCE_FADD_VL , VECREDUCE_SEQ_FADD_VL , VECREDUCE_FMIN_VL , VECREDUCE_FMAX_VL ,
  ADD_VL , AND_VL , MUL_VL , OR_VL ,
  SDIV_VL , SHL_VL , SREM_VL , SRA_VL ,
  SRL_VL , ROTL_VL , ROTR_VL , SUB_VL ,
  UDIV_VL , UREM_VL , XOR_VL , SMIN_VL ,
  SMAX_VL , UMIN_VL , UMAX_VL , BITREVERSE_VL ,
  BSWAP_VL , CTLZ_VL , CTTZ_VL , CTPOP_VL ,
  SADDSAT_VL , UADDSAT_VL , SSUBSAT_VL , USUBSAT_VL ,
  AVGFLOORU_VL , AVGCEILU_VL , MULHS_VL , MULHU_VL ,
  FADD_VL , FSUB_VL , FMUL_VL , FDIV_VL ,
  VFMIN_VL , VFMAX_VL , FNEG_VL , FABS_VL ,
  FSQRT_VL , FCLASS_VL , FCOPYSIGN_VL , VFCVT_RTZ_X_F_VL ,
  VFCVT_RTZ_XU_F_VL , VFCVT_X_F_VL , VFCVT_XU_F_VL , VFROUND_NOEXCEPT_VL ,
  VFCVT_RM_X_F_VL , VFCVT_RM_XU_F_VL , SINT_TO_FP_VL , UINT_TO_FP_VL ,
  VFCVT_RM_F_X_VL , VFCVT_RM_F_XU_VL , FP_ROUND_VL , FP_EXTEND_VL ,
  VFMADD_VL , VFNMADD_VL , VFMSUB_VL , VFNMSUB_VL ,
  VFWMADD_VL , VFWNMADD_VL , VFWMSUB_VL , VFWNMSUB_VL ,
  VWMUL_VL , VWMULU_VL , VWMULSU_VL , VWADD_VL ,
  VWADDU_VL , VWSUB_VL , VWSUBU_VL , VWADD_W_VL ,
  VWADDU_W_VL , VWSUB_W_VL , VWSUBU_W_VL , VWSLL_VL ,
  VFWMUL_VL , VFWADD_VL , VFWSUB_VL , VFWADD_W_VL ,
  VFWSUB_W_VL , VWMACC_VL , VWMACCU_VL , VWMACCSU_VL ,
  VNSRL_VL , SETCC_VL , VMERGE_VL , VMAND_VL ,
  VMOR_VL , VMXOR_VL , VMCLR_VL , VMSET_VL ,
  VRGATHER_VX_VL , VRGATHER_VV_VL , VRGATHEREI16_VV_VL , VSEXT_VL ,
  VZEXT_VL , VCPOP_VL , VFIRST_VL , LAST_VL_VECTOR_OP = VFIRST_VL ,
  READ_VLENB , READ_CSR , WRITE_CSR , SWAP_CSR ,
  CZERO_EQZ , CZERO_NEZ , STRICT_FCVT_W_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE , STRICT_FCVT_WU_RV64 ,
  STRICT_FADD_VL , STRICT_FSUB_VL , STRICT_FMUL_VL , STRICT_FDIV_VL ,
  STRICT_FSQRT_VL , STRICT_VFMADD_VL , STRICT_VFNMADD_VL , STRICT_VFMSUB_VL ,
  STRICT_VFNMSUB_VL , STRICT_FP_ROUND_VL , STRICT_FP_EXTEND_VL , STRICT_VFNCVT_ROD_VL ,
  STRICT_SINT_TO_FP_VL , STRICT_UINT_TO_FP_VL , STRICT_VFCVT_RM_X_F_VL , STRICT_VFCVT_RTZ_X_F_VL ,
  STRICT_VFCVT_RTZ_XU_F_VL , STRICT_FSETCC_VL , STRICT_FSETCCS_VL , STRICT_VFROUND_NOEXCEPT_VL ,
  LAST_RISCV_STRICTFP_OPCODE = STRICT_VFROUND_NOEXCEPT_VL , SF_VC_XV_SE , SF_VC_IV_SE , SF_VC_VV_SE ,
  SF_VC_FV_SE , SF_VC_XVV_SE , SF_VC_IVV_SE , SF_VC_VVV_SE ,
  SF_VC_FVV_SE , SF_VC_XVW_SE , SF_VC_IVW_SE , SF_VC_VVW_SE ,
  SF_VC_FVW_SE , SF_VC_V_X_SE , SF_VC_V_I_SE , SF_VC_V_XV_SE ,
  SF_VC_V_IV_SE , SF_VC_V_VV_SE , SF_VC_V_FV_SE , SF_VC_V_XVV_SE ,
  SF_VC_V_IVV_SE , SF_VC_V_VVV_SE , SF_VC_V_FVV_SE , SF_VC_V_XVW_SE ,
  SF_VC_V_IVW_SE , SF_VC_V_VVW_SE , SF_VC_V_FVW_SE , TH_LWD = ISD::FIRST_TARGET_MEMORY_OPCODE ,
  TH_LWUD , TH_LDD , TH_SWD , TH_SDD
}
 

Enumeration Type Documentation

◆ NodeType

Enumerator
FIRST_NUMBER 
RET_GLUE 
SRET_GLUE 
MRET_GLUE 
CALL 
SELECT_CC 

Select with condition operator - This selects between a true value and a false value (ops #3 and #4) based on the boolean result of comparing the lhs and rhs (ops #0 and #1) of a conditional expression with the condition code in op #2, a XLenVT constant from the ISD::CondCode enum.

The lhs and rhs are XLenVT integers. The true and false values can be integer or floating point.

BR_CC 
BuildPairF64 
SplitF64 
TAIL 
ADD_LO 
HI 
LLA 
ADD_TPREL 
MULHSU 
SLLW 
SRAW 
SRLW 
DIVW 
DIVUW 
REMUW 
ROLW 
RORW 
CLZW 
CTZW 
ABSW 
FMV_H_X 
FMV_X_ANYEXTH 
FMV_X_SIGNEXTH 
FMV_W_X_RV64 
FMV_X_ANYEXTW_RV64 
FCVT_X 
FCVT_XU 
FCVT_W_RV64 
FCVT_WU_RV64 
FP_ROUND_BF16 
FP_EXTEND_BF16 
FROUND 
FCLASS 
FMAX 
FMIN 
READ_COUNTER_WIDE 
BREV8 
ORC_B 
ZIP 
UNZIP 
CLMUL 
CLMULH 
CLMULR 
SHA256SIG0 
SHA256SIG1 
SHA256SUM0 
SHA256SUM1 
SM4KS 
SM4ED 
SM3P0 
SM3P1 
MOPR 
MOPRR 
FIRST_VL_VECTOR_OP 
VMV_V_V_VL 
VMV_V_X_VL 
VFMV_V_F_VL 
VMV_X_S 
VMV_S_X_VL 
VFMV_S_F_VL 
SPLAT_VECTOR_SPLIT_I64_VL 
TRUNCATE_VECTOR_VL 
VSLIDEUP_VL 
VSLIDEDOWN_VL 
VSLIDE1UP_VL 
VSLIDE1DOWN_VL 
VFSLIDE1UP_VL 
VFSLIDE1DOWN_VL 
VID_VL 
VFNCVT_ROD_VL 
VECREDUCE_ADD_VL 
VECREDUCE_UMAX_VL 
VECREDUCE_SMAX_VL 
VECREDUCE_UMIN_VL 
VECREDUCE_SMIN_VL 
VECREDUCE_AND_VL 
VECREDUCE_OR_VL 
VECREDUCE_XOR_VL 
VECREDUCE_FADD_VL 
VECREDUCE_SEQ_FADD_VL 
VECREDUCE_FMIN_VL 
VECREDUCE_FMAX_VL 
ADD_VL 
AND_VL 
MUL_VL 
OR_VL 
SDIV_VL 
SHL_VL 
SREM_VL 
SRA_VL 
SRL_VL 
ROTL_VL 
ROTR_VL 
SUB_VL 
UDIV_VL 
UREM_VL 
XOR_VL 
SMIN_VL 
SMAX_VL 
UMIN_VL 
UMAX_VL 
BITREVERSE_VL 
BSWAP_VL 
CTLZ_VL 
CTTZ_VL 
CTPOP_VL 
SADDSAT_VL 
UADDSAT_VL 
SSUBSAT_VL 
USUBSAT_VL 
AVGFLOORU_VL 
AVGCEILU_VL 
MULHS_VL 
MULHU_VL 
FADD_VL 
FSUB_VL 
FMUL_VL 
FDIV_VL 
VFMIN_VL 
VFMAX_VL 
FNEG_VL 
FABS_VL 
FSQRT_VL 
FCLASS_VL 
FCOPYSIGN_VL 
VFCVT_RTZ_X_F_VL 
VFCVT_RTZ_XU_F_VL 
VFCVT_X_F_VL 
VFCVT_XU_F_VL 
VFROUND_NOEXCEPT_VL 
VFCVT_RM_X_F_VL 
VFCVT_RM_XU_F_VL 
SINT_TO_FP_VL 
UINT_TO_FP_VL 
VFCVT_RM_F_X_VL 
VFCVT_RM_F_XU_VL 
FP_ROUND_VL 
FP_EXTEND_VL 
VFMADD_VL 
VFNMADD_VL 
VFMSUB_VL 
VFNMSUB_VL 
VFWMADD_VL 
VFWNMADD_VL 
VFWMSUB_VL 
VFWNMSUB_VL 
VWMUL_VL 
VWMULU_VL 
VWMULSU_VL 
VWADD_VL 
VWADDU_VL 
VWSUB_VL 
VWSUBU_VL 
VWADD_W_VL 
VWADDU_W_VL 
VWSUB_W_VL 
VWSUBU_W_VL 
VWSLL_VL 
VFWMUL_VL 
VFWADD_VL 
VFWSUB_VL 
VFWADD_W_VL 
VFWSUB_W_VL 
VWMACC_VL 
VWMACCU_VL 
VWMACCSU_VL 
VNSRL_VL 
SETCC_VL 
VMERGE_VL 
VMAND_VL 
VMOR_VL 
VMXOR_VL 
VMCLR_VL 
VMSET_VL 
VRGATHER_VX_VL 
VRGATHER_VV_VL 
VRGATHEREI16_VV_VL 
VSEXT_VL 
VZEXT_VL 
VCPOP_VL 
VFIRST_VL 
LAST_VL_VECTOR_OP 
READ_VLENB 
READ_CSR 
WRITE_CSR 
SWAP_CSR 
CZERO_EQZ 
CZERO_NEZ 
STRICT_FCVT_W_RV64 
STRICT_FCVT_WU_RV64 
STRICT_FADD_VL 
STRICT_FSUB_VL 
STRICT_FMUL_VL 
STRICT_FDIV_VL 
STRICT_FSQRT_VL 
STRICT_VFMADD_VL 
STRICT_VFNMADD_VL 
STRICT_VFMSUB_VL 
STRICT_VFNMSUB_VL 
STRICT_FP_ROUND_VL 
STRICT_FP_EXTEND_VL 
STRICT_VFNCVT_ROD_VL 
STRICT_SINT_TO_FP_VL 
STRICT_UINT_TO_FP_VL 
STRICT_VFCVT_RM_X_F_VL 
STRICT_VFCVT_RTZ_X_F_VL 
STRICT_VFCVT_RTZ_XU_F_VL 
STRICT_FSETCC_VL 
STRICT_FSETCCS_VL 
STRICT_VFROUND_NOEXCEPT_VL 
LAST_RISCV_STRICTFP_OPCODE 
SF_VC_XV_SE 
SF_VC_IV_SE 
SF_VC_VV_SE 
SF_VC_FV_SE 
SF_VC_XVV_SE 
SF_VC_IVV_SE 
SF_VC_VVV_SE 
SF_VC_FVV_SE 
SF_VC_XVW_SE 
SF_VC_IVW_SE 
SF_VC_VVW_SE 
SF_VC_FVW_SE 
SF_VC_V_X_SE 
SF_VC_V_I_SE 
SF_VC_V_XV_SE 
SF_VC_V_IV_SE 
SF_VC_V_VV_SE 
SF_VC_V_FV_SE 
SF_VC_V_XVV_SE 
SF_VC_V_IVV_SE 
SF_VC_V_VVV_SE 
SF_VC_V_FVV_SE 
SF_VC_V_XVW_SE 
SF_VC_V_IVW_SE 
SF_VC_V_VVW_SE 
SF_VC_V_FVW_SE 
TH_LWD 
TH_LWUD 
TH_LDD 
TH_SWD 
TH_SDD 

Definition at line 30 of file RISCVISelLowering.h.