15#ifndef LLVM_MCA_HARDWAREUNITS_LSUNIT_H
16#define LLVM_MCA_HARDWAREUNITS_LSUNIT_H
36 unsigned NumPredecessors = 0;
37 unsigned NumExecutingPredecessors = 0;
38 unsigned NumExecutedPredecessors = 0;
40 unsigned NumInstructions = 0;
41 unsigned NumExecuting = 0;
42 unsigned NumExecuted = 0;
49 InstRef CriticalMemoryInstruction;
59 return OrderSucc.
size() + DataSucc.
size();
63 return NumExecutingPredecessors;
66 return NumExecutedPredecessors;
73 return CriticalMemoryInstruction;
76 return CriticalPredecessor;
86 Group->NumPredecessors++;
89 Group->
onGroupIssued(CriticalMemoryInstruction, IsDataDependent);
98 return NumPredecessors >
99 (NumExecutingPredecessors + NumExecutedPredecessors);
102 return NumExecutingPredecessors &&
103 ((NumExecutedPredecessors + NumExecutingPredecessors) ==
106 bool isReady()
const {
return NumExecutedPredecessors == NumPredecessors; }
108 return NumExecuting && (NumExecuting == (NumInstructions - NumExecuted));
110 bool isExecuted()
const {
return NumInstructions == NumExecuted; }
114 NumExecutingPredecessors++;
116 if (!ShouldUpdateCriticalDep)
119 unsigned Cycles =
IR.getInstruction()->getCyclesLeft();
120 if (CriticalPredecessor.
Cycles < Cycles) {
121 CriticalPredecessor.
IID =
IR.getSourceIndex();
122 CriticalPredecessor.
Cycles = Cycles;
128 NumExecutingPredecessors--;
129 NumExecutedPredecessors++;
138 if ((
bool)CriticalMemoryInstruction) {
139 const Instruction &OtherIS = *CriticalMemoryInstruction.getInstruction();
141 CriticalMemoryInstruction =
IR;
143 CriticalMemoryInstruction =
IR;
151 MG->onGroupIssued(CriticalMemoryInstruction,
false);
153 MG->onGroupExecuted();
157 MG->onGroupIssued(CriticalMemoryInstruction,
true);
165 if (CriticalMemoryInstruction &&
175 MG->onGroupExecuted();
185 CriticalPredecessor.
Cycles--;
207 unsigned UsedLQEntries;
208 unsigned UsedSQEntries;
219 unsigned NextGroupID;
223 unsigned StoreQueueSize,
bool AssumeNoAlias);
265 bool isSQFull()
const {
return SQSize && SQSize == UsedSQEntries; }
266 bool isLQFull()
const {
return LQSize && LQSize == UsedLQEntries; }
274 unsigned GroupID =
IR.getInstruction()->getLSUTokenID();
282 unsigned GroupID =
IR.getInstruction()->getLSUTokenID();
290 unsigned GroupID =
IR.getInstruction()->getLSUTokenID();
296 unsigned GroupID =
IR.getInstruction()->getLSUTokenID();
313 std::make_pair(NextGroupID, std::make_unique<MemoryGroup>()));
314 return NextGroupID++;
326 unsigned GroupID =
IR.getInstruction()->getLSUTokenID();
327 Groups[GroupID]->onInstructionIssued(
IR);
437 unsigned CurrentLoadGroupID;
438 unsigned CurrentLoadBarrierGroupID;
439 unsigned CurrentStoreGroupID;
440 unsigned CurrentStoreBarrierGroupID;
448 :
LSUnitBase(SM, LQ, SQ, AssumeNoAlias), CurrentLoadGroupID(0),
449 CurrentLoadBarrierGroupID(0), CurrentStoreGroupID(0),
450 CurrentStoreBarrierGroupID(0) {}
This file defines the DenseMap class.
This file defines a base class for describing a simulated hardware unit.
Legalize the Machine IR a function s Machine IR
This file defines abstractions used by the Pipeline to model register reads, register writes and inst...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
iterator find(const_arg_type_t< KeyT > Val)
bool contains(const_arg_type_t< KeyT > Val) const
Return true if the specified key is in the map, false otherwise.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
reference emplace_back(ArgTypes &&... Args)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An InstRef contains both a SourceMgr index and Instruction pair.
void invalidate()
Invalidate this reference.
unsigned getSourceIndex() const
An instruction propagated through the simulated instruction pipeline.
int getCyclesLeft() const
Abstract base interface for LS (load/store) units in llvm-mca.
MemoryGroup & getGroup(unsigned Index)
virtual unsigned dispatch(const InstRef &IR)=0
Allocates LS resources for instruction IR.
virtual void onInstructionExecuted(const InstRef &IR)
unsigned getUsedSQEntries() const
bool isWaiting(const InstRef &IR) const
Check if instruction IR is still waiting on memory operations, and the wait time is still unknown.
virtual void onInstructionIssued(const InstRef &IR)
bool isValidGroupID(unsigned Index) const
const MemoryGroup & getGroup(unsigned Index) const
unsigned createMemoryGroup()
bool isPending(const InstRef &IR) const
Check if instruction IR only depends on memory instructions that are currently executing.
virtual Status isAvailable(const InstRef &IR) const =0
This method checks the availability of the load/store buffers.
virtual void cycleEvent()
unsigned getUsedLQEntries() const
bool assumeNoAlias() const
bool hasDependentUsers(const InstRef &IR) const
virtual void onInstructionRetired(const InstRef &IR)
unsigned getLoadQueueSize() const
Returns the total number of entries in the load queue.
unsigned getStoreQueueSize() const
Returns the total number of entries in the store queue.
bool isReady(const InstRef &IR) const
Check if a peviously dispatched instruction IR is now ready for execution.
Default Load/Store Unit (LS Unit) for simulated processors.
Status isAvailable(const InstRef &IR) const override
Returns LSU_AVAILABLE if there are enough load/store queue entries to accomodate instruction IR.
LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ, bool AssumeNoAlias)
void onInstructionExecuted(const InstRef &IR) override
unsigned dispatch(const InstRef &IR) override
Allocates LS resources for instruction IR.
LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ)
LSUnit(const MCSchedModel &SM)
A node of a memory dependency graph.
unsigned getNumExecuted() const
unsigned getNumExecutingPredecessors() const
unsigned getNumExecuting() const
const InstRef & getCriticalMemoryInstruction() const
unsigned getNumExecutedPredecessors() const
unsigned getNumInstructions() const
unsigned getNumPredecessors() const
void onGroupIssued(const InstRef &IR, bool ShouldUpdateCriticalDep)
const CriticalDependency & getCriticalPredecessor() const
void addSuccessor(MemoryGroup *Group, bool IsDataDependent)
void onInstructionExecuted(const InstRef &IR)
void onInstructionIssued(const InstRef &IR)
MemoryGroup(MemoryGroup &&)=default
size_t getNumSuccessors() const
This is an optimization pass for GlobalISel generic memory operations.
Machine model for scheduling, bundling, and heuristics.
A critical data dependency descriptor.