15#ifndef LLVM_MCA_INSTRUCTION_H
16#define LLVM_MCA_INSTRUCTION_H
42 enum MCAOperandType :
unsigned char {
67 bool isValid()
const {
return Kind != kInvalid; }
68 bool isReg()
const {
return Kind == kRegister; }
69 bool isImm()
const {
return Kind == kImmediate; }
70 bool isSFPImm()
const {
return Kind == kSFPImmediate; }
71 bool isDFPImm()
const {
return Kind == kDFPImmediate; }
75 assert(
isReg() &&
"This is not a register operand!");
107 Op.Kind = kImmediate;
114 Op.Kind = kSFPImmediate;
121 Op.Kind = kDFPImmediate;
215 bool ClearsSuperRegs;
234 unsigned DependentWriteCyclesLeft;
249 bool clearsSuperRegs =
false,
bool writesZero =
false)
251 ClearsSuperRegs(clearsSuperRegs), WritesZero(writesZero),
252 IsEliminated(
false), DependentWrite(nullptr), PartialWrite(nullptr),
253 DependentWriteCyclesLeft(0), CRD() {}
265 return DependentWriteCyclesLeft;
281 unsigned NumUsers =
Users.size();
295 return !CyclesLeft || CyclesLeft <
getLatency();
306 assert(
Users.empty() &&
"Write is in an inconsistent state.");
311 void setPRF(
unsigned PRF) { PRFID = PRF; }
335 unsigned DependentWrites;
344 unsigned TotalCycles;
353 bool IndependentFromDef;
357 : RD(&
Desc), RegisterID(RegID), PRFID(0), DependentWrites(0),
367 bool isPending()
const {
return !IndependentFromDef && CyclesLeft > 0; }
395 CycleSegment(
unsigned StartCycle,
unsigned EndCycle,
bool IsReserved =
false)
396 : Begin(StartCycle),
End(EndCycle),
Reserved(IsReserved) {}
407 return Begin <
Other.Begin;
418 unsigned size()
const {
return End - Begin; };
424 unsigned begin()
const {
return Begin; }
502 bool IsOptimizableMove;
513 std::vector<MCAOperand> Operands;
519 bool IsALoadBarrier : 1;
520 bool IsAStoreBarrier : 1;
525 bool HasSideEffects : 1;
533 IsALoadBarrier(
false), IsAStoreBarrier(
false) {}
553 return Op.getIndex() ==
Idx;
564 [](
const WriteState &Def) {
return Def.getNumUsers() > 0; });
568 unsigned NumUsers = 0;
570 NumUsers += Def.getNumUsers();
578 bool isMemOp()
const {
return MayLoad || MayStore; }
612 enum InstrStage
Stage;
650 UsedBuffers(
D.UsedBuffers), CriticalRegDep(), CriticalMemDep(),
651 CriticalResourceMask(0), IsEliminated(
false) {}
706 CriticalMemDep = MemDep;
711 CriticalResourceMask = ResourceMask;
721 std::pair<unsigned, Instruction *> Data;
730 return Data.first <
Other.Data.first;
738 explicit operator bool()
const {
return Data.second !=
nullptr; }
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
SmallVector< uint32_t, 0 > Writes
Rewrite Partial Register Uses
iv Induction Variable Users
Legalize the Machine IR a function s Machine IR
mir Rename Register Operands
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class represents an Operation in the Expression.
A possibly irreducible generalization of a Loop.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
A Use represents the edge between a Value definition and its users.
CycleSegment(unsigned StartCycle, unsigned EndCycle, bool IsReserved=false)
bool operator<(const CycleSegment &Other) const
bool startsAfter(const CycleSegment &CS) const
bool contains(unsigned Cycle) const
void setEnd(unsigned NewEnd)
void subtract(unsigned Cycles)
CycleSegment & operator--()
bool endsBefore(const CycleSegment &CS) const
bool overlaps(const CycleSegment &CS) const
An InstRef contains both a SourceMgr index and Instruction pair.
void invalidate()
Invalidate this reference.
bool operator<(const InstRef &Other) const
const Instruction * getInstruction() const
InstRef(unsigned Index, Instruction *I)
Instruction * getInstruction()
unsigned getSourceIndex() const
bool operator!=(const InstRef &Other) const
bool operator==(const InstRef &Other) const
void print(raw_ostream &OS) const
Base class for instructions consumed by the simulation pipeline.
void setEndGroup(bool newVal)
unsigned getOpcode() const
bool isAStoreBarrier() const
bool isOptimizableMove() const
void setRetireOOO(bool newVal)
bool getRetireOOO() const
ArrayRef< WriteState > getDefs() const
void addOperand(const MCAOperand Op)
unsigned getNumMicroOps() const
const InstrDesc & getDesc() const
const MCAOperand * getOperand(const unsigned Idx) const
Return the MCAOperand which corresponds to index Idx within the original MCInst.
SmallVectorImpl< WriteState > & getDefs()
bool hasDependentUsers() const
unsigned getLatency() const
void clearOptimizableMove()
void setBeginGroup(bool newVal)
bool getHasSideEffects() const
SmallVectorImpl< ReadState > & getUses()
void setLoadBarrier(bool IsBarrier)
unsigned getNumOperands() const
bool getBeginGroup() const
void setStoreBarrier(bool IsBarrier)
void setHasSideEffects(bool newVal)
void setMayStore(bool newVal)
ArrayRef< ReadState > getUses() const
InstructionBase(const InstrDesc &D, const unsigned Opcode)
unsigned getNumUsers() const
void setOptimizableMove()
bool isALoadBarrier() const
void setMayLoad(bool newVal)
An instruction propagated through the simulated instruction pipeline.
bool isDispatched() const
bool isEliminated() const
Instruction(const InstrDesc &D, const unsigned Opcode)
uint64_t getCriticalResourceMask() const
unsigned getRCUTokenID() const
const CriticalDependency & getCriticalMemDep() const
const CriticalDependency & getCriticalRegDep() const
int getCyclesLeft() const
void setCriticalResourceMask(uint64_t ResourceMask)
const CriticalDependency & computeCriticalRegDep()
void execute(unsigned IID)
void setLSUTokenID(unsigned LSUTok)
void setUsedBuffers(uint64_t Mask)
void setCriticalMemDep(const CriticalDependency &MemDep)
void dispatch(unsigned RCUTokenID)
uint64_t getUsedBuffers() const
unsigned getLSUTokenID() const
A representation of an mca::Instruction operand for use in mca::CustomBehaviour.
unsigned getReg() const
Returns the register number.
static MCAOperand createSFPImm(uint32_t Val)
uint32_t getSFPImm() const
static MCAOperand createInvalid()
static MCAOperand createDFPImm(uint64_t Val)
static MCAOperand createImm(int64_t Val)
static MCAOperand createReg(unsigned Reg)
unsigned getIndex() const
uint64_t getDFPImm() const
void setIndex(const unsigned Idx)
Tracks register operand latency in cycles.
unsigned getRegisterFileID() const
unsigned getSchedClass() const
void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles)
bool isIndependentFromDef() const
const ReadDescriptor & getDescriptor() const
const CriticalDependency & getCriticalRegDep() const
void setDependentWrites(unsigned Writes)
MCPhysReg getRegisterID() const
bool isImplicitRead() const
ReadState(const ReadDescriptor &Desc, MCPhysReg RegID)
void setIndependentFromDef()
Tracks uses of a register definition (e.g.
unsigned getRegisterFileID() const
bool isEliminated() const
const WriteState * getDependentWrite() const
void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles)
unsigned getDependentWriteCyclesLeft() const
void setRegisterID(const MCPhysReg RegID)
unsigned getLatency() const
WriteState & operator=(const WriteState &Other)=default
void setPRF(unsigned PRF)
void setDependentWrite(const WriteState *Other)
int getCyclesLeft() const
WriteState(const WriteDescriptor &Desc, MCPhysReg RegID, bool clearsSuperRegs=false, bool writesZero=false)
const CriticalDependency & getCriticalRegDep() const
void onInstructionIssued(unsigned IID)
WriteState(const WriteState &Other)=default
bool clearsSuperRegisters() const
unsigned getNumUsers() const
MCPhysReg getRegisterID() const
unsigned getWriteResourceID() const
void addUser(unsigned IID, ReadState *Use, int ReadAdvance)
This class implements an extremely fast bulk output stream that can only output to a stream.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
raw_ostream & operator<<(raw_ostream &OS, const InstRef &IR)
constexpr int UNKNOWN_CYCLES
This is an optimization pass for GlobalISel generic memory operations.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
DWARFExpression::Operation Op
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Implement std::hash so that hash_code can be used in STL containers.
Description of the encoding of one expression Op.
A critical data dependency descriptor.
An instruction descriptor.
uint64_t UsedProcResGroups
uint64_t UsedProcResUnits
SmallVector< WriteDescriptor, 2 > Writes
InstrDesc(const InstrDesc &Other)=delete
SmallVector< std::pair< uint64_t, ResourceUsage >, 4 > Resources
unsigned HasPartiallyOverlappingGroups
SmallVector< ReadDescriptor, 4 > Reads
bool isZeroLatency() const
InstrDesc & operator=(const InstrDesc &Other)=delete
unsigned MustIssueImmediately
A register read descriptor.
bool isImplicitRead() const
Helper used by class InstrDesc to describe how hardware resources are used.
ResourceUsage(CycleSegment Cycles, unsigned Units=1)
A register write descriptor.
unsigned SClassOrWriteResourceID
bool isImplicitWrite() const