26 DependentWriteCyclesLeft = Cycles;
27 DependentWrite =
nullptr;
41 if (TotalCycles < Cycles) {
48 if (!DependentWrites) {
49 CyclesLeft = TotalCycles;
50 IsReady = !CyclesLeft;
61 for (
const std::pair<ReadState *, int> &
User : Users) {
63 unsigned ReadCycles = std::max(0, CyclesLeft -
User.second);
77 unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance);
78 User->writeStartEvent(IID, RegisterID, ReadCycles);
82 Users.emplace_back(
User, ReadAdvance);
87 User->writeStartEvent(IID, RegisterID, std::max(0, CyclesLeft));
91 assert(!PartialWrite &&
"PartialWrite already set!");
93 User->setDependentWrite(
this);
103 if (DependentWriteCyclesLeft)
104 DependentWriteCyclesLeft--;
109 if (DependentWrites && TotalCycles) {
120 IsReady = !CyclesLeft;
132 if (CriticalRegDep.
Cycles)
133 return CriticalRegDep;
135 unsigned MaxLatency = 0;
138 if (WriteCRD.
Cycles > MaxLatency)
139 CriticalRegDep = WriteCRD;
144 if (ReadCRD.
Cycles > MaxLatency)
145 CriticalRegDep = ReadCRD;
148 return CriticalRegDep;
159 CriticalResourceMask = 0;
160 IsEliminated =
false;
165 Stage = IS_DISPATCHED;
166 RCUTokenID = RCUToken;
175 Stage = IS_EXECUTING;
181 WS.onInstructionIssued(IID);
189 assert(
Stage == IS_READY &&
"Invalid internal state!");
212 return Use.isPending() ||
Use.isReady();
218 [](
const WriteState &Def) {
return !Def.getDependentWrite(); }))
248 assert(CyclesLeft &&
"Instruction already executed?");
This file defines abstractions used by the Pipeline to model register reads, register writes and inst...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A Use represents the edge between a Value definition and its users.
SmallVectorImpl< WriteState > & getDefs()
unsigned getLatency() const
void clearOptimizableMove()
SmallVectorImpl< ReadState > & getUses()
bool isDispatched() const
const CriticalDependency & computeCriticalRegDep()
void execute(unsigned IID)
void dispatch(unsigned RCUTokenID)
Tracks register operand latency in cycles.
void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles)
Tracks uses of a register definition (e.g.
void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles)
unsigned getLatency() const
int getCyclesLeft() const
void onInstructionIssued(unsigned IID)
MCPhysReg getRegisterID() const
void addUser(unsigned IID, ReadState *Use, int ReadAdvance)
constexpr int UNKNOWN_CYCLES
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
A critical data dependency descriptor.