LLVM 20.0.0git
Namespaces | Enumerations | Functions
ARMBaseInfo.h File Reference
#include "ARMMCTargetDesc.h"
#include "llvm/Support/ErrorHandling.h"
#include "Utils/ARMBaseInfo.h"

Go to the source code of this file.

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
namespace  llvm::ARM_PROC
 
namespace  llvm::ARM_MB
 
namespace  llvm::ARM_TSB
 
namespace  llvm::ARM_ISB
 
namespace  llvm::ARMII
 ARMII - This namespace holds all of the target specific flags that instruction info tracks.
 

Enumerations

enum  llvm::ARM_PROC::IMod { llvm::ARM_PROC::IE = 2 , llvm::ARM_PROC::ID = 3 }
 
enum  llvm::ARM_PROC::IFlags { llvm::ARM_PROC::F = 1 , llvm::ARM_PROC::I = 2 , llvm::ARM_PROC::A = 4 }
 
enum  llvm::ARM_MB::MemBOpt {
  llvm::ARM_MB::RESERVED_0 = 0 , llvm::ARM_MB::OSHLD = 1 , llvm::ARM_MB::OSHST = 2 , llvm::ARM_MB::OSH = 3 ,
  llvm::ARM_MB::RESERVED_4 = 4 , llvm::ARM_MB::NSHLD = 5 , llvm::ARM_MB::NSHST = 6 , llvm::ARM_MB::NSH = 7 ,
  llvm::ARM_MB::RESERVED_8 = 8 , llvm::ARM_MB::ISHLD = 9 , llvm::ARM_MB::ISHST = 10 , llvm::ARM_MB::ISH = 11 ,
  llvm::ARM_MB::RESERVED_12 = 12 , llvm::ARM_MB::LD = 13 , llvm::ARM_MB::ST = 14 , llvm::ARM_MB::SY = 15
}
 
enum  llvm::ARM_TSB::TraceSyncBOpt { llvm::ARM_TSB::CSYNC = 0 }
 
enum  llvm::ARM_ISB::InstSyncBOpt {
  llvm::ARM_ISB::RESERVED_0 = 0 , llvm::ARM_ISB::RESERVED_1 = 1 , llvm::ARM_ISB::RESERVED_2 = 2 , llvm::ARM_ISB::RESERVED_3 = 3 ,
  llvm::ARM_ISB::RESERVED_4 = 4 , llvm::ARM_ISB::RESERVED_5 = 5 , llvm::ARM_ISB::RESERVED_6 = 6 , llvm::ARM_ISB::RESERVED_7 = 7 ,
  llvm::ARM_ISB::RESERVED_8 = 8 , llvm::ARM_ISB::RESERVED_9 = 9 , llvm::ARM_ISB::RESERVED_10 = 10 , llvm::ARM_ISB::RESERVED_11 = 11 ,
  llvm::ARM_ISB::RESERVED_12 = 12 , llvm::ARM_ISB::RESERVED_13 = 13 , llvm::ARM_ISB::RESERVED_14 = 14 , llvm::ARM_ISB::SY = 15
}
 
enum  llvm::ARMII::IndexMode { llvm::ARMII::IndexModeNone = 0 , llvm::ARMII::IndexModePre = 1 , llvm::ARMII::IndexModePost = 2 , llvm::ARMII::IndexModeUpd = 3 }
 ARM Index Modes. More...
 
enum  llvm::ARMII::AddrMode {
  llvm::ARMII::AddrModeNone = 0 , llvm::ARMII::AddrMode1 = 1 , llvm::ARMII::AddrMode2 = 2 , llvm::ARMII::AddrMode3 = 3 ,
  llvm::ARMII::AddrMode4 = 4 , llvm::ARMII::AddrMode5 = 5 , llvm::ARMII::AddrMode6 = 6 , llvm::ARMII::AddrModeT1_1 = 7 ,
  llvm::ARMII::AddrModeT1_2 = 8 , llvm::ARMII::AddrModeT1_4 = 9 , llvm::ARMII::AddrModeT1_s = 10 , llvm::ARMII::AddrModeT2_i12 = 11 ,
  llvm::ARMII::AddrModeT2_i8 = 12 , llvm::ARMII::AddrModeT2_i8pos = 13 , llvm::ARMII::AddrModeT2_i8neg = 14 , llvm::ARMII::AddrModeT2_so = 15 ,
  llvm::ARMII::AddrModeT2_pc = 16 , llvm::ARMII::AddrModeT2_i8s4 = 17 , llvm::ARMII::AddrMode_i12 = 18 , llvm::ARMII::AddrMode5FP16 = 19 ,
  llvm::ARMII::AddrModeT2_ldrex = 20 , llvm::ARMII::AddrModeT2_i7s4 = 21 , llvm::ARMII::AddrModeT2_i7s2 = 22 , llvm::ARMII::AddrModeT2_i7 = 23
}
 ARM Addressing Modes. More...
 
enum  llvm::ARMII::TOF {
  llvm::ARMII::MO_NO_FLAG = 0 , llvm::ARMII::MO_LO16 = 0x1 , llvm::ARMII::MO_HI16 = 0x2 , llvm::ARMII::MO_OPTION_MASK = 0xf03 ,
  llvm::ARMII::MO_COFFSTUB = 0x4 , llvm::ARMII::MO_GOT = 0x8 , llvm::ARMII::MO_SBREL = 0x10 , llvm::ARMII::MO_DLLIMPORT = 0x20 ,
  llvm::ARMII::MO_SECREL = 0x40 , llvm::ARMII::MO_NONLAZY = 0x80 , llvm::ARMII::MO_LO_0_7 = 0x100 , llvm::ARMII::MO_LO_8_15 = 0x200 ,
  llvm::ARMII::MO_HI_0_7 = 0x400 , llvm::ARMII::MO_HI_8_15 = 0x800
}
 Target Operand Flag enum. More...
 
enum  {
  llvm::ARMII::AddrModeMask = 0x1f , llvm::ARMII::IndexModeShift = 5 , llvm::ARMII::IndexModeMask = 3 << IndexModeShift , llvm::ARMII::FormShift = 7 ,
  llvm::ARMII::FormMask = 0x3f << FormShift , llvm::ARMII::Pseudo = 0 << FormShift , llvm::ARMII::MulFrm = 1 << FormShift , llvm::ARMII::BrFrm = 2 << FormShift ,
  llvm::ARMII::BrMiscFrm = 3 << FormShift , llvm::ARMII::DPFrm = 4 << FormShift , llvm::ARMII::DPSoRegFrm = 5 << FormShift , llvm::ARMII::LdFrm = 6 << FormShift ,
  llvm::ARMII::StFrm = 7 << FormShift , llvm::ARMII::LdMiscFrm = 8 << FormShift , llvm::ARMII::StMiscFrm = 9 << FormShift , llvm::ARMII::LdStMulFrm = 10 << FormShift ,
  llvm::ARMII::LdStExFrm = 11 << FormShift , llvm::ARMII::ArithMiscFrm = 12 << FormShift , llvm::ARMII::SatFrm = 13 << FormShift , llvm::ARMII::ExtFrm = 14 << FormShift ,
  llvm::ARMII::VFPUnaryFrm = 15 << FormShift , llvm::ARMII::VFPBinaryFrm = 16 << FormShift , llvm::ARMII::VFPConv1Frm = 17 << FormShift , llvm::ARMII::VFPConv2Frm = 18 << FormShift ,
  llvm::ARMII::VFPConv3Frm = 19 << FormShift , llvm::ARMII::VFPConv4Frm = 20 << FormShift , llvm::ARMII::VFPConv5Frm = 21 << FormShift , llvm::ARMII::VFPLdStFrm = 22 << FormShift ,
  llvm::ARMII::VFPLdStMulFrm = 23 << FormShift , llvm::ARMII::VFPMiscFrm = 24 << FormShift , llvm::ARMII::ThumbFrm = 25 << FormShift , llvm::ARMII::MiscFrm = 26 << FormShift ,
  llvm::ARMII::NGetLnFrm = 27 << FormShift , llvm::ARMII::NSetLnFrm = 28 << FormShift , llvm::ARMII::NDupFrm = 29 << FormShift , llvm::ARMII::NLdStFrm = 30 << FormShift ,
  llvm::ARMII::N1RegModImmFrm = 31 << FormShift , llvm::ARMII::N2RegFrm = 32 << FormShift , llvm::ARMII::NVCVTFrm = 33 << FormShift , llvm::ARMII::NVDupLnFrm = 34 << FormShift ,
  llvm::ARMII::N2RegVShLFrm = 35 << FormShift , llvm::ARMII::N2RegVShRFrm = 36 << FormShift , llvm::ARMII::N3RegFrm = 37 << FormShift , llvm::ARMII::N3RegVShFrm = 38 << FormShift ,
  llvm::ARMII::NVExtFrm = 39 << FormShift , llvm::ARMII::NVMulSLFrm = 40 << FormShift , llvm::ARMII::NVTBLFrm = 41 << FormShift , llvm::ARMII::N3RegCplxFrm = 43 << FormShift ,
  llvm::ARMII::UnaryDP = 1 << 13 , llvm::ARMII::Xform16Bit = 1 << 14 , llvm::ARMII::ThumbArithFlagSetting = 1 << 19 , llvm::ARMII::ValidForTailPredication = 1 << 20 ,
  llvm::ARMII::RetainsPreviousHalfElement = 1 << 21 , llvm::ARMII::HorizontalReduction = 1 << 22 , llvm::ARMII::DoubleWidthResult = 1 << 23 , llvm::ARMII::VecSizeShift = 24 ,
  llvm::ARMII::VecSize = 3 << VecSizeShift , llvm::ARMII::DomainShift = 15 , llvm::ARMII::DomainMask = 15 << DomainShift , llvm::ARMII::DomainGeneral = 0 << DomainShift ,
  llvm::ARMII::DomainVFP = 1 << DomainShift , llvm::ARMII::DomainNEON = 2 << DomainShift , llvm::ARMII::DomainNEONA8 = 4 << DomainShift , llvm::ARMII::DomainMVE = 8 << DomainShift ,
  llvm::ARMII::ShiftTypeShift = 4 , llvm::ARMII::M_BitShift = 5 , llvm::ARMII::ShiftImmShift = 5 , llvm::ARMII::ShiftShift = 7 ,
  llvm::ARMII::N_BitShift = 7 , llvm::ARMII::ImmHiShift = 8 , llvm::ARMII::SoRotImmShift = 8 , llvm::ARMII::RegRsShift = 8 ,
  llvm::ARMII::ExtRotImmShift = 10 , llvm::ARMII::RegRdLoShift = 12 , llvm::ARMII::RegRdShift = 12 , llvm::ARMII::RegRdHiShift = 16 ,
  llvm::ARMII::RegRnShift = 16 , llvm::ARMII::S_BitShift = 20 , llvm::ARMII::W_BitShift = 21 , llvm::ARMII::AM3_I_BitShift = 22 ,
  llvm::ARMII::D_BitShift = 22 , llvm::ARMII::U_BitShift = 23 , llvm::ARMII::P_BitShift = 24 , llvm::ARMII::I_BitShift = 25 ,
  llvm::ARMII::CondShift = 28
}
 

Functions

static const char * llvm::ARM_PROC::IFlagsToString (unsigned val)
 
static const char * llvm::ARM_PROC::IModToString (unsigned val)
 
static const char * llvm::ARM_MB::MemBOptToString (unsigned val, bool HasV8)
 
static const char * llvm::ARM_TSB::TraceSyncBOptToString (unsigned val)
 
static const char * llvm::ARM_ISB::InstSyncBOptToString (unsigned val)
 
static bool llvm::isARMLowRegister (MCRegister Reg)
 isARMLowRegister - Returns true if the register is a low register (r0-r7).
 
static const char * llvm::ARMII::AddrModeToString (AddrMode addrmode)
 
Generated on Sun Dec 22 2024 04:16:47 for LLVM by doxygen 1.9.6