19#ifndef LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
20#define LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
41 : Streamer(S), Context(Context) {
43 ri_cprmask[0] = ri_cprmask[1] = ri_cprmask[2] = ri_cprmask[3] = 0;
47 GPR32RegClass = &(
TRI->getRegClass(Mips::GPR32RegClassID));
48 GPR64RegClass = &(
TRI->getRegClass(Mips::GPR64RegClassID));
49 FGR32RegClass = &(
TRI->getRegClass(Mips::FGR32RegClassID));
50 FGR64RegClass = &(
TRI->getRegClass(Mips::FGR64RegClassID));
51 AFGR64RegClass = &(
TRI->getRegClass(Mips::AFGR64RegClassID));
52 MSA128BRegClass = &(
TRI->getRegClass(Mips::MSA128BRegClassID));
53 COP0RegClass = &(
TRI->getRegClass(Mips::COP0RegClassID));
54 COP2RegClass = &(
TRI->getRegClass(Mips::COP2RegClassID));
55 COP3RegClass = &(
TRI->getRegClass(Mips::COP3RegClassID));
unsigned const TargetRegisterInfo * TRI
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
virtual ~MipsOptionRecord()=default
virtual void EmitMipsOptionRecord()=0
void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo)
void EmitMipsOptionRecord() override
~MipsRegInfoRecord() override=default
MipsRegInfoRecord(MipsELFStreamer *S, MCContext &Context)
This is an optimization pass for GlobalISel generic memory operations.