| AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) | llvm::AArch64RegisterBankInfo | |
| applyDefaultMapping(const OperandsMapper &OpdMapper) | llvm::RegisterBankInfo | static |
| applyMapping(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const | llvm::RegisterBankInfo | inline |
| BankIDToCopyMapIdx | llvm::AArch64GenRegisterBankInfo | protectedstatic |
| cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, TypeSize Size) const | llvm::RegisterBankInfo | inline |
| checkPartialMap(unsigned Idx, unsigned ValStartIdx, unsigned ValLength, const RegisterBank &RB) | llvm::AArch64GenRegisterBankInfo | protectedstatic |
| checkPartialMappingIdx(PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order) | llvm::AArch64GenRegisterBankInfo | protectedstatic |
| checkValueMapImpl(unsigned Idx, unsigned FirstInBank, unsigned Size, unsigned Offset) | llvm::AArch64GenRegisterBankInfo | protectedstatic |
| constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) | llvm::RegisterBankInfo | static |
| copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const override | llvm::AArch64RegisterBankInfo | virtual |
| DefaultMappingID | llvm::RegisterBankInfo | static |
| DistanceBetweenCrossRegCpy enum value | llvm::AArch64GenRegisterBankInfo | protected |
| DistanceBetweenRegBanks enum value | llvm::AArch64GenRegisterBankInfo | protected |
| First3OpsIdx enum value | llvm::AArch64GenRegisterBankInfo | protected |
| FirstCrossRegCpyIdx enum value | llvm::AArch64GenRegisterBankInfo | protected |
| FPExt16To32Idx enum value | llvm::AArch64GenRegisterBankInfo | protected |
| FPExt16To64Idx enum value | llvm::AArch64GenRegisterBankInfo | protected |
| FPExt32To64Idx enum value | llvm::AArch64GenRegisterBankInfo | protected |
| FPExt64To128Idx enum value | llvm::AArch64GenRegisterBankInfo | protected |
| getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const | llvm::RegisterBankInfo | inlinevirtual |
| getCopyMapping(unsigned DstBankID, unsigned SrcBankID, TypeSize Size) | llvm::AArch64GenRegisterBankInfo | protectedstatic |
| getFPExtMapping(unsigned DstSize, unsigned SrcSize) | llvm::AArch64GenRegisterBankInfo | protectedstatic |
| getInstrAlternativeMappings(const MachineInstr &MI) const override | llvm::AArch64RegisterBankInfo | virtual |
| getInstrMapping(const MachineInstr &MI) const override | llvm::AArch64RegisterBankInfo | virtual |
| getInstrMappingImpl(const MachineInstr &MI) const | llvm::RegisterBankInfo | protected |
| getInstrPossibleMappings(const MachineInstr &MI) const | llvm::RegisterBankInfo | |
| getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const | llvm::RegisterBankInfo | inline |
| getInvalidInstructionMapping() const | llvm::RegisterBankInfo | inline |
| getMaximumSize(unsigned RegBankID) const | llvm::RegisterBankInfo | inline |
| getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | protected |
| getNumRegBanks() const | llvm::RegisterBankInfo | inline |
| getOperandsMapping(Iterator Begin, Iterator End) const | llvm::RegisterBankInfo | protected |
| getOperandsMapping(const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const | llvm::RegisterBankInfo | protected |
| getOperandsMapping(std::initializer_list< const ValueMapping * > OpdsMapping) const | llvm::RegisterBankInfo | protected |
| getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const | llvm::RegisterBankInfo | protected |
| getRegBank(unsigned ID) | llvm::RegisterBankInfo | inlineprotected |
| getRegBank(unsigned ID) const | llvm::RegisterBankInfo | inline |
| getRegBank(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
| getRegBankBaseIdxOffset(unsigned RBIdx, TypeSize Size) | llvm::AArch64GenRegisterBankInfo | protectedstatic |
| getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const | llvm::RegisterBankInfo | |
| getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override | llvm::AArch64RegisterBankInfo | virtual |
| getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
| getValueMapping(PartialMappingIdx RBIdx, TypeSize Size) | llvm::AArch64GenRegisterBankInfo | protectedstatic |
| llvm::RegisterBankInfo::getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const | llvm::RegisterBankInfo | protected |
| llvm::RegisterBankInfo::getValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns) const | llvm::RegisterBankInfo | protected |
| HwMode | llvm::RegisterBankInfo | protected |
| InstructionMappings typedef | llvm::RegisterBankInfo | |
| InvalidIdx enum value | llvm::AArch64GenRegisterBankInfo | protected |
| InvalidMappingID | llvm::RegisterBankInfo | static |
| isDivergentRegBank(const RegisterBank *RB) const | llvm::RegisterBankInfo | inlinevirtual |
| Last3OpsIdx enum value | llvm::AArch64GenRegisterBankInfo | protected |
| LastCrossRegCpyIdx enum value | llvm::AArch64GenRegisterBankInfo | protected |
| MapOfInstructionMappings | llvm::RegisterBankInfo | mutableprotected |
| MapOfOperandsMappings | llvm::RegisterBankInfo | mutableprotected |
| MapOfPartialMappings | llvm::RegisterBankInfo | mutableprotected |
| MapOfValueMappings | llvm::RegisterBankInfo | mutableprotected |
| NumRegBanks | llvm::RegisterBankInfo | protected |
| PartialMappingIdx enum name | llvm::AArch64GenRegisterBankInfo | protected |
| PartMappings | llvm::AArch64GenRegisterBankInfo | protectedstatic |
| PhysRegMinimalRCs | llvm::RegisterBankInfo | mutableprotected |
| PMI_FirstFPR enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_FirstGPR enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_FPR128 enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_FPR16 enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_FPR256 enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_FPR32 enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_FPR512 enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_FPR64 enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_GPR128 enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_GPR32 enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_GPR64 enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_LastFPR enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_LastGPR enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_Min enum value | llvm::AArch64GenRegisterBankInfo | protected |
| PMI_None enum value | llvm::AArch64GenRegisterBankInfo | protected |
| RegBanks | llvm::RegisterBankInfo | protected |
| RegisterBankInfo(const RegisterBank **RegBanks, unsigned NumRegBanks, const unsigned *Sizes, unsigned HwMode) | llvm::RegisterBankInfo | protected |
| RegisterBankInfo() | llvm::RegisterBankInfo | inlineprotected |
| Shift64Imm enum value | llvm::AArch64GenRegisterBankInfo | protected |
| Sizes | llvm::RegisterBankInfo | protected |
| ValMappings | llvm::AArch64GenRegisterBankInfo | protectedstatic |
| ValueMappingIdx enum name | llvm::AArch64GenRegisterBankInfo | protected |
| verify(const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
| ~RegisterBankInfo()=default | llvm::RegisterBankInfo | virtual |
