LLVM  12.0.0git
llvm::TargetPassConfig Member List

This is the complete list of members for llvm::TargetPassConfig, including all inherited members.

addBlockPlacement()llvm::TargetPassConfigprotectedvirtual
addCodeGenPrepare()llvm::TargetPassConfigvirtual
addCoreISelPasses()llvm::TargetPassConfigprotected
addDebugifyPass()llvm::TargetPassConfig
addFastRegAlloc()llvm::TargetPassConfigprotectedvirtual
addGCPasses()llvm::TargetPassConfigprotectedvirtual
addGlobalInstructionSelect()llvm::TargetPassConfiginlinevirtual
addILPOpts()llvm::TargetPassConfiginlineprotectedvirtual
addInstSelector()llvm::TargetPassConfiginlinevirtual
addIRPasses()llvm::TargetPassConfigvirtual
addIRTranslator()llvm::TargetPassConfiginlinevirtual
addISelPasses()llvm::TargetPassConfig
addISelPrepare()llvm::TargetPassConfigvirtual
addLegalizeMachineIR()llvm::TargetPassConfiginlinevirtual
addMachineLateOptimization()llvm::TargetPassConfigprotectedvirtual
addMachinePasses()llvm::TargetPassConfigvirtual
addMachinePostPasses(const std::string &Banner, bool AllowPrint=true, bool AllowVerify=true, bool AllowStrip=true)llvm::TargetPassConfig
addMachinePrePasses(bool AllowDebugify=true)llvm::TargetPassConfig
addMachineSSAOptimization()llvm::TargetPassConfigprotectedvirtual
addOptimizedRegAlloc()llvm::TargetPassConfigprotectedvirtual
addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)llvm::TargetPassConfigprotected
addPass(Pass *P, bool verifyAfter=true, bool printAfter=true)llvm::TargetPassConfigprotected
addPassesToHandleExceptions()llvm::TargetPassConfig
addPostRegAlloc()llvm::TargetPassConfiginlineprotectedvirtual
addPostRewrite()llvm::TargetPassConfiginlineprotectedvirtual
addPreEmitPass()llvm::TargetPassConfiginlineprotectedvirtual
addPreEmitPass2()llvm::TargetPassConfiginlineprotectedvirtual
addPreGlobalInstructionSelect()llvm::TargetPassConfiginlinevirtual
addPreISel()llvm::TargetPassConfiginlineprotectedvirtual
addPreLegalizeMachineIR()llvm::TargetPassConfiginlinevirtual
addPreRegAlloc()llvm::TargetPassConfiginlineprotectedvirtual
addPreRegBankSelect()llvm::TargetPassConfiginlinevirtual
addPreRewrite()llvm::TargetPassConfiginlineprotectedvirtual
addPreSched2()llvm::TargetPassConfiginlineprotectedvirtual
addPrintPass(const std::string &Banner)llvm::TargetPassConfig
addRegAssignmentFast()llvm::TargetPassConfigprotectedvirtual
addRegAssignmentOptimized()llvm::TargetPassConfigprotectedvirtual
addRegBankSelect()llvm::TargetPassConfiginlinevirtual
addStripDebugPass()llvm::TargetPassConfig
addVerifyPass(const std::string &Banner)llvm::TargetPassConfig
assignPassManager(PMStack &PMS, PassManagerType T) overridellvm::ModulePassvirtual
createPass(AnalysisID ID)llvm::Passstatic
createPostMachineScheduler(MachineSchedContext *C) constllvm::TargetPassConfiginlinevirtual
createPrinterPass(raw_ostream &OS, const std::string &Banner) const overridellvm::ModulePassvirtual
createRegAllocPass(bool Optimized)llvm::TargetPassConfigprotectedvirtual
createTargetRegisterAllocator(bool Optimized)llvm::TargetPassConfigprotectedvirtual
default(generic) machine scheduler. */virtual ScheduleDAGInstrs *createMachineScheduler(MachineSchedContext *C) constllvm::TargetPassConfiginline
disablePass(AnalysisID PassID)llvm::TargetPassConfiginline
DisableVerifyllvm::TargetPassConfigprotected
doFinalization(Module &)llvm::Passinlinevirtual
doInitialization(Module &)llvm::Passinlinevirtual
dump() constllvm::Pass
dumpPassStructure(unsigned Offset=0)llvm::Passvirtual
enablePass(AnalysisID PassID)llvm::TargetPassConfiginline
EnableTailMergellvm::TargetPassConfigprotected
getAdjustedAnalysisPointer(AnalysisID ID)llvm::Passvirtual
getAnalysis() constllvm::Pass
getAnalysis(Function &F, bool *Changed=nullptr)llvm::Pass
getAnalysisID(AnalysisID PI) constllvm::Pass
getAnalysisID(AnalysisID PI, Function &F, bool *Changed=nullptr)llvm::Pass
getAnalysisIfAvailable() constllvm::Pass
getAnalysisUsage(AnalysisUsage &) constllvm::Passvirtual
getAsImmutablePass() overridellvm::ImmutablePassinlinevirtual
getAsPMDataManager()llvm::Passvirtual
getCSEConfig() constllvm::TargetPassConfigvirtual
getEnableTailMerge() constllvm::TargetPassConfiginline
getLimitedCodeGenPipelineReason(const char *Separator="/")llvm::TargetPassConfigstatic
getOptimizeRegAlloc() constllvm::TargetPassConfig
getOptLevel() constllvm::TargetPassConfig
getPassID() constllvm::Passinline
getPassKind() constllvm::Passinline
getPassName() constllvm::Passvirtual
getPassSubstitution(AnalysisID StandardID) constllvm::TargetPassConfig
getPotentialPassManagerType() const overridellvm::ModulePassvirtual
getResolver() constllvm::Passinline
getTM() constllvm::TargetPassConfiginline
hasLimitedCodeGenPipeline()llvm::TargetPassConfigstatic
IDllvm::TargetPassConfigstatic
ImmutablePass(char &pid)llvm::ImmutablePassinlineexplicit
Implllvm::TargetPassConfigprotected
Initializedllvm::TargetPassConfigprotected
initializePass()llvm::ImmutablePassvirtual
insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true, bool PrintAfter=true)llvm::TargetPassConfig
isGISelCSEEnabled() constllvm::TargetPassConfigvirtual
isGlobalISelAbortEnabled() constllvm::TargetPassConfig
isPassSubstitutedOrOverridden(AnalysisID ID) constllvm::TargetPassConfig
lookupPassInfo(const void *TI)llvm::Passstatic
lookupPassInfo(StringRef Arg)llvm::Passstatic
ModulePass(char &pid)llvm::ModulePassinlineexplicit
mustPreserveAnalysisID(char &AID) constllvm::Pass
operator=(const Pass &)=deletellvm::Pass
Pass(PassKind K, char &pid)llvm::Passinlineexplicit
Pass(const Pass &)=deletellvm::Pass
preparePassManager(PMStack &)llvm::Passvirtual
print(raw_ostream &OS, const Module *M) constllvm::Passvirtual
printAndVerify(const std::string &Banner)llvm::TargetPassConfig
releaseMemory()llvm::Passvirtual
reportDiagnosticWhenGlobalISelFallback() constllvm::TargetPassConfigvirtual
RequireCodeGenSCCOrderllvm::TargetPassConfigprotected
requiresCodeGenSCCOrder() constllvm::TargetPassConfiginline
runOnModule(Module &) overridellvm::ImmutablePassinlinevirtual
setDisableVerify(bool Disable)llvm::TargetPassConfiginline
setEnableTailMerge(bool Enable)llvm::TargetPassConfiginline
setInitialized()llvm::TargetPassConfiginline
setOpt(bool &Opt, bool Val)llvm::TargetPassConfigprotected
setRequiresCodeGenSCCOrder(bool Enable=true)llvm::TargetPassConfiginline
setResolver(AnalysisResolver *AR)llvm::Pass
skipModule(Module &M) constllvm::ModulePassprotected
substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)llvm::TargetPassConfig
TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)llvm::TargetPassConfig
TargetPassConfig()llvm::TargetPassConfig
TMllvm::TargetPassConfigprotected
usingDefaultRegAlloc() constllvm::TargetPassConfig
verifyAnalysis() constllvm::Passvirtual
willCompleteCodeGenPipeline()llvm::TargetPassConfigstatic
~ImmutablePass() overridellvm::ImmutablePass
~ModulePass() overridellvm::ModulePass
~Pass()llvm::Passvirtual
~TargetPassConfig() overridellvm::TargetPassConfig