These are in-progress notes for the upcoming LLVM 3.5 release. You may prefer the LLVM 3.4 Release Notes.
This document contains the release notes for the LLVM Compiler Infrastructure, release 3.5. Here we describe the status of LLVM, including major improvements from the previous release, improvements in various subprojects of LLVM, and some of the current users of the code. All LLVM releases may be downloaded from the LLVM releases web site.
For more information about LLVM, including information about the latest release, please check out the main LLVM web site. If you have questions or comments, the LLVM Developer’s Mailing List is a good place to send them.
Note that if you are reading this file from a Subversion checkout or the main LLVM web page, this document applies to the next release, not the current one. To see the release notes for a specific release, please see the releases page.
Since release 3.3, a lot of new features have been included in the ARM back-end but weren’t production ready (ie. well tested) on release 3.4. Just after the 3.4 release, we started heavily testing two major parts of the back-end: the integrated assembler (IAS) and the ARM exception handling (EHABI), and now they are enabled by default on LLVM/Clang.
The IAS received a lot of GNU extensions and directives, as well as some specific pre-UAL instructions. Not all remaining directives will be implemented, as we made judgement calls on the need versus the complexity, and have chosen simplicity and future compatibility where hard decisions had to be made. The major difference is, as stated above, the IAS validates all inline ASM, not just for object emission, and that cause trouble with some uses of inline ASM as pre-processor magic.
So, while the IAS is good enough to compile large projects (including most of the Linux kernel), there are a few things that we can’t (and probably won’t) do. For those cases, please use -fno-integrated-as in Clang.
Exception handling is another big change. After extensive testing and changes to cooperate with Dwarf unwinding, EHABI is enabled by default. The options -arm-enable-ehabi and -arm-enable-ehabi-descriptors, which were used to enable EHABI in the previous releases, are removed now.
This means all ARM code will emit EH unwind tables, or CFI unwinding (for debug/profiling), or both. To avoid run-time inconsistencies, C code will also emit EH tables (in case they interoperate with C++ code), as is the case for other architectures (ex. x86_64).
There has been a large amount of improvements to the MIPS target which can be broken down into subtarget, ABI, and Integrated Assembler changes.
Added support for Release 6 of the MIPS32 and MIPS64 architecture (MIPS32r6 and MIPS64r6). Release 6 makes a number of significant changes to the MIPS32 and MIPS64 architectures. For example, FPU registers are always 64-bits wide, FPU NaN values conform to IEEE 754 (2008), and the unaligned memory instructions (such as lwl and lwr) have been replaced with a requirement for ordinary memory operations to support unaligned operations. Full details of MIPS32 and MIPS64 Release 6 can be found on the MIPS64 Architecture page at Imagination Technologies.
This release also adds experimental support for MIPS-IV, cnMIPS, and Cavium Octeon CPU’s.
Support for the MIPS SIMD Architecture (MSA) has been improved to support MSA on MIPS64.
Support for IEEE 754 (2008) NaN values has been added.
There has also been considerable ABI work since the 3.4 release. This release adds support for the N32 ABI, the O32-FPXX ABI Extension, the O32-FP64 ABI Extension, and the O32-FP64A ABI Extension.
The N32 ABI is an existing ABI that has now been implemented in LLVM. It is a 64-bit ABI that is similar to N64 but retains 32-bit pointers. N64 remains the default 64-bit ABI in LLVM. This differs from GCC where N32 is the default 64-bit ABI.
The O32-FPXX ABI Extension is 100% compatible with the O32-ABI and the O32-FP64 ABI Extension and may be linked with either but may not be linked with both of these simultaneously. It extends the O32 ABI to allow the same code to execute without modification on processors with 32-bit FPU registers as well as 64-bit FPU registers. The O32-FPXX ABI Extension is enabled by default for the O32 ABI on mips*-img-linux-gnu and mips*-mti-linux-gnu triples and is selected with -mfpxx. It is expected that future releases of LLVM will enable the FPXX Extension for O32 on all triples.
The O32-FP64 ABI Extension is an extension to the O32 ABI to fully exploit FPU’s with 64-bit registers and is enabled with -mfp64. This replaces an undocumented and unsupported O32 extension which was previously enabled with -mfp64. It is 100% compatible with the O32-FPXX ABI Extension.
The O32-FP64A ABI Extension is a restricted form of the O32-FP64 ABI Extension which allows interlinking with unmodified binaries that use the base O32 ABI.
The MIPS Integrated Assembler has undergone a substantial overhaul including a rewrite of the assembly parser. It’s not ready for general use in this release but adventurous users may wish to enable it using -fintegrated-as.
In this release, the integrated assembler supports the majority of MIPS-I, MIPS-II, MIPS-III, MIPS-IV, MIPS-V, MIPS32, MIPS32r2, MIPS32r6, MIPS64, MIPS64r2, and MIPS64r6 as well as some of the Application Specific Extensions such as MSA. It also supports several of the MIPS specific assembler directives such as .set, .module, .cpload, etc.
The PowerPC 64-bit Little Endian subtarget (powerpc64le-unknown-linux-gnu) is now fully supported. This includes support for the Altivec instruction set.
The Power Architecture 64-Bit ELFv2 ABI Specification is now supported, and is the default ABI for Little Endian. The ELFv1 ABI remains the default ABI for Big Endian. Currently, it is not possible to override these defaults. That capability will be available (albeit not recommended) in a future release.
Links to the ELFv2 ABI specification and to the Power ISA Version 2.07 specification may be found here (free registration required). Efforts are underway to move this to a location that doesn’t require registration, but the planned site isn’t ready yet.
Experimental support for the VSX instruction set introduced with ISA 2.06 is now available using the -mvsx switch. Work remains on this, so it is not recommended for production use. VSX is disabled for Little Endian regardless of this switch setting.
Load/store cost estimates have been improved.
Constant hoisting has been enabled.
Global named register support has been enabled.
Initial support for PIC code has been added for the 32-bit ELF subtarget. Further support will be available in a future release.
An exciting aspect of LLVM is that it is used as an enabling technology for a lot of other language and tools projects. This section lists some of the projects that have already been updated to work with LLVM 3.5.
A wide variety of additional information is available on the LLVM web page, in particular in the documentation section. The web page also contains versions of the API documentation which is up-to-date with the Subversion version of the source code. You can access versions of these documents specific to this release by going into the llvm/docs/ directory in the LLVM tree.
If you have any questions or comments about LLVM, please feel free to contact us via the mailing lists.