LLVM 10.0.0 Release Notes


These are in-progress notes for the upcoming LLVM 10 release. Release notes for previous releases can be found on the Download Page.


This document contains the release notes for the LLVM Compiler Infrastructure, release 10.0.0. Here we describe the status of LLVM, including major improvements from the previous release, improvements in various subprojects of LLVM, and some of the current users of the code. All LLVM releases may be downloaded from the LLVM releases web site.

For more information about LLVM, including information about the latest release, please check out the main LLVM web site. If you have questions or comments, the LLVM Developer’s Mailing List is a good place to send them.

Note that if you are reading this file from a Subversion checkout or the main LLVM web page, this document applies to the next release, not the current one. To see the release notes for a specific release, please see the releases page.

Non-comprehensive list of changes in this release

  • The ISD::FP_ROUND_INREG opcode and related code was removed from SelectionDAG.
  • Enabled MemorySSA as a loop dependency.

Changes to the LLVM IR

  • Unnamed function arguments now get printed with their automatically generated name (e.g. “i32 %0”) in definitions. This may require front-ends to update their tests; if so there is a script utils/add_argument_names.py that correctly converted 80-90% of Clang tests. Some manual work will almost certainly still be needed.

Changes to the ARM Backend

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Changes to the MIPS Target

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Changes to the PowerPC Target

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Changes to the X86 Target

During this release …
  • Less than 128 bit vector types, v2i32, v4i16, v2i16, v8i8, v4i8, and v2i8, are now stored in the lower bits of an xmm register and the upper bits are undefined. Previously the elements were spread apart with undefined bits in between them.
  • v32i8 and v64i8 vectors with AVX512F enabled, but AVX512BW disabled will now be passed in ZMM registers for calls and returns. Previously they were passed in two YMM registers. Old behavior can be enabled by passing -x86-enable-old-knl-abi
  • -mprefer-vector-width=256 is now the default behavior skylake-avx512 and later Intel CPUs. This tries to limit the use of 512-bit registers which can cause a decrease in CPU frequency on these CPUs. This can be re-enabled by passing -mprefer-vector-width=512 to clang or passing -mattr=-prefer-256-bit to llc.

Changes to the AVR Target

During this release …
  • Deprecated the mpx feature flag for the Intel MPX instructions. There were no intrinsics for this feature. This change only this effects the results returned by getHostCPUFeatures on CPUs that implement the MPX instructions.

Changes to the WebAssembly Target

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Additional Information

A wide variety of additional information is available on the LLVM web page, in particular in the documentation section. The web page also contains versions of the API documentation which is up-to-date with the Subversion version of the source code. You can access versions of these documents specific to this release by going into the llvm/docs/ directory in the LLVM tree.

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