Syntax of GFX10 Instructions

Notation

Notation used in this document is explained here.

Introduction

An overview of generic syntax and other features of AMDGPU instructions may be found in this document.

Instructions

DPP16

INSTRUCTION             DST0  DST1 SRC0       SRC1      SRC2   MODIFIERS
———————————————————————————————————————————————————————————————————————————————————————————————————————————
v_add_co_ci_u32_dpp     vdst, vcc, vsrc0,     vsrc1,    vcc    dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_add_f16_dpp           vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_add_f32_dpp           vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_add_nc_u32_dpp        vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_and_b32_dpp           vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_ashrrev_i32_dpp       vdst,      vsrc0:u32, vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_bfrev_b32_dpp         vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_ceil_f16_dpp          vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_ceil_f32_dpp          vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cos_f16_dpp           vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cos_f32_dpp           vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_f16_f32_dpp       vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_f16_i16_dpp       vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_f16_u16_dpp       vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_f32_f16_dpp       vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_f32_i32_dpp       vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_f32_u32_dpp       vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_f32_ubyte0_dpp    vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_f32_ubyte1_dpp    vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_f32_ubyte2_dpp    vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_f32_ubyte3_dpp    vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_flr_i32_f32_dpp   vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_i16_f16_dpp       vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_i32_f32_dpp       vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_norm_i16_f16_dpp  vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_norm_u16_f16_dpp  vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_off_f32_i4_dpp    vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_rpi_i32_f32_dpp   vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_u16_f16_dpp       vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_cvt_u32_f32_dpp       vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_exp_f16_dpp           vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_exp_f32_dpp           vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_ffbh_i32_dpp          vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_ffbh_u32_dpp          vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_ffbl_b32_dpp          vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_floor_f16_dpp         vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_floor_f32_dpp         vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_fmac_f16_dpp          vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_fmac_f32_dpp          vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_fract_f16_dpp         vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_fract_f32_dpp         vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_frexp_exp_i16_f16_dpp vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_frexp_exp_i32_f32_dpp vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_frexp_mant_f16_dpp    vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_frexp_mant_f32_dpp    vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_ldexp_f16_dpp         vdst,      vsrc0:m,   vsrc1:i16        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_log_f16_dpp           vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_log_f32_dpp           vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_lshlrev_b32_dpp       vdst,      vsrc0:u32, vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_lshrrev_b32_dpp       vdst,      vsrc0:u32, vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_mac_f32_dpp           vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_max_f16_dpp           vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_max_f32_dpp           vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_max_i32_dpp           vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_max_u32_dpp           vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_min_f16_dpp           vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_min_f32_dpp           vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_min_i32_dpp           vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_min_u32_dpp           vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_mov_b32_dpp           vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_mul_f16_dpp           vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_mul_f32_dpp           vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_mul_hi_i32_i24_dpp    vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_mul_hi_u32_u24_dpp    vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_mul_i32_i24_dpp       vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_mul_legacy_f32_dpp    vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_mul_u32_u24_dpp       vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_not_b32_dpp           vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_or_b32_dpp            vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_rcp_f16_dpp           vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_rcp_f32_dpp           vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_rcp_iflag_f32_dpp     vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_rndne_f16_dpp         vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_rndne_f32_dpp         vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_rsq_f16_dpp           vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_rsq_f32_dpp           vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_sat_pk_u8_i16_dpp     vdst,      vsrc                        dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_sin_f16_dpp           vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_sin_f32_dpp           vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_sqrt_f16_dpp          vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_sqrt_f32_dpp          vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_sub_co_ci_u32_dpp     vdst, vcc, vsrc0,     vsrc1,    vcc    dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_sub_f16_dpp           vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_sub_f32_dpp           vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_sub_nc_u32_dpp        vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_subrev_co_ci_u32_dpp  vdst, vcc, vsrc0,     vsrc1,    vcc    dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_subrev_f16_dpp        vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_subrev_f32_dpp        vdst,      vsrc0:m,   vsrc1:m          dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_subrev_nc_u32_dpp     vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_trunc_f16_dpp         vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_trunc_f32_dpp         vdst,      vsrc:m                      dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_xnor_b32_dpp          vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi
v_xor_b32_dpp           vdst,      vsrc0,     vsrc1            dpp16_ctrl row_mask bank_mask bound_ctrl fi

DPP8

INSTRUCTION                    DST0      DST1      SRC0       SRC1      SRC2           MODIFIERS
———————————————————————————————————————————————————————————————————————————————————————————————————
v_add_co_ci_u32_dpp            vdst,     vcc,      vsrc0,     vsrc1,    vcc            dpp8_sel fi
v_add_f16_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_add_f32_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_add_nc_u32_dpp               vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_and_b32_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_ashrrev_i32_dpp              vdst,               vsrc0:u32, vsrc1                    dpp8_sel fi
v_bfrev_b32_dpp                vdst,               vsrc                                dpp8_sel fi
v_ceil_f16_dpp                 vdst,               vsrc                                dpp8_sel fi
v_ceil_f32_dpp                 vdst,               vsrc                                dpp8_sel fi
v_cos_f16_dpp                  vdst,               vsrc                                dpp8_sel fi
v_cos_f32_dpp                  vdst,               vsrc                                dpp8_sel fi
v_cvt_f16_f32_dpp              vdst,               vsrc                                dpp8_sel fi
v_cvt_f16_i16_dpp              vdst,               vsrc                                dpp8_sel fi
v_cvt_f16_u16_dpp              vdst,               vsrc                                dpp8_sel fi
v_cvt_f32_f16_dpp              vdst,               vsrc                                dpp8_sel fi
v_cvt_f32_i32_dpp              vdst,               vsrc                                dpp8_sel fi
v_cvt_f32_u32_dpp              vdst,               vsrc                                dpp8_sel fi
v_cvt_f32_ubyte0_dpp           vdst,               vsrc                                dpp8_sel fi
v_cvt_f32_ubyte1_dpp           vdst,               vsrc                                dpp8_sel fi
v_cvt_f32_ubyte2_dpp           vdst,               vsrc                                dpp8_sel fi
v_cvt_f32_ubyte3_dpp           vdst,               vsrc                                dpp8_sel fi
v_cvt_flr_i32_f32_dpp          vdst,               vsrc                                dpp8_sel fi
v_cvt_i16_f16_dpp              vdst,               vsrc                                dpp8_sel fi
v_cvt_i32_f32_dpp              vdst,               vsrc                                dpp8_sel fi
v_cvt_norm_i16_f16_dpp         vdst,               vsrc                                dpp8_sel fi
v_cvt_norm_u16_f16_dpp         vdst,               vsrc                                dpp8_sel fi
v_cvt_off_f32_i4_dpp           vdst,               vsrc                                dpp8_sel fi
v_cvt_rpi_i32_f32_dpp          vdst,               vsrc                                dpp8_sel fi
v_cvt_u16_f16_dpp              vdst,               vsrc                                dpp8_sel fi
v_cvt_u32_f32_dpp              vdst,               vsrc                                dpp8_sel fi
v_exp_f16_dpp                  vdst,               vsrc                                dpp8_sel fi
v_exp_f32_dpp                  vdst,               vsrc                                dpp8_sel fi
v_ffbh_i32_dpp                 vdst,               vsrc                                dpp8_sel fi
v_ffbh_u32_dpp                 vdst,               vsrc                                dpp8_sel fi
v_ffbl_b32_dpp                 vdst,               vsrc                                dpp8_sel fi
v_floor_f16_dpp                vdst,               vsrc                                dpp8_sel fi
v_floor_f32_dpp                vdst,               vsrc                                dpp8_sel fi
v_fmac_f16_dpp                 vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_fmac_f32_dpp                 vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_fract_f16_dpp                vdst,               vsrc                                dpp8_sel fi
v_fract_f32_dpp                vdst,               vsrc                                dpp8_sel fi
v_frexp_exp_i16_f16_dpp        vdst,               vsrc                                dpp8_sel fi
v_frexp_exp_i32_f32_dpp        vdst,               vsrc                                dpp8_sel fi
v_frexp_mant_f16_dpp           vdst,               vsrc                                dpp8_sel fi
v_frexp_mant_f32_dpp           vdst,               vsrc                                dpp8_sel fi
v_ldexp_f16_dpp                vdst,               vsrc0,     vsrc1:i16                dpp8_sel fi
v_log_f16_dpp                  vdst,               vsrc                                dpp8_sel fi
v_log_f32_dpp                  vdst,               vsrc                                dpp8_sel fi
v_lshlrev_b32_dpp              vdst,               vsrc0:u32, vsrc1                    dpp8_sel fi
v_lshrrev_b32_dpp              vdst,               vsrc0:u32, vsrc1                    dpp8_sel fi
v_mac_f32_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_max_f16_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_max_f32_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_max_i32_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_max_u32_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_min_f16_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_min_f32_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_min_i32_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_min_u32_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_mov_b32_dpp                  vdst,               vsrc                                dpp8_sel fi
v_mul_f16_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_mul_f32_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_mul_hi_i32_i24_dpp           vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_mul_hi_u32_u24_dpp           vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_mul_i32_i24_dpp              vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_mul_legacy_f32_dpp           vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_mul_u32_u24_dpp              vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_not_b32_dpp                  vdst,               vsrc                                dpp8_sel fi
v_or_b32_dpp                   vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_rcp_f16_dpp                  vdst,               vsrc                                dpp8_sel fi
v_rcp_f32_dpp                  vdst,               vsrc                                dpp8_sel fi
v_rcp_iflag_f32_dpp            vdst,               vsrc                                dpp8_sel fi
v_rndne_f16_dpp                vdst,               vsrc                                dpp8_sel fi
v_rndne_f32_dpp                vdst,               vsrc                                dpp8_sel fi
v_rsq_f16_dpp                  vdst,               vsrc                                dpp8_sel fi
v_rsq_f32_dpp                  vdst,               vsrc                                dpp8_sel fi
v_sat_pk_u8_i16_dpp            vdst,               vsrc                                dpp8_sel fi
v_sin_f16_dpp                  vdst,               vsrc                                dpp8_sel fi
v_sin_f32_dpp                  vdst,               vsrc                                dpp8_sel fi
v_sqrt_f16_dpp                 vdst,               vsrc                                dpp8_sel fi
v_sqrt_f32_dpp                 vdst,               vsrc                                dpp8_sel fi
v_sub_co_ci_u32_dpp            vdst,     vcc,      vsrc0,     vsrc1,    vcc            dpp8_sel fi
v_sub_f16_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_sub_f32_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_sub_nc_u32_dpp               vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_subrev_co_ci_u32_dpp         vdst,     vcc,      vsrc0,     vsrc1,    vcc            dpp8_sel fi
v_subrev_f16_dpp               vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_subrev_f32_dpp               vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_subrev_nc_u32_dpp            vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_trunc_f16_dpp                vdst,               vsrc                                dpp8_sel fi
v_trunc_f32_dpp                vdst,               vsrc                                dpp8_sel fi
v_xnor_b32_dpp                 vdst,               vsrc0,     vsrc1                    dpp8_sel fi
v_xor_b32_dpp                  vdst,               vsrc0,     vsrc1                    dpp8_sel fi

DS

INSTRUCTION                    DST         SRC0      SRC1      SRC2           MODIFIERS
——————————————————————————————————————————————————————————————————————————————————————————————————
ds_add_f32                                 vaddr,    vdata                    offset16 gds
ds_add_rtn_f32                 vdst,       vaddr,    vdata                    offset16 gds
ds_add_rtn_u32                 vdst,       vaddr,    vdata                    offset16 gds
ds_add_rtn_u64                 vdst,       vaddr,    vdata                    offset16 gds
ds_add_src2_f32                            vaddr                              offset16 gds
ds_add_src2_u32                            vaddr                              offset16 gds
ds_add_src2_u64                            vaddr                              offset16 gds
ds_add_u32                                 vaddr,    vdata                    offset16 gds
ds_add_u64                                 vaddr,    vdata                    offset16 gds
ds_and_b32                                 vaddr,    vdata                    offset16 gds
ds_and_b64                                 vaddr,    vdata                    offset16 gds
ds_and_rtn_b32                 vdst,       vaddr,    vdata                    offset16 gds
ds_and_rtn_b64                 vdst,       vaddr,    vdata                    offset16 gds
ds_and_src2_b32                            vaddr                              offset16 gds
ds_and_src2_b64                            vaddr                              offset16 gds
ds_append                      vdst                                           offset16 gds
ds_bpermute_b32                vdst,       vaddr,    vdata                    offset16
ds_cmpst_b32                               vaddr,    vdata0,   vdata1         offset16 gds
ds_cmpst_b64                               vaddr,    vdata0,   vdata1         offset16 gds
ds_cmpst_f32                               vaddr,    vdata0,   vdata1         offset16 gds
ds_cmpst_f64                               vaddr,    vdata0,   vdata1         offset16 gds
ds_cmpst_rtn_b32               vdst,       vaddr,    vdata0,   vdata1         offset16 gds
ds_cmpst_rtn_b64               vdst,       vaddr,    vdata0,   vdata1         offset16 gds
ds_cmpst_rtn_f32               vdst,       vaddr,    vdata0,   vdata1         offset16 gds
ds_cmpst_rtn_f64               vdst,       vaddr,    vdata0,   vdata1         offset16 gds
ds_condxchg32_rtn_b64          vdst,       vaddr,    vdata                    offset16 gds
ds_consume                     vdst                                           offset16 gds
ds_dec_rtn_u32                 vdst,       vaddr,    vdata                    offset16 gds
ds_dec_rtn_u64                 vdst,       vaddr,    vdata                    offset16 gds
ds_dec_src2_u32                            vaddr                              offset16 gds
ds_dec_src2_u64                            vaddr                              offset16 gds
ds_dec_u32                                 vaddr,    vdata                    offset16 gds
ds_dec_u64                                 vaddr,    vdata                    offset16 gds
ds_gws_barrier                             vdata                              offset16 gds
ds_gws_init                                vdata                              offset16 gds
ds_gws_sema_br                             vdata                              offset16 gds
ds_gws_sema_p                                                                 offset16 gds
ds_gws_sema_release_all                                                       offset16 gds
ds_gws_sema_v                                                                 offset16 gds
ds_inc_rtn_u32                 vdst,       vaddr,    vdata                    offset16 gds
ds_inc_rtn_u64                 vdst,       vaddr,    vdata                    offset16 gds
ds_inc_src2_u32                            vaddr                              offset16 gds
ds_inc_src2_u64                            vaddr                              offset16 gds
ds_inc_u32                                 vaddr,    vdata                    offset16 gds
ds_inc_u64                                 vaddr,    vdata                    offset16 gds
ds_max_f32                                 vaddr,    vdata                    offset16 gds
ds_max_f64                                 vaddr,    vdata                    offset16 gds
ds_max_i32                                 vaddr,    vdata                    offset16 gds
ds_max_i64                                 vaddr,    vdata                    offset16 gds
ds_max_rtn_f32                 vdst,       vaddr,    vdata                    offset16 gds
ds_max_rtn_f64                 vdst,       vaddr,    vdata                    offset16 gds
ds_max_rtn_i32                 vdst,       vaddr,    vdata                    offset16 gds
ds_max_rtn_i64                 vdst,       vaddr,    vdata                    offset16 gds
ds_max_rtn_u32                 vdst,       vaddr,    vdata                    offset16 gds
ds_max_rtn_u64                 vdst,       vaddr,    vdata                    offset16 gds
ds_max_src2_f32                            vaddr                              offset16 gds
ds_max_src2_f64                            vaddr                              offset16 gds
ds_max_src2_i32                            vaddr                              offset16 gds
ds_max_src2_i64                            vaddr                              offset16 gds
ds_max_src2_u32                            vaddr                              offset16 gds
ds_max_src2_u64                            vaddr                              offset16 gds
ds_max_u32                                 vaddr,    vdata                    offset16 gds
ds_max_u64                                 vaddr,    vdata                    offset16 gds
ds_min_f32                                 vaddr,    vdata                    offset16 gds
ds_min_f64                                 vaddr,    vdata                    offset16 gds
ds_min_i32                                 vaddr,    vdata                    offset16 gds
ds_min_i64                                 vaddr,    vdata                    offset16 gds
ds_min_rtn_f32                 vdst,       vaddr,    vdata                    offset16 gds
ds_min_rtn_f64                 vdst,       vaddr,    vdata                    offset16 gds
ds_min_rtn_i32                 vdst,       vaddr,    vdata                    offset16 gds
ds_min_rtn_i64                 vdst,       vaddr,    vdata                    offset16 gds
ds_min_rtn_u32                 vdst,       vaddr,    vdata                    offset16 gds
ds_min_rtn_u64                 vdst,       vaddr,    vdata                    offset16 gds
ds_min_src2_f32                            vaddr                              offset16 gds
ds_min_src2_f64                            vaddr                              offset16 gds
ds_min_src2_i32                            vaddr                              offset16 gds
ds_min_src2_i64                            vaddr                              offset16 gds
ds_min_src2_u32                            vaddr                              offset16 gds
ds_min_src2_u64                            vaddr                              offset16 gds
ds_min_u32                                 vaddr,    vdata                    offset16 gds
ds_min_u64                                 vaddr,    vdata                    offset16 gds
ds_mskor_b32                               vaddr,    vdata0,   vdata1         offset16 gds
ds_mskor_b64                               vaddr,    vdata0,   vdata1         offset16 gds
ds_mskor_rtn_b32               vdst,       vaddr,    vdata0,   vdata1         offset16 gds
ds_mskor_rtn_b64               vdst,       vaddr,    vdata0,   vdata1         offset16 gds
ds_nop
ds_or_b32                                  vaddr,    vdata                    offset16 gds
ds_or_b64                                  vaddr,    vdata                    offset16 gds
ds_or_rtn_b32                  vdst,       vaddr,    vdata                    offset16 gds
ds_or_rtn_b64                  vdst,       vaddr,    vdata                    offset16 gds
ds_or_src2_b32                             vaddr                              offset16 gds
ds_or_src2_b64                             vaddr                              offset16 gds
ds_ordered_count               vdst,       vaddr                              offset16 gds
ds_permute_b32                 vdst,       vaddr,    vdata                    offset16
ds_read2_b32                   vdst:b32x2, vaddr                              offset8 offset8 gds
ds_read2_b64                   vdst:b64x2, vaddr                              offset8 offset8 gds
ds_read2st64_b32               vdst:b32x2, vaddr                              offset8 offset8 gds
ds_read2st64_b64               vdst:b64x2, vaddr                              offset8 offset8 gds
ds_read_b128                   vdst,       vaddr                              offset16 gds
ds_read_b32                    vdst,       vaddr                              offset16 gds
ds_read_b64                    vdst,       vaddr                              offset16 gds
ds_read_b96                    vdst,       vaddr                              offset16 gds
ds_read_i16                    vdst,       vaddr                              offset16 gds
ds_read_i8                     vdst,       vaddr                              offset16 gds
ds_read_i8_d16                 vdst,       vaddr                              offset16 gds
ds_read_i8_d16_hi              vdst,       vaddr                              offset16 gds
ds_read_u16                    vdst,       vaddr                              offset16 gds
ds_read_u16_d16                vdst,       vaddr                              offset16 gds
ds_read_u16_d16_hi             vdst,       vaddr                              offset16 gds
ds_read_u8                     vdst,       vaddr                              offset16 gds
ds_read_u8_d16                 vdst,       vaddr                              offset16 gds
ds_read_u8_d16_hi              vdst,       vaddr                              offset16 gds
ds_rsub_rtn_u32                vdst,       vaddr,    vdata                    offset16 gds
ds_rsub_rtn_u64                vdst,       vaddr,    vdata                    offset16 gds
ds_rsub_src2_u32                           vaddr                              offset16 gds
ds_rsub_src2_u64                           vaddr                              offset16 gds
ds_rsub_u32                                vaddr,    vdata                    offset16 gds
ds_rsub_u64                                vaddr,    vdata                    offset16 gds
ds_sub_rtn_u32                 vdst,       vaddr,    vdata                    offset16 gds
ds_sub_rtn_u64                 vdst,       vaddr,    vdata                    offset16 gds
ds_sub_src2_u32                            vaddr                              offset16 gds
ds_sub_src2_u64                            vaddr                              offset16 gds
ds_sub_u32                                 vaddr,    vdata                    offset16 gds
ds_sub_u64                                 vaddr,    vdata                    offset16 gds
ds_swizzle_b32                 vdst,       vaddr                              pattern gds
ds_wrap_rtn_b32                vdst,       vaddr,    vdata0,   vdata1         offset16 gds
ds_write2_b32                              vaddr,    vdata0,   vdata1         offset8 offset8 gds
ds_write2_b64                              vaddr,    vdata0,   vdata1         offset8 offset8 gds
ds_write2st64_b32                          vaddr,    vdata0,   vdata1         offset8 offset8 gds
ds_write2st64_b64                          vaddr,    vdata0,   vdata1         offset8 offset8 gds
ds_write_b128                              vaddr,    vdata                    offset16 gds
ds_write_b16                               vaddr,    vdata                    offset16 gds
ds_write_b16_d16_hi                        vaddr,    vdata                    offset16 gds
ds_write_b32                               vaddr,    vdata                    offset16 gds
ds_write_b64                               vaddr,    vdata                    offset16 gds
ds_write_b8                                vaddr,    vdata                    offset16 gds
ds_write_b8_d16_hi                         vaddr,    vdata                    offset16 gds
ds_write_b96                               vaddr,    vdata                    offset16 gds
ds_write_src2_b32                          vaddr                              offset16 gds
ds_write_src2_b64                          vaddr                              offset16 gds
ds_wrxchg2_rtn_b32             vdst:b32x2, vaddr,    vdata0,   vdata1         offset8 offset8 gds
ds_wrxchg2_rtn_b64             vdst:b64x2, vaddr,    vdata0,   vdata1         offset8 offset8 gds
ds_wrxchg2st64_rtn_b32         vdst:b32x2, vaddr,    vdata0,   vdata1         offset8 offset8 gds
ds_wrxchg2st64_rtn_b64         vdst:b64x2, vaddr,    vdata0,   vdata1         offset8 offset8 gds
ds_wrxchg_rtn_b32              vdst,       vaddr,    vdata                    offset16 gds
ds_wrxchg_rtn_b64              vdst,       vaddr,    vdata                    offset16 gds
ds_xor_b32                                 vaddr,    vdata                    offset16 gds
ds_xor_b64                                 vaddr,    vdata                    offset16 gds
ds_xor_rtn_b32                 vdst,       vaddr,    vdata                    offset16 gds
ds_xor_rtn_b64                 vdst,       vaddr,    vdata                    offset16 gds
ds_xor_src2_b32                            vaddr                              offset16 gds
ds_xor_src2_b64                            vaddr                              offset16 gds

EXP

INSTRUCTION                    DST       SRC0      SRC1      SRC2      SRC3           MODIFIERS
————————————————————————————————————————————————————————————————————————————————————————————————————
exp                            tgt,      vsrc0,    vsrc1,    vsrc2,    vsrc3          done compr vm

FLAT

INSTRUCTION                    DST           SRC0      SRC1         SRC2           MODIFIERS
—————————————————————————————————————————————————————————————————————————————————————————————————————————
flat_atomic_add                vdst:opt,     vaddr,    vdata                       offset11 glc slc
flat_atomic_add_x2             vdst:opt,     vaddr,    vdata                       offset11 glc slc
flat_atomic_and                vdst:opt,     vaddr,    vdata                       offset11 glc slc
flat_atomic_and_x2             vdst:opt,     vaddr,    vdata                       offset11 glc slc
flat_atomic_cmpswap            vdst:opt,     vaddr,    vdata:b32x2                 offset11 glc slc
flat_atomic_cmpswap_x2         vdst:opt,     vaddr,    vdata:b64x2                 offset11 glc slc
flat_atomic_dec                vdst:opt:u32, vaddr,    vdata:u32                   offset11 glc slc
flat_atomic_dec_x2             vdst:opt:u64, vaddr,    vdata:u64                   offset11 glc slc
flat_atomic_fcmpswap           vdst:opt:f32, vaddr,    vdata:f32x2                 offset11 glc slc
flat_atomic_fcmpswap_x2        vdst:opt:f64, vaddr,    vdata:f64x2                 offset11 glc slc
flat_atomic_fmax               vdst:opt:f32, vaddr,    vdata:f32                   offset11 glc slc
flat_atomic_fmax_x2            vdst:opt:f64, vaddr,    vdata:f64                   offset11 glc slc
flat_atomic_fmin               vdst:opt:f32, vaddr,    vdata:f32                   offset11 glc slc
flat_atomic_fmin_x2            vdst:opt:f64, vaddr,    vdata:f64                   offset11 glc slc
flat_atomic_inc                vdst:opt:u32, vaddr,    vdata:u32                   offset11 glc slc
flat_atomic_inc_x2             vdst:opt:u64, vaddr,    vdata:u64                   offset11 glc slc
flat_atomic_or                 vdst:opt,     vaddr,    vdata                       offset11 glc slc
flat_atomic_or_x2              vdst:opt,     vaddr,    vdata                       offset11 glc slc
flat_atomic_smax               vdst:opt:s32, vaddr,    vdata:s32                   offset11 glc slc
flat_atomic_smax_x2            vdst:opt:s64, vaddr,    vdata:s64                   offset11 glc slc
flat_atomic_smin               vdst:opt:s32, vaddr,    vdata:s32                   offset11 glc slc
flat_atomic_smin_x2            vdst:opt:s64, vaddr,    vdata:s64                   offset11 glc slc
flat_atomic_sub                vdst:opt,     vaddr,    vdata                       offset11 glc slc
flat_atomic_sub_x2             vdst:opt,     vaddr,    vdata                       offset11 glc slc
flat_atomic_swap               vdst:opt,     vaddr,    vdata                       offset11 glc slc
flat_atomic_swap_x2            vdst:opt,     vaddr,    vdata                       offset11 glc slc
flat_atomic_umax               vdst:opt:u32, vaddr,    vdata:u32                   offset11 glc slc
flat_atomic_umax_x2            vdst:opt:u64, vaddr,    vdata:u64                   offset11 glc slc
flat_atomic_umin               vdst:opt:u32, vaddr,    vdata:u32                   offset11 glc slc
flat_atomic_umin_x2            vdst:opt:u64, vaddr,    vdata:u64                   offset11 glc slc
flat_atomic_xor                vdst:opt,     vaddr,    vdata                       offset11 glc slc
flat_atomic_xor_x2             vdst:opt,     vaddr,    vdata                       offset11 glc slc
flat_load_dword                vdst,         vaddr                                 offset11 glc slc dlc
flat_load_dwordx2              vdst,         vaddr                                 offset11 glc slc dlc
flat_load_dwordx3              vdst,         vaddr                                 offset11 glc slc dlc
flat_load_dwordx4              vdst,         vaddr                                 offset11 glc slc dlc
flat_load_sbyte                vdst,         vaddr                                 offset11 glc slc dlc
flat_load_sbyte_d16            vdst,         vaddr                                 offset11 glc slc dlc
flat_load_sbyte_d16_hi         vdst,         vaddr                                 offset11 glc slc dlc
flat_load_short_d16            vdst,         vaddr                                 offset11 glc slc dlc
flat_load_short_d16_hi         vdst,         vaddr                                 offset11 glc slc dlc
flat_load_sshort               vdst,         vaddr                                 offset11 glc slc dlc
flat_load_ubyte                vdst,         vaddr                                 offset11 glc slc dlc
flat_load_ubyte_d16            vdst,         vaddr                                 offset11 glc slc dlc
flat_load_ubyte_d16_hi         vdst,         vaddr                                 offset11 glc slc dlc
flat_load_ushort               vdst,         vaddr                                 offset11 glc slc dlc
flat_store_byte                              vaddr,    vdata                       offset11 glc slc dlc
flat_store_byte_d16_hi                       vaddr,    vdata                       offset11 glc slc dlc
flat_store_dword                             vaddr,    vdata                       offset11 glc slc dlc
flat_store_dwordx2                           vaddr,    vdata                       offset11 glc slc dlc
flat_store_dwordx3                           vaddr,    vdata                       offset11 glc slc dlc
flat_store_dwordx4                           vaddr,    vdata                       offset11 glc slc dlc
flat_store_short                             vaddr,    vdata                       offset11 glc slc dlc
flat_store_short_d16_hi                      vaddr,    vdata                       offset11 glc slc dlc
global_atomic_add              vdst:opt,     vaddr,    vdata,       saddr          offset12s glc
global_atomic_add_x2           vdst:opt,     vaddr,    vdata,       saddr          offset12s glc
global_atomic_and              vdst:opt,     vaddr,    vdata,       saddr          offset12s glc
global_atomic_and_x2           vdst:opt,     vaddr,    vdata,       saddr          offset12s glc
global_atomic_cmpswap          vdst:opt,     vaddr,    vdata:b32x2, saddr          offset12s glc
global_atomic_cmpswap_x2       vdst:opt,     vaddr,    vdata:b64x2, saddr          offset12s glc
global_atomic_dec              vdst:opt:u32, vaddr,    vdata:u32,   saddr          offset12s glc
global_atomic_dec_x2           vdst:opt:u64, vaddr,    vdata:u64,   saddr          offset12s glc
global_atomic_fmax             vdst:opt:f32, vaddr,    vdata:f32,   saddr          offset12s glc
global_atomic_fmax_x2          vdst:opt:f64, vaddr,    vdata:f64,   saddr          offset12s glc
global_atomic_fmin             vdst:opt:f32, vaddr,    vdata:f32,   saddr          offset12s glc
global_atomic_fmin_x2          vdst:opt:f64, vaddr,    vdata:f64,   saddr          offset12s glc
global_atomic_inc              vdst:opt:u32, vaddr,    vdata:u32,   saddr          offset12s glc
global_atomic_inc_x2           vdst:opt:u64, vaddr,    vdata:u64,   saddr          offset12s glc
global_atomic_or               vdst:opt,     vaddr,    vdata,       saddr          offset12s glc
global_atomic_or_x2            vdst:opt,     vaddr,    vdata,       saddr          offset12s glc
global_atomic_smax             vdst:opt:s32, vaddr,    vdata:s32,   saddr          offset12s glc
global_atomic_smax_x2          vdst:opt:s64, vaddr,    vdata:s64,   saddr          offset12s glc
global_atomic_smin             vdst:opt:s32, vaddr,    vdata:s32,   saddr          offset12s glc
global_atomic_smin_x2          vdst:opt:s64, vaddr,    vdata:s64,   saddr          offset12s glc
global_atomic_sub              vdst:opt,     vaddr,    vdata,       saddr          offset12s glc
global_atomic_sub_x2           vdst:opt,     vaddr,    vdata,       saddr          offset12s glc
global_atomic_swap             vdst:opt,     vaddr,    vdata,       saddr          offset12s glc
global_atomic_swap_x2          vdst:opt,     vaddr,    vdata,       saddr          offset12s glc
global_atomic_umax             vdst:opt:u32, vaddr,    vdata:u32,   saddr          offset12s glc
global_atomic_umax_x2          vdst:opt:u64, vaddr,    vdata:u64,   saddr          offset12s glc
global_atomic_umin             vdst:opt:u32, vaddr,    vdata:u32,   saddr          offset12s glc
global_atomic_umin_x2          vdst:opt:u64, vaddr,    vdata:u64,   saddr          offset12s glc
global_atomic_xor              vdst:opt,     vaddr,    vdata,       saddr          offset12s glc
global_atomic_xor_x2           vdst:opt,     vaddr,    vdata,       saddr          offset12s glc
global_load_dword              vdst,         vaddr,    saddr                       offset12s glc
global_load_dwordx2            vdst,         vaddr,    saddr                       offset12s glc
global_load_dwordx3            vdst,         vaddr,    saddr                       offset12s glc
global_load_dwordx4            vdst,         vaddr,    saddr                       offset12s glc
global_load_sbyte              vdst,         vaddr,    saddr                       offset12s glc
global_load_sbyte_d16          vdst,         vaddr,    saddr                       offset12s glc
global_load_sbyte_d16_hi       vdst,         vaddr,    saddr                       offset12s glc
global_load_short_d16          vdst,         vaddr,    saddr                       offset12s glc
global_load_short_d16_hi       vdst,         vaddr,    saddr                       offset12s glc
global_load_sshort             vdst,         vaddr,    saddr                       offset12s glc
global_load_ubyte              vdst,         vaddr,    saddr                       offset12s glc
global_load_ubyte_d16          vdst,         vaddr,    saddr                       offset12s glc
global_load_ubyte_d16_hi       vdst,         vaddr,    saddr                       offset12s glc
global_load_ushort             vdst,         vaddr,    saddr                       offset12s glc
global_store_byte                            vaddr,    vdata,       saddr          offset12s glc
global_store_byte_d16_hi                     vaddr,    vdata,       saddr          offset12s glc
global_store_dword                           vaddr,    vdata,       saddr          offset12s glc
global_store_dwordx2                         vaddr,    vdata,       saddr          offset12s glc
global_store_dwordx3                         vaddr,    vdata,       saddr          offset12s glc
global_store_dwordx4                         vaddr,    vdata,       saddr          offset12s glc
global_store_short                           vaddr,    vdata,       saddr          offset12s glc
global_store_short_d16_hi                    vaddr,    vdata,       saddr          offset12s glc
scratch_load_dword             vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_dwordx2           vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_dwordx3           vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_dwordx4           vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_sbyte             vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_sbyte_d16         vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_sbyte_d16_hi      vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_short_d16         vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_short_d16_hi      vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_sshort            vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_ubyte             vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_ubyte_d16         vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_ubyte_d16_hi      vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_load_ushort            vdst,         vaddr,    saddr                       offset12s glc slc dlc
scratch_store_byte                           vaddr,    vdata,       saddr          offset12s glc slc dlc
scratch_store_byte_d16_hi                    vaddr,    vdata,       saddr          offset12s glc slc dlc
scratch_store_dword                          vaddr,    vdata,       saddr          offset12s glc slc dlc
scratch_store_dwordx2                        vaddr,    vdata,       saddr          offset12s glc slc dlc
scratch_store_dwordx3                        vaddr,    vdata,       saddr          offset12s glc slc dlc
scratch_store_dwordx4                        vaddr,    vdata,       saddr          offset12s glc slc dlc
scratch_store_short                          vaddr,    vdata,       saddr          offset12s glc slc dlc
scratch_store_short_d16_hi                   vaddr,    vdata,       saddr          offset12s glc slc dlc

MIMG

INSTRUCTION            DST      SRC0       SRC1     SRC2       MODIFIERS
———————————————————————————————————————————————————————————————————————————————————————————————————
image_atomic_add                vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_atomic_and                vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_atomic_cmpswap            vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_atomic_dec                vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_atomic_inc                vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_atomic_or                 vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_atomic_smax               vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_atomic_smin               vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_atomic_sub                vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_atomic_swap               vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_atomic_umax               vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_atomic_umin               vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_atomic_xor                vdata:dst, vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_gather4          vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_b        vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_b_cl     vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_b_cl_o   vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_b_o      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_c        vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_c_b      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_c_b_cl   vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_c_b_cl_o vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_c_b_o    vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_c_cl     vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_c_cl_o   vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_c_l      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_c_l_o    vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_c_lz     vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_c_lz_o   vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_c_o      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_cl       vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_cl_o     vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_l        vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_l_o      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_lz       vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_lz_o     vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_gather4_o        vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_get_lod          vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe
image_get_resinfo      vdst,    vaddr,     srsrc               dmask dim unorm dlc glc slc lwe
image_load             vdst,    vaddr,     srsrc               dmask dim unorm dlc glc slc lwe d16
image_load_mip         vdst,    vaddr,     srsrc               dmask dim unorm dlc glc slc lwe d16
image_load_mip_pck     vdst,    vaddr,     srsrc               dmask dim unorm dlc glc slc lwe
image_load_mip_pck_sgn vdst,    vaddr,     srsrc               dmask dim unorm dlc glc slc lwe
image_load_pck         vdst,    vaddr,     srsrc               dmask dim unorm dlc glc slc lwe
image_load_pck_sgn     vdst,    vaddr,     srsrc               dmask dim unorm dlc glc slc lwe
image_sample           vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_b         vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_b_cl      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_b_cl_o    vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_b_o       vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c         vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_b       vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_b_cl    vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_b_cl_o  vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_b_o     vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_cd      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_cd_cl   vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_cd_cl_o vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_cd_o    vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_cl      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_cl_o    vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_d       vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_d_cl    vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_d_cl_o  vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_d_o     vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_l       vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_l_o     vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_lz      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_lz_o    vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_c_o       vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_cd        vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_cd_cl     vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_cd_cl_o   vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_cd_o      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_cl        vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_cl_o      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_d         vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_d_cl      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_d_cl_o    vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_d_o       vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_l         vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_l_o       vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_lz        vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_lz_o      vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_sample_o         vdst,    vaddr,     srsrc,   ssamp      dmask dim unorm dlc glc slc lwe d16
image_store                     vdata,     vaddr,   srsrc      dmask dim unorm dlc glc slc lwe d16
image_store_mip                 vdata,     vaddr,   srsrc      dmask dim unorm dlc glc slc lwe d16
image_store_mip_pck             vdata,     vaddr,   srsrc      dmask dim unorm dlc glc slc lwe
image_store_pck                 vdata,     vaddr,   srsrc      dmask dim unorm dlc glc slc lwe

MUBUF

INSTRUCTION                  DST   SRC0             SRC1   SRC2    SRC3    MODIFIERS
————————————————————————————————————————————————————————————————————————————————————————————————————————————————
buffer_atomic_add                  vdata:dst,       vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_add_x2               vdata:dst,       vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_and                  vdata:dst,       vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_and_x2               vdata:dst,       vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_cmpswap              vdata:dst:b32x2, vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_cmpswap_x2           vdata:dst:b64x2, vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_dec                  vdata:dst:u32,   vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_dec_x2               vdata:dst:u64,   vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_inc                  vdata:dst:u32,   vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_inc_x2               vdata:dst:u64,   vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_or                   vdata:dst,       vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_or_x2                vdata:dst,       vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_smax                 vdata:dst:s32,   vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_smax_x2              vdata:dst:s64,   vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_smin                 vdata:dst:s32,   vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_smin_x2              vdata:dst:s64,   vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_sub                  vdata:dst,       vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_sub_x2               vdata:dst,       vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_swap                 vdata:dst,       vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_swap_x2              vdata:dst,       vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_umax                 vdata:dst:u32,   vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_umax_x2              vdata:dst:u64,   vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_umin                 vdata:dst:u32,   vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_umin_x2              vdata:dst:u64,   vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_xor                  vdata:dst,       vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_atomic_xor_x2               vdata:dst,       vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_gl0_inv
buffer_gl1_inv
buffer_load_dword            vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc lds dlc
buffer_load_dwordx2          vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_dwordx3          vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_dwordx4          vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_format_d16_x     vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_format_d16_xy    vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_format_d16_xyz   vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_format_d16_xyzw  vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_format_x         vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc lds dlc
buffer_load_format_xy        vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_format_xyz       vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_format_xyzw      vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_sbyte            vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc lds dlc
buffer_load_sbyte_d16        vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_sbyte_d16_hi     vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_short_d16        vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_short_d16_hi     vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_sshort           vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc lds dlc
buffer_load_ubyte            vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc lds dlc
buffer_load_ubyte_d16        vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_ubyte_d16_hi     vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc dlc
buffer_load_ushort           vdst, vaddr,           srsrc, soffset         idxen offen offset12 glc slc lds dlc
buffer_store_byte                  vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_byte_d16_hi           vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_dword                 vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_dwordx2               vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_dwordx3               vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_dwordx4               vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_format_d16_x          vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_format_d16_xy         vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_format_d16_xyz        vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_format_d16_xyzw       vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_format_x              vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_format_xy             vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_format_xyz            vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_format_xyzw           vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_short                 vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc
buffer_store_short_d16_hi          vdata,           vaddr, srsrc,  soffset idxen offen offset12 glc slc

SDWA

INSTRUCTION              DST0  DST1 SRC0        SRC1       SRC2 MODIFIERS
————————————————————————————————————————————————————————————————————————————————————————————————————————————————
v_add_co_ci_u32_sdwa     vdst, vcc, src0:m,     src1:m,    vcc  clamp dst_sel dst_unused src0_sel src1_sel
v_add_f16_sdwa           vdst,      src0:m,     src1:m          clamp dst_sel dst_unused src0_sel src1_sel
v_add_f32_sdwa           vdst,      src0:m,     src1:m          clamp omod dst_sel dst_unused src0_sel src1_sel
v_add_nc_u32_sdwa        vdst,      src0:m,     src1:m          clamp dst_sel dst_unused src0_sel src1_sel
v_and_b32_sdwa           vdst,      src0:m,     src1:m          dst_sel dst_unused src0_sel src1_sel
v_ashrrev_i32_sdwa       vdst,      src0:m:u32, src1:m          dst_sel dst_unused src0_sel src1_sel
v_bfrev_b32_sdwa         vdst,      src:m                       dst_sel dst_unused src0_sel
v_ceil_f16_sdwa          vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_ceil_f32_sdwa          vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_cmp_class_f16_sdwa     sdst,      src0:m,     src1:m:b32      src0_sel src1_sel
v_cmp_class_f32_sdwa     sdst,      src0:m,     src1:m:b32      src0_sel src1_sel
v_cmp_eq_f16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_eq_f32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_eq_i16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_eq_i32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_eq_u16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_eq_u32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_f_f16_sdwa         sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_f_f32_sdwa         sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_f_i32_sdwa         sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_f_u32_sdwa         sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_ge_f16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_ge_f32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_ge_i16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_ge_i32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_ge_u16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_ge_u32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_gt_f16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_gt_f32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_gt_i16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_gt_i32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_gt_u16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_gt_u32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_le_f16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_le_f32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_le_i16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_le_i32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_le_u16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_le_u32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_lg_f16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_lg_f32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_lt_f16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_lt_f32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_lt_i16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_lt_i32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_lt_u16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_lt_u32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_ne_i16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_ne_i32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_ne_u16_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_ne_u32_sdwa        sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_neq_f16_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_neq_f32_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_nge_f16_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_nge_f32_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_ngt_f16_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_ngt_f32_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_nle_f16_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_nle_f32_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_nlg_f16_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_nlg_f32_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_nlt_f16_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_nlt_f32_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_o_f16_sdwa         sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_o_f32_sdwa         sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_t_i32_sdwa         sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_t_u32_sdwa         sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_tru_f16_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_tru_f32_sdwa       sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_u_f16_sdwa         sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmp_u_f32_sdwa         sdst,      src0:m,     src1:m          src0_sel src1_sel
v_cmpx_class_f16_sdwa               src0:m,     src1:m:b32      src0_sel src1_sel
v_cmpx_class_f32_sdwa               src0:m,     src1:m:b32      src0_sel src1_sel
v_cmpx_eq_f16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_eq_f32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_eq_i16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_eq_i32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_eq_u16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_eq_u32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_f_f16_sdwa                   src0:m,     src1:m          src0_sel src1_sel
v_cmpx_f_f32_sdwa                   src0:m,     src1:m          src0_sel src1_sel
v_cmpx_f_i32_sdwa                   src0:m,     src1:m          src0_sel src1_sel
v_cmpx_f_u32_sdwa                   src0:m,     src1:m          src0_sel src1_sel
v_cmpx_ge_f16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_ge_f32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_ge_i16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_ge_i32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_ge_u16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_ge_u32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_gt_f16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_gt_f32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_gt_i16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_gt_i32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_gt_u16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_gt_u32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_le_f16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_le_f32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_le_i16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_le_i32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_le_u16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_le_u32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_lg_f16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_lg_f32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_lt_f16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_lt_f32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_lt_i16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_lt_i32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_lt_u16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_lt_u32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_ne_i16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_ne_i32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_ne_u16_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_ne_u32_sdwa                  src0:m,     src1:m          src0_sel src1_sel
v_cmpx_neq_f16_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_neq_f32_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_nge_f16_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_nge_f32_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_ngt_f16_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_ngt_f32_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_nle_f16_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_nle_f32_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_nlg_f16_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_nlg_f32_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_nlt_f16_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_nlt_f32_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_o_f16_sdwa                   src0:m,     src1:m          src0_sel src1_sel
v_cmpx_o_f32_sdwa                   src0:m,     src1:m          src0_sel src1_sel
v_cmpx_t_i32_sdwa                   src0:m,     src1:m          src0_sel src1_sel
v_cmpx_t_u32_sdwa                   src0:m,     src1:m          src0_sel src1_sel
v_cmpx_tru_f16_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_tru_f32_sdwa                 src0:m,     src1:m          src0_sel src1_sel
v_cmpx_u_f16_sdwa                   src0:m,     src1:m          src0_sel src1_sel
v_cmpx_u_f32_sdwa                   src0:m,     src1:m          src0_sel src1_sel
v_cos_f16_sdwa           vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_cos_f32_sdwa           vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_cvt_f16_f32_sdwa       vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_cvt_f16_i16_sdwa       vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_cvt_f16_u16_sdwa       vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_cvt_f32_f16_sdwa       vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_cvt_f32_i32_sdwa       vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_cvt_f32_u32_sdwa       vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_cvt_f32_ubyte0_sdwa    vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_cvt_f32_ubyte1_sdwa    vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_cvt_f32_ubyte2_sdwa    vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_cvt_f32_ubyte3_sdwa    vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_cvt_flr_i32_f32_sdwa   vdst,      src:m                       dst_sel dst_unused src0_sel
v_cvt_i16_f16_sdwa       vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_cvt_i32_f32_sdwa       vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_cvt_norm_i16_f16_sdwa  vdst,      src:m                       dst_sel dst_unused src0_sel
v_cvt_norm_u16_f16_sdwa  vdst,      src:m                       dst_sel dst_unused src0_sel
v_cvt_off_f32_i4_sdwa    vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_cvt_rpi_i32_f32_sdwa   vdst,      src:m                       dst_sel dst_unused src0_sel
v_cvt_u16_f16_sdwa       vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_cvt_u32_f32_sdwa       vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_exp_f16_sdwa           vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_exp_f32_sdwa           vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_ffbh_i32_sdwa          vdst,      src:m                       dst_sel dst_unused src0_sel
v_ffbh_u32_sdwa          vdst,      src:m                       dst_sel dst_unused src0_sel
v_ffbl_b32_sdwa          vdst,      src:m                       dst_sel dst_unused src0_sel
v_floor_f16_sdwa         vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_floor_f32_sdwa         vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_fract_f16_sdwa         vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_fract_f32_sdwa         vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_frexp_exp_i16_f16_sdwa vdst,      src:m                       dst_sel dst_unused src0_sel
v_frexp_exp_i32_f32_sdwa vdst,      src:m                       dst_sel dst_unused src0_sel
v_frexp_mant_f16_sdwa    vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_frexp_mant_f32_sdwa    vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_ldexp_f16_sdwa         vdst,      src0:m,     src1:m:i16      clamp dst_sel dst_unused src0_sel src1_sel
v_log_f16_sdwa           vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_log_f32_sdwa           vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_lshlrev_b32_sdwa       vdst,      src0:m:u32, src1:m          dst_sel dst_unused src0_sel src1_sel
v_lshrrev_b32_sdwa       vdst,      src0:m:u32, src1:m          dst_sel dst_unused src0_sel src1_sel
v_max_f16_sdwa           vdst,      src0:m,     src1:m          clamp dst_sel dst_unused src0_sel src1_sel
v_max_f32_sdwa           vdst,      src0:m,     src1:m          clamp omod dst_sel dst_unused src0_sel src1_sel
v_max_i32_sdwa           vdst,      src0:m,     src1:m          dst_sel dst_unused src0_sel src1_sel
v_max_u32_sdwa           vdst,      src0:m,     src1:m          dst_sel dst_unused src0_sel src1_sel
v_min_f16_sdwa           vdst,      src0:m,     src1:m          clamp dst_sel dst_unused src0_sel src1_sel
v_min_f32_sdwa           vdst,      src0:m,     src1:m          clamp omod dst_sel dst_unused src0_sel src1_sel
v_min_i32_sdwa           vdst,      src0:m,     src1:m          dst_sel dst_unused src0_sel src1_sel
v_min_u32_sdwa           vdst,      src0:m,     src1:m          dst_sel dst_unused src0_sel src1_sel
v_mov_b32_sdwa           vdst,      src:m                       dst_sel dst_unused src0_sel
v_mul_f16_sdwa           vdst,      src0:m,     src1:m          clamp dst_sel dst_unused src0_sel src1_sel
v_mul_f32_sdwa           vdst,      src0:m,     src1:m          clamp omod dst_sel dst_unused src0_sel src1_sel
v_mul_hi_i32_i24_sdwa    vdst,      src0:m,     src1:m          dst_sel dst_unused src0_sel src1_sel
v_mul_hi_u32_u24_sdwa    vdst,      src0:m,     src1:m          dst_sel dst_unused src0_sel src1_sel
v_mul_i32_i24_sdwa       vdst,      src0:m,     src1:m          clamp dst_sel dst_unused src0_sel src1_sel
v_mul_legacy_f32_sdwa    vdst,      src0:m,     src1:m          clamp omod dst_sel dst_unused src0_sel src1_sel
v_mul_u32_u24_sdwa       vdst,      src0:m,     src1:m          clamp dst_sel dst_unused src0_sel src1_sel
v_not_b32_sdwa           vdst,      src:m                       dst_sel dst_unused src0_sel
v_or_b32_sdwa            vdst,      src0:m,     src1:m          dst_sel dst_unused src0_sel src1_sel
v_rcp_f16_sdwa           vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_rcp_f32_sdwa           vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_rcp_iflag_f32_sdwa     vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_rndne_f16_sdwa         vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_rndne_f32_sdwa         vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_rsq_f16_sdwa           vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_rsq_f32_sdwa           vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_sat_pk_u8_i16_sdwa     vdst,      src:m                       dst_sel dst_unused src0_sel
v_sin_f16_sdwa           vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_sin_f32_sdwa           vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_sqrt_f16_sdwa          vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_sqrt_f32_sdwa          vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_sub_co_ci_u32_sdwa     vdst, vcc, src0:m,     src1:m,    vcc  clamp dst_sel dst_unused src0_sel src1_sel
v_sub_f16_sdwa           vdst,      src0:m,     src1:m          clamp dst_sel dst_unused src0_sel src1_sel
v_sub_f32_sdwa           vdst,      src0:m,     src1:m          clamp omod dst_sel dst_unused src0_sel src1_sel
v_sub_nc_u32_sdwa        vdst,      src0:m,     src1:m          clamp dst_sel dst_unused src0_sel src1_sel
v_subrev_co_ci_u32_sdwa  vdst, vcc, src0:m,     src1:m,    vcc  clamp dst_sel dst_unused src0_sel src1_sel
v_subrev_f16_sdwa        vdst,      src0:m,     src1:m          clamp dst_sel dst_unused src0_sel src1_sel
v_subrev_f32_sdwa        vdst,      src0:m,     src1:m          clamp omod dst_sel dst_unused src0_sel src1_sel
v_subrev_nc_u32_sdwa     vdst,      src0:m,     src1:m          clamp dst_sel dst_unused src0_sel src1_sel
v_trunc_f16_sdwa         vdst,      src:m                       clamp dst_sel dst_unused src0_sel
v_trunc_f32_sdwa         vdst,      src:m                       clamp omod dst_sel dst_unused src0_sel
v_xnor_b32_sdwa          vdst,      src0:m,     src1:m          dst_sel dst_unused src0_sel src1_sel
v_xor_b32_sdwa           vdst,      src0:m,     src1:m          dst_sel dst_unused src0_sel src1_sel

SMEM

INSTRUCTION                    DST       SRC0             SRC1      SRC2           MODIFIERS
—————————————————————————————————————————————————————————————————————————————————————————————
s_atc_probe                              imm3,            sbase,    soffset
s_atc_probe_buffer                       imm3,            sbase,    soffset
s_atomic_add                             sdata:dst,       sbase,    soffset        glc
s_atomic_add_x2                          sdata:dst,       sbase,    soffset        glc
s_atomic_and                             sdata:dst,       sbase,    soffset        glc
s_atomic_and_x2                          sdata:dst,       sbase,    soffset        glc
s_atomic_cmpswap                         sdata:dst:b32x2, sbase,    soffset        glc
s_atomic_cmpswap_x2                      sdata:dst:b64x2, sbase,    soffset        glc
s_atomic_dec                             sdata:dst:u32,   sbase,    soffset        glc
s_atomic_dec_x2                          sdata:dst:u64,   sbase,    soffset        glc
s_atomic_inc                             sdata:dst:u32,   sbase,    soffset        glc
s_atomic_inc_x2                          sdata:dst:u64,   sbase,    soffset        glc
s_atomic_or                              sdata:dst,       sbase,    soffset        glc
s_atomic_or_x2                           sdata:dst,       sbase,    soffset        glc
s_atomic_smax                            sdata:dst:s32,   sbase,    soffset        glc
s_atomic_smax_x2                         sdata:dst:s64,   sbase,    soffset        glc
s_atomic_smin                            sdata:dst:s32,   sbase,    soffset        glc
s_atomic_smin_x2                         sdata:dst:s64,   sbase,    soffset        glc
s_atomic_sub                             sdata:dst,       sbase,    soffset        glc
s_atomic_sub_x2                          sdata:dst,       sbase,    soffset        glc
s_atomic_swap                            sdata:dst,       sbase,    soffset        glc
s_atomic_swap_x2                         sdata:dst,       sbase,    soffset        glc
s_atomic_umax                            sdata:dst:u32,   sbase,    soffset        glc
s_atomic_umax_x2                         sdata:dst:u64,   sbase,    soffset        glc
s_atomic_umin                            sdata:dst:u32,   sbase,    soffset        glc
s_atomic_umin_x2                         sdata:dst:u64,   sbase,    soffset        glc
s_atomic_xor                             sdata:dst,       sbase,    soffset        glc
s_atomic_xor_x2                          sdata:dst,       sbase,    soffset        glc
s_buffer_atomic_add                      sdata:dst,       sbase,    soffset        glc
s_buffer_atomic_add_x2                   sdata:dst,       sbase,    soffset        glc
s_buffer_atomic_and                      sdata:dst,       sbase,    soffset        glc
s_buffer_atomic_and_x2                   sdata:dst,       sbase,    soffset        glc
s_buffer_atomic_cmpswap                  sdata:dst:b32x2, sbase,    soffset        glc
s_buffer_atomic_cmpswap_x2               sdata:dst:b64x2, sbase,    soffset        glc
s_buffer_atomic_dec                      sdata:dst:u32,   sbase,    soffset        glc
s_buffer_atomic_dec_x2                   sdata:dst:u64,   sbase,    soffset        glc
s_buffer_atomic_inc                      sdata:dst:u32,   sbase,    soffset        glc
s_buffer_atomic_inc_x2                   sdata:dst:u64,   sbase,    soffset        glc
s_buffer_atomic_or                       sdata:dst,       sbase,    soffset        glc
s_buffer_atomic_or_x2                    sdata:dst,       sbase,    soffset        glc
s_buffer_atomic_smax                     sdata:dst:s32,   sbase,    soffset        glc
s_buffer_atomic_smax_x2                  sdata:dst:s64,   sbase,    soffset        glc
s_buffer_atomic_smin                     sdata:dst:s32,   sbase,    soffset        glc
s_buffer_atomic_smin_x2                  sdata:dst:s64,   sbase,    soffset        glc
s_buffer_atomic_sub                      sdata:dst,       sbase,    soffset        glc
s_buffer_atomic_sub_x2                   sdata:dst,       sbase,    soffset        glc
s_buffer_atomic_swap                     sdata:dst,       sbase,    soffset        glc
s_buffer_atomic_swap_x2                  sdata:dst,       sbase,    soffset        glc
s_buffer_atomic_umax                     sdata:dst:u32,   sbase,    soffset        glc
s_buffer_atomic_umax_x2                  sdata:dst:u64,   sbase,    soffset        glc
s_buffer_atomic_umin                     sdata:dst:u32,   sbase,    soffset        glc
s_buffer_atomic_umin_x2                  sdata:dst:u64,   sbase,    soffset        glc
s_buffer_atomic_xor                      sdata:dst,       sbase,    soffset        glc
s_buffer_atomic_xor_x2                   sdata:dst,       sbase,    soffset        glc
s_buffer_load_dword            sdst,     sbase,           soffset                  glc dlc
s_buffer_load_dwordx16         sdst,     sbase,           soffset                  glc dlc
s_buffer_load_dwordx2          sdst,     sbase,           soffset                  glc dlc
s_buffer_load_dwordx4          sdst,     sbase,           soffset                  glc dlc
s_buffer_load_dwordx8          sdst,     sbase,           soffset                  glc dlc
s_buffer_store_dword                     sdata,           sbase,    soffset        glc
s_buffer_store_dwordx2                   sdata,           sbase,    soffset        glc
s_buffer_store_dwordx4                   sdata,           sbase,    soffset        glc
s_dcache_discard                         sbase,           soffset
s_dcache_discard_x2                      sbase,           soffset
s_dcache_inv
s_dcache_wb
s_get_waveid_in_workgroup      sdst
s_gl1_inv
s_load_dword                   sdst,     sbase,           soffset                  glc dlc
s_load_dwordx16                sdst,     sbase,           soffset                  glc dlc
s_load_dwordx2                 sdst,     sbase,           soffset                  glc dlc
s_load_dwordx4                 sdst,     sbase,           soffset                  glc dlc
s_load_dwordx8                 sdst,     sbase,           soffset                  glc dlc
s_memrealtime                  sdst
s_memtime                      sdst
s_scratch_load_dword           sdst,     sbase,           soffset                  glc dlc
s_scratch_load_dwordx2         sdst,     sbase,           soffset                  glc dlc
s_scratch_load_dwordx4         sdst,     sbase,           soffset                  glc dlc
s_scratch_store_dword                    sdata,           sbase,    soffset        glc
s_scratch_store_dwordx2                  sdata,           sbase,    soffset        glc
s_scratch_store_dwordx4                  sdata,           sbase,    soffset        glc
s_store_dword                            sdata,           sbase,    soffset        glc
s_store_dwordx2                          sdata,           sbase,    soffset        glc
s_store_dwordx4                          sdata,           sbase,    soffset        glc

SOP1

INSTRUCTION                    DST       SRC
————————————————————————————————————————————————————————
s_abs_i32                      sdst,     ssrc
s_and_saveexec_b32             sdst,     ssrc
s_and_saveexec_b64             sdst,     ssrc
s_andn1_saveexec_b32           sdst,     ssrc
s_andn1_saveexec_b64           sdst,     ssrc
s_andn1_wrexec_b32             sdst,     ssrc
s_andn1_wrexec_b64             sdst,     ssrc
s_andn2_saveexec_b32           sdst,     ssrc
s_andn2_saveexec_b64           sdst,     ssrc
s_andn2_wrexec_b32             sdst,     ssrc
s_andn2_wrexec_b64             sdst,     ssrc
s_bcnt0_i32_b32                sdst,     ssrc
s_bcnt0_i32_b64                sdst,     ssrc
s_bcnt1_i32_b32                sdst,     ssrc
s_bcnt1_i32_b64                sdst,     ssrc
s_bitreplicate_b64_b32         sdst,     ssrc
s_bitset0_b32                  sdst,     ssrc
s_bitset0_b64                  sdst,     ssrc:b32
s_bitset1_b32                  sdst,     ssrc
s_bitset1_b64                  sdst,     ssrc:b32
s_brev_b32                     sdst,     ssrc
s_brev_b64                     sdst,     ssrc
s_cmov_b32                     sdst,     ssrc
s_cmov_b64                     sdst,     ssrc
s_ff0_i32_b32                  sdst,     ssrc
s_ff0_i32_b64                  sdst,     ssrc
s_ff1_i32_b32                  sdst,     ssrc
s_ff1_i32_b64                  sdst,     ssrc
s_flbit_i32                    sdst,     ssrc
s_flbit_i32_b32                sdst,     ssrc
s_flbit_i32_b64                sdst,     ssrc
s_flbit_i32_i64                sdst,     ssrc
s_getpc_b64                    sdst
s_mov_b32                      sdst,     ssrc
s_mov_b64                      sdst,     ssrc
s_movreld_b32                  sdst,     ssrc
s_movreld_b64                  sdst,     ssrc
s_movrels_b32                  sdst,     ssrc
s_movrels_b64                  sdst,     ssrc
s_movrelsd_2_b32               sdst,     ssrc
s_nand_saveexec_b32            sdst,     ssrc
s_nand_saveexec_b64            sdst,     ssrc
s_nor_saveexec_b32             sdst,     ssrc
s_nor_saveexec_b64             sdst,     ssrc
s_not_b32                      sdst,     ssrc
s_not_b64                      sdst,     ssrc
s_or_saveexec_b32              sdst,     ssrc
s_or_saveexec_b64              sdst,     ssrc
s_orn1_saveexec_b32            sdst,     ssrc
s_orn1_saveexec_b64            sdst,     ssrc
s_orn2_saveexec_b32            sdst,     ssrc
s_orn2_saveexec_b64            sdst,     ssrc
s_quadmask_b32                 sdst,     ssrc
s_quadmask_b64                 sdst,     ssrc
s_rfe_b64                                ssrc
s_setpc_b64                              ssrc
s_sext_i32_i16                 sdst,     ssrc
s_sext_i32_i8                  sdst,     ssrc
s_swappc_b64                   sdst,     ssrc
s_wqm_b32                      sdst,     ssrc
s_wqm_b64                      sdst,     ssrc
s_xnor_saveexec_b32            sdst,     ssrc
s_xnor_saveexec_b64            sdst,     ssrc
s_xor_saveexec_b32             sdst,     ssrc
s_xor_saveexec_b64             sdst,     ssrc

SOP2

INSTRUCTION                    DST       SRC0         SRC1
———————————————————————————————————————————————————————————————————————
s_absdiff_i32                  sdst,     ssrc0,       ssrc1
s_add_i32                      sdst,     ssrc0,       ssrc1
s_add_u32                      sdst,     ssrc0,       ssrc1
s_addc_u32                     sdst,     ssrc0,       ssrc1
s_and_b32                      sdst,     ssrc0,       ssrc1
s_and_b64                      sdst,     ssrc0,       ssrc1
s_andn2_b32                    sdst,     ssrc0,       ssrc1
s_andn2_b64                    sdst,     ssrc0,       ssrc1
s_ashr_i32                     sdst,     ssrc0,       ssrc1:u32
s_ashr_i64                     sdst,     ssrc0,       ssrc1:u32
s_bfe_i32                      sdst,     ssrc0,       ssrc1:u32
s_bfe_i64                      sdst,     ssrc0,       ssrc1:u32
s_bfe_u32                      sdst,     ssrc0,       ssrc1
s_bfe_u64                      sdst,     ssrc0,       ssrc1:u32
s_bfm_b32                      sdst,     ssrc0,       ssrc1
s_bfm_b64                      sdst,     ssrc0:b32,   ssrc1:b32
s_cselect_b32                  sdst,     ssrc0,       ssrc1
s_cselect_b64                  sdst,     ssrc0,       ssrc1
s_lshl1_add_u32                sdst,     ssrc0,       ssrc1
s_lshl2_add_u32                sdst,     ssrc0,       ssrc1
s_lshl3_add_u32                sdst,     ssrc0,       ssrc1
s_lshl4_add_u32                sdst,     ssrc0,       ssrc1
s_lshl_b32                     sdst,     ssrc0,       ssrc1:u32
s_lshl_b64                     sdst,     ssrc0,       ssrc1:u32
s_lshr_b32                     sdst,     ssrc0,       ssrc1:u32
s_lshr_b64                     sdst,     ssrc0,       ssrc1:u32
s_max_i32                      sdst,     ssrc0,       ssrc1
s_max_u32                      sdst,     ssrc0,       ssrc1
s_min_i32                      sdst,     ssrc0,       ssrc1
s_min_u32                      sdst,     ssrc0,       ssrc1
s_mul_hi_i32                   sdst,     ssrc0,       ssrc1
s_mul_hi_u32                   sdst,     ssrc0,       ssrc1
s_mul_i32                      sdst,     ssrc0,       ssrc1
s_nand_b32                     sdst,     ssrc0,       ssrc1
s_nand_b64                     sdst,     ssrc0,       ssrc1
s_nor_b32                      sdst,     ssrc0,       ssrc1
s_nor_b64                      sdst,     ssrc0,       ssrc1
s_or_b32                       sdst,     ssrc0,       ssrc1
s_or_b64                       sdst,     ssrc0,       ssrc1
s_orn2_b32                     sdst,     ssrc0,       ssrc1
s_orn2_b64                     sdst,     ssrc0,       ssrc1
s_pack_hh_b32_b16              sdst,     ssrc0:b16x2, ssrc1:b16x2
s_pack_lh_b32_b16              sdst,     ssrc0,       ssrc1:b16x2
s_pack_ll_b32_b16              sdst,     ssrc0,       ssrc1
s_sub_i32                      sdst,     ssrc0,       ssrc1
s_sub_u32                      sdst,     ssrc0,       ssrc1
s_subb_u32                     sdst,     ssrc0,       ssrc1
s_xnor_b32                     sdst,     ssrc0,       ssrc1
s_xnor_b64                     sdst,     ssrc0,       ssrc1
s_xor_b32                      sdst,     ssrc0,       ssrc1
s_xor_b64                      sdst,     ssrc0,       ssrc1

SOPC

INSTRUCTION                    SRC0      SRC1
————————————————————————————————————————————————————————
s_bitcmp0_b32                  ssrc0,    ssrc1
s_bitcmp0_b64                  ssrc0,    ssrc1:u32
s_bitcmp1_b32                  ssrc0,    ssrc1
s_bitcmp1_b64                  ssrc0,    ssrc1:u32
s_cmp_eq_i32                   ssrc0,    ssrc1
s_cmp_eq_u32                   ssrc0,    ssrc1
s_cmp_eq_u64                   ssrc0,    ssrc1
s_cmp_ge_i32                   ssrc0,    ssrc1
s_cmp_ge_u32                   ssrc0,    ssrc1
s_cmp_gt_i32                   ssrc0,    ssrc1
s_cmp_gt_u32                   ssrc0,    ssrc1
s_cmp_le_i32                   ssrc0,    ssrc1
s_cmp_le_u32                   ssrc0,    ssrc1
s_cmp_lg_i32                   ssrc0,    ssrc1
s_cmp_lg_u32                   ssrc0,    ssrc1
s_cmp_lg_u64                   ssrc0,    ssrc1
s_cmp_lt_i32                   ssrc0,    ssrc1
s_cmp_lt_u32                   ssrc0,    ssrc1

SOPK

INSTRUCTION                    DST       SRC0      SRC1
——————————————————————————————————————————————————————————————————
s_addk_i32                     sdst,     imm16
s_call_b64                     sdst,     label
s_cmovk_i32                    sdst,     imm16
s_cmpk_eq_i32                            ssrc,     imm16
s_cmpk_eq_u32                            ssrc,     imm16
s_cmpk_ge_i32                            ssrc,     imm16
s_cmpk_ge_u32                            ssrc,     imm16
s_cmpk_gt_i32                            ssrc,     imm16
s_cmpk_gt_u32                            ssrc,     imm16
s_cmpk_le_i32                            ssrc,     imm16
s_cmpk_le_u32                            ssrc,     imm16
s_cmpk_lg_i32                            ssrc,     imm16
s_cmpk_lg_u32                            ssrc,     imm16
s_cmpk_lt_i32                            ssrc,     imm16
s_cmpk_lt_u32                            ssrc,     imm16
s_getreg_b32                   sdst,     hwreg
s_movk_i32                     sdst,     imm16
s_mulk_i32                     sdst,     imm16
s_setreg_b32                   hwreg,    ssrc
s_setreg_imm32_b32             hwreg,    imm32
s_subvector_loop_begin         sdst,     label
s_subvector_loop_end           sdst,     label
s_version                                imm16
s_waitcnt_expcnt                         ssrc,     imm16
s_waitcnt_lgkmcnt                        ssrc,     imm16
s_waitcnt_vmcnt                          ssrc,     imm16
s_waitcnt_vscnt                          ssrc,     imm16

SOPP

INSTRUCTION                    SRC
——————————————————————————————————————————————
s_barrier
s_branch                       label
s_cbranch_cdbgsys              label
s_cbranch_cdbgsys_and_user     label
s_cbranch_cdbgsys_or_user      label
s_cbranch_cdbguser             label
s_cbranch_execnz               label
s_cbranch_execz                label
s_cbranch_scc0                 label
s_cbranch_scc1                 label
s_cbranch_vccnz                label
s_cbranch_vccz                 label
s_clause                       imm16
s_code_end
s_decperflevel                 imm16
s_denorm_mode                  imm16
s_endpgm
s_endpgm_ordered_ps_done
s_endpgm_saved
s_icache_inv
s_incperflevel                 imm16
s_inst_prefetch                imm16
s_nop                          imm16
s_round_mode                   imm16
s_sendmsg                      msg
s_sendmsghalt                  msg
s_sethalt                      imm16
s_setkill                      imm16
s_setprio                      imm16
s_sleep                        imm16
s_trap                         imm16
s_ttracedata
s_ttracedata_imm               imm16
s_waitcnt                      waitcnt
s_wakeup

VINTRP

INSTRUCTION                    DST       SRC0       SRC1
———————————————————————————————————————————————————————————————————
v_interp_mov_f32               vdst,     param:b32, attr:b32
v_interp_p1_f32                vdst,     vsrc,      attr:b32
v_interp_p2_f32                vdst,     vsrc,      attr:b32

VOP1

INSTRUCTION                    DST       SRC
————————————————————————————————————————————————————————
v_bfrev_b32                    vdst,     src
v_ceil_f16                     vdst,     src
v_ceil_f32                     vdst,     src
v_ceil_f64                     vdst,     src
v_clrexcp
v_cos_f16                      vdst,     src
v_cos_f32                      vdst,     src
v_cvt_f16_f32                  vdst,     src
v_cvt_f16_i16                  vdst,     src
v_cvt_f16_u16                  vdst,     src
v_cvt_f32_f16                  vdst,     src
v_cvt_f32_f64                  vdst,     src
v_cvt_f32_i32                  vdst,     src
v_cvt_f32_u32                  vdst,     src
v_cvt_f32_ubyte0               vdst,     src
v_cvt_f32_ubyte1               vdst,     src
v_cvt_f32_ubyte2               vdst,     src
v_cvt_f32_ubyte3               vdst,     src
v_cvt_f64_f32                  vdst,     src
v_cvt_f64_i32                  vdst,     src
v_cvt_f64_u32                  vdst,     src
v_cvt_flr_i32_f32              vdst,     src
v_cvt_i16_f16                  vdst,     src
v_cvt_i32_f32                  vdst,     src
v_cvt_i32_f64                  vdst,     src
v_cvt_norm_i16_f16             vdst,     src
v_cvt_norm_u16_f16             vdst,     src
v_cvt_off_f32_i4               vdst,     src
v_cvt_rpi_i32_f32              vdst,     src
v_cvt_u16_f16                  vdst,     src
v_cvt_u32_f32                  vdst,     src
v_cvt_u32_f64                  vdst,     src
v_exp_f16                      vdst,     src
v_exp_f32                      vdst,     src
v_ffbh_i32                     vdst,     src
v_ffbh_u32                     vdst,     src
v_ffbl_b32                     vdst,     src
v_floor_f16                    vdst,     src
v_floor_f32                    vdst,     src
v_floor_f64                    vdst,     src
v_fract_f16                    vdst,     src
v_fract_f32                    vdst,     src
v_fract_f64                    vdst,     src
v_frexp_exp_i16_f16            vdst,     src
v_frexp_exp_i32_f32            vdst,     src
v_frexp_exp_i32_f64            vdst,     src
v_frexp_mant_f16               vdst,     src
v_frexp_mant_f32               vdst,     src
v_frexp_mant_f64               vdst,     src
v_log_f16                      vdst,     src
v_log_f32                      vdst,     src
v_mov_b32                      vdst,     src
v_movreld_b32                  vdst,     src
v_movrels_b32                  vdst,     vsrc
v_movrelsd_2_b32               vdst,     vsrc
v_movrelsd_b32                 vdst,     vsrc
v_nop
v_not_b32                      vdst,     src
v_pipeflush
v_rcp_f16                      vdst,     src
v_rcp_f32                      vdst,     src
v_rcp_f64                      vdst,     src
v_rcp_iflag_f32                vdst,     src
v_readfirstlane_b32            sdst,     vsrc
v_rndne_f16                    vdst,     src
v_rndne_f32                    vdst,     src
v_rndne_f64                    vdst,     src
v_rsq_f16                      vdst,     src
v_rsq_f32                      vdst,     src
v_rsq_f64                      vdst,     src
v_sat_pk_u8_i16                vdst,     src
v_sin_f16                      vdst,     src
v_sin_f32                      vdst,     src
v_sqrt_f16                     vdst,     src
v_sqrt_f32                     vdst,     src
v_sqrt_f64                     vdst,     src
v_swap_b32                     vdst,     vsrc
v_swaprel_b32                  vdst,     vsrc
v_trunc_f16                    vdst,     src
v_trunc_f32                    vdst,     src
v_trunc_f64                    vdst,     src

VOP2

INSTRUCTION                    DST0      DST1      SRC0      SRC1      SRC2
——————————————————————————————————————————————————————————————————————————————————————
v_add_co_ci_u32                vdst,     vcc,      src0,     vsrc1,    vcc
v_add_f16                      vdst,               src0,     vsrc1
v_add_f32                      vdst,               src0,     vsrc1
v_add_nc_u32                   vdst,               src0,     vsrc1
v_and_b32                      vdst,               src0,     vsrc1
v_ashrrev_i32                  vdst,               src0:u32, vsrc1
v_cndmask_b32                  vdst,               src0,     vsrc1,    vcc
v_cvt_pkrtz_f16_f32            vdst,               src0,     vsrc1
v_fmaak_f16                    vdst,               src0,     vsrc1,    imm32
v_fmaak_f32                    vdst,               src0,     vsrc1,    imm32
v_fmac_f16                     vdst,               src0,     vsrc1
v_fmac_f32                     vdst,               src0,     vsrc1
v_fmamk_f16                    vdst,               src0,     imm32,    vsrc2
v_fmamk_f32                    vdst,               src0,     imm32,    vsrc2
v_ldexp_f16                    vdst,               src0,     vsrc1:i16
v_lshlrev_b32                  vdst,               src0:u32, vsrc1
v_lshrrev_b32                  vdst,               src0:u32, vsrc1
v_mac_f32                      vdst,               src0,     vsrc1
v_mac_legacy_f32               vdst,               src0,     vsrc1
v_madak_f32                    vdst,               src0,     vsrc1,    imm32
v_madmk_f32                    vdst,               src0,     imm32,    vsrc2
v_max_f16                      vdst,               src0,     vsrc1
v_max_f32                      vdst,               src0,     vsrc1
v_max_i32                      vdst,               src0,     vsrc1
v_max_u32                      vdst,               src0,     vsrc1
v_min_f16                      vdst,               src0,     vsrc1
v_min_f32                      vdst,               src0,     vsrc1
v_min_i32                      vdst,               src0,     vsrc1
v_min_u32                      vdst,               src0,     vsrc1
v_mul_f16                      vdst,               src0,     vsrc1
v_mul_f32                      vdst,               src0,     vsrc1
v_mul_hi_i32_i24               vdst,               src0,     vsrc1
v_mul_hi_u32_u24               vdst,               src0,     vsrc1
v_mul_i32_i24                  vdst,               src0,     vsrc1
v_mul_legacy_f32               vdst,               src0,     vsrc1
v_mul_u32_u24                  vdst,               src0,     vsrc1
v_or_b32                       vdst,               src0,     vsrc1
v_pk_fmac_f16                  vdst,               src0,     vsrc1
v_sub_co_ci_u32                vdst,     vcc,      src0,     vsrc1,    vcc
v_sub_f16                      vdst,               src0,     vsrc1
v_sub_f32                      vdst,               src0,     vsrc1
v_sub_nc_u32                   vdst,               src0,     vsrc1
v_subrev_co_ci_u32             vdst,     vcc,      src0,     vsrc1,    vcc
v_subrev_f16                   vdst,               src0,     vsrc1
v_subrev_f32                   vdst,               src0,     vsrc1
v_subrev_nc_u32                vdst,               src0,     vsrc1
v_xnor_b32                     vdst,               src0,     vsrc1
v_xor_b32                      vdst,               src0,     vsrc1

VOP3

INSTRUCTION             DST0       DST1     SRC0         SRC1        SRC2            MODIFIERS
—————————————————————————————————————————————————————————————————————————————————————————————————————
v_add3_u32              vdst,               src0,        src1,       src2
v_add_co_ci_u32_e64     vdst,      sdst,    src0,        src1,       ssrc2           clamp
v_add_co_u32            vdst,      sdst,    src0,        src1                        clamp
v_add_f16_e64           vdst,               src0:m,      src1:m                      clamp
v_add_f32_e64           vdst,               src0:m,      src1:m                      clamp omod
v_add_f64               vdst,               src0:m,      src1:m                      clamp omod
v_add_lshl_u32          vdst,               src0,        src1,       src2
v_add_nc_i16            vdst,               src0,        src1                        op_sel clamp
v_add_nc_i32            vdst,               src0,        src1
v_add_nc_u16            vdst,               src0,        src1
v_add_nc_u32_e64        vdst,               src0,        src1                        clamp
v_alignbit_b32          vdst,               src0,        src1,       src2
v_alignbyte_b32         vdst,               src0,        src1,       src2
v_and_b32_e64           vdst,               src0,        src1
v_and_or_b32            vdst,               src0,        src1,       src2
v_ashrrev_i16           vdst,               src0:u16,    src1
v_ashrrev_i32_e64       vdst,               src0:u32,    src1
v_ashrrev_i64           vdst,               src0:u32,    src1
v_bcnt_u32_b32          vdst,               src0,        src1
v_bfe_i32               vdst,               src0,        src1:u32,   src2:u32
v_bfe_u32               vdst,               src0,        src1,       src2
v_bfi_b32               vdst,               src0,        src1,       src2
v_bfm_b32               vdst,               src0,        src1
v_bfrev_b32_e64         vdst,               src
v_ceil_f16_e64          vdst,               src:m                                    clamp
v_ceil_f32_e64          vdst,               src:m                                    clamp omod
v_ceil_f64_e64          vdst,               src:m                                    clamp omod
v_clrexcp_e64
v_cmp_class_f16_e64     sdst,               src0:m,      src1:b32
v_cmp_class_f32_e64     sdst,               src0:m,      src1:b32
v_cmp_class_f64_e64     sdst,               src0:m,      src1:b32
v_cmp_eq_f16_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_eq_f32_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_eq_f64_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_eq_i16_e64        sdst,               src0,        src1
v_cmp_eq_i32_e64        sdst,               src0,        src1
v_cmp_eq_i64_e64        sdst,               src0,        src1
v_cmp_eq_u16_e64        sdst,               src0,        src1
v_cmp_eq_u32_e64        sdst,               src0,        src1
v_cmp_eq_u64_e64        sdst,               src0,        src1
v_cmp_f_f16_e64         sdst,               src0:m,      src1:m                      clamp
v_cmp_f_f32_e64         sdst,               src0:m,      src1:m                      clamp
v_cmp_f_f64_e64         sdst,               src0:m,      src1:m                      clamp
v_cmp_f_i32_e64         sdst,               src0,        src1
v_cmp_f_i64_e64         sdst,               src0,        src1
v_cmp_f_u32_e64         sdst,               src0,        src1
v_cmp_f_u64_e64         sdst,               src0,        src1
v_cmp_ge_f16_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_ge_f32_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_ge_f64_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_ge_i16_e64        sdst,               src0,        src1
v_cmp_ge_i32_e64        sdst,               src0,        src1
v_cmp_ge_i64_e64        sdst,               src0,        src1
v_cmp_ge_u16_e64        sdst,               src0,        src1
v_cmp_ge_u32_e64        sdst,               src0,        src1
v_cmp_ge_u64_e64        sdst,               src0,        src1
v_cmp_gt_f16_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_gt_f32_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_gt_f64_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_gt_i16_e64        sdst,               src0,        src1
v_cmp_gt_i32_e64        sdst,               src0,        src1
v_cmp_gt_i64_e64        sdst,               src0,        src1
v_cmp_gt_u16_e64        sdst,               src0,        src1
v_cmp_gt_u32_e64        sdst,               src0,        src1
v_cmp_gt_u64_e64        sdst,               src0,        src1
v_cmp_le_f16_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_le_f32_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_le_f64_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_le_i16_e64        sdst,               src0,        src1
v_cmp_le_i32_e64        sdst,               src0,        src1
v_cmp_le_i64_e64        sdst,               src0,        src1
v_cmp_le_u16_e64        sdst,               src0,        src1
v_cmp_le_u32_e64        sdst,               src0,        src1
v_cmp_le_u64_e64        sdst,               src0,        src1
v_cmp_lg_f16_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_lg_f32_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_lg_f64_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_lt_f16_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_lt_f32_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_lt_f64_e64        sdst,               src0:m,      src1:m                      clamp
v_cmp_lt_i16_e64        sdst,               src0,        src1
v_cmp_lt_i32_e64        sdst,               src0,        src1
v_cmp_lt_i64_e64        sdst,               src0,        src1
v_cmp_lt_u16_e64        sdst,               src0,        src1
v_cmp_lt_u32_e64        sdst,               src0,        src1
v_cmp_lt_u64_e64        sdst,               src0,        src1
v_cmp_ne_i16_e64        sdst,               src0,        src1
v_cmp_ne_i32_e64        sdst,               src0,        src1
v_cmp_ne_i64_e64        sdst,               src0,        src1
v_cmp_ne_u16_e64        sdst,               src0,        src1
v_cmp_ne_u32_e64        sdst,               src0,        src1
v_cmp_ne_u64_e64        sdst,               src0,        src1
v_cmp_neq_f16_e64       sdst,               src0:m,      src1:m                      clamp
v_cmp_neq_f32_e64       sdst,               src0: