LLVM 20.0.0git
LoongArchDeadRegisterDefinitions.cpp
Go to the documentation of this file.
1//=== LoongArchDeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg ===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===---------------------------------------------------------------------===//
8//
9// This pass rewrites Rd to r0 for instrs whose return values are unused.
10//
11//===---------------------------------------------------------------------===//
12
13#include "LoongArch.h"
14#include "LoongArchSubtarget.h"
15#include "llvm/ADT/Statistic.h"
20
21using namespace llvm;
22#define DEBUG_TYPE "loongarch-dead-defs"
23#define LoongArch_DEAD_REG_DEF_NAME "LoongArch Dead register definitions"
24
25STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
26
27namespace {
28class LoongArchDeadRegisterDefinitions : public MachineFunctionPass {
29public:
30 static char ID;
31
32 LoongArchDeadRegisterDefinitions() : MachineFunctionPass(ID) {}
33 bool runOnMachineFunction(MachineFunction &MF) override;
34 void getAnalysisUsage(AnalysisUsage &AU) const override {
35 AU.setPreservesCFG();
43 }
44
45 StringRef getPassName() const override { return LoongArch_DEAD_REG_DEF_NAME; }
46};
47} // end anonymous namespace
48
49char LoongArchDeadRegisterDefinitions::ID = 0;
50INITIALIZE_PASS(LoongArchDeadRegisterDefinitions, DEBUG_TYPE,
51 LoongArch_DEAD_REG_DEF_NAME, false, false)
52
54 return new LoongArchDeadRegisterDefinitions();
55}
56
57bool LoongArchDeadRegisterDefinitions::runOnMachineFunction(
58 MachineFunction &MF) {
59 if (skipFunction(MF.getFunction()))
60 return false;
61
64 LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
65 LLVM_DEBUG(dbgs() << "***** LoongArchDeadRegisterDefinitions *****\n");
66
67 bool MadeChange = false;
68 for (MachineBasicBlock &MBB : MF) {
69 for (MachineInstr &MI : MBB) {
70 // We only handle non-computational instructions.
71 const MCInstrDesc &Desc = MI.getDesc();
72 if (!Desc.mayLoad() && !Desc.mayStore() &&
73 !Desc.hasUnmodeledSideEffects())
74 continue;
75 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
76 MachineOperand &MO = MI.getOperand(I);
77 if (!MO.isReg() || !MO.isDef() || MO.isEarlyClobber())
78 continue;
79 // Be careful not to change the register if it's a tied operand.
80 if (MI.isRegTiedToUseOperand(I)) {
81 LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
82 continue;
83 }
84 Register Reg = MO.getReg();
85 if (!Reg.isVirtual() || !MO.isDead())
86 continue;
87 LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";
88 MI.print(dbgs()));
89 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
90 if (!(RC && RC->contains(LoongArch::R0))) {
91 LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
92 continue;
93 }
94 assert(LIS.hasInterval(Reg));
95 LIS.removeInterval(Reg);
96 MO.setReg(LoongArch::R0);
97 LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n ";
98 MI.print(dbgs()));
99 ++NumDeadDefsReplaced;
100 MadeChange = true;
101 }
102 }
103 }
104
105 return MadeChange;
106}
MachineBasicBlock & MBB
#define LLVM_DEBUG(...)
Definition: Debug.h:106
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define LoongArch_DEAD_REG_DEF_NAME
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:166
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:256
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:310
bool hasInterval(Register Reg) const
void removeInterval(Register Reg)
Interval removal.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
TargetInstrInfo - Interface to description of machine instruction set.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createLoongArchDeadRegisterDefinitionsPass()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
Description of the encoding of one expression Op.