LLVM 20.0.0git
Context.cpp
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1//===---------------------------- Context.cpp -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file defines a class for holding ownership of various simulated
11/// hardware units. A Context also provides a utility routine for constructing
12/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
13/// stages.
14///
15//===----------------------------------------------------------------------===//
16
17#include "llvm/MCA/Context.h"
27
28namespace llvm {
29namespace mca {
30
31std::unique_ptr<Pipeline>
33 CustomBehaviour &CB) {
34 const MCSchedModel &SM = STI.getSchedModel();
35
36 if (!SM.isOutOfOrder())
37 return createInOrderPipeline(Opts, SrcMgr, CB);
38
39 // Create the hardware units defining the backend.
40 auto RCU = std::make_unique<RetireControlUnit>(SM);
41 auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
42 auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
43 Opts.StoreQueueSize, Opts.AssumeNoAlias);
44 auto HWS = std::make_unique<Scheduler>(SM, *LSU);
45
46 // Create the pipeline stages.
47 auto Fetch = std::make_unique<EntryStage>(SrcMgr);
48 auto Dispatch =
49 std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth, *RCU, *PRF);
50 auto Execute =
51 std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis);
52 auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU);
53
54 // Pass the ownership of all the hardware units to this Context.
55 addHardwareUnit(std::move(RCU));
56 addHardwareUnit(std::move(PRF));
57 addHardwareUnit(std::move(LSU));
58 addHardwareUnit(std::move(HWS));
59
60 // Build the pipeline.
61 auto StagePipeline = std::make_unique<Pipeline>();
62 StagePipeline->appendStage(std::move(Fetch));
63 if (Opts.MicroOpQueueSize)
64 StagePipeline->appendStage(std::make_unique<MicroOpQueueStage>(
66 StagePipeline->appendStage(std::move(Dispatch));
67 StagePipeline->appendStage(std::move(Execute));
68 StagePipeline->appendStage(std::move(Retire));
69 return StagePipeline;
70}
71
72std::unique_ptr<Pipeline>
74 CustomBehaviour &CB) {
75 const MCSchedModel &SM = STI.getSchedModel();
76 auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
77 auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
78 Opts.StoreQueueSize, Opts.AssumeNoAlias);
79
80 // Create the pipeline stages.
81 auto Entry = std::make_unique<EntryStage>(SrcMgr);
82 auto InOrderIssue = std::make_unique<InOrderIssueStage>(STI, *PRF, CB, *LSU);
83 auto StagePipeline = std::make_unique<Pipeline>();
84
85 // Pass the ownership of all the hardware units to this Context.
86 addHardwareUnit(std::move(PRF));
87 addHardwareUnit(std::move(LSU));
88
89 // Build the pipeline.
90 StagePipeline->appendStage(std::move(Entry));
91 StagePipeline->appendStage(std::move(InOrderIssue));
92 return StagePipeline;
93}
94
95} // namespace mca
96} // namespace llvm
This file models the dispatch component of an instruction pipeline.
This file defines the Entry stage of an instruction pipeline.
This file defines the execution stage of a default instruction pipeline.
InOrderIssueStage implements an in-order execution pipeline.
This file defines a class for holding ownership of various simulated hardware units.
A scheduler for Processor Resource Units and Processor Resource Groups.
This file defines a stage that implements a queue of micro opcodes.
static bool Execute(ProcessInfo &PI, StringRef Program, ArrayRef< StringRef > Args, std::optional< ArrayRef< StringRef > > Env, ArrayRef< std::optional< StringRef > > Redirects, unsigned MemoryLimit, std::string *ErrMsg, BitVector *AffinityMask, bool DetachProcess)
This file defines a register mapping file class.
This file simulates the hardware responsible for retiring instructions.
This file defines the retire stage of a default instruction pipeline.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
std::unique_ptr< Pipeline > createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB)
Construct a basic pipeline for simulating an in-order pipeline.
Definition: Context.cpp:73
void addHardwareUnit(std::unique_ptr< HardwareUnit > H)
Definition: Context.h:64
std::unique_ptr< Pipeline > createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB)
Construct a basic pipeline for simulating an out-of-order pipeline.
Definition: Context.cpp:32
Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren'...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
SourceMgr SrcMgr
Definition: Error.cpp:24
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:256
bool isOutOfOrder() const
Return true if machine supports out of order execution.
Definition: MCSchedule.h:350
This is a convenience struct to hold the parameters necessary for creating the pre-built "default" ou...
Definition: Context.h:33
unsigned DecodersThroughput
Definition: Context.h:42
Abstracting the input code sequence (a sequence of MCInst) and assigning unique identifiers to every ...
Definition: SourceMgr.h:29