LLVM
22.0.0git
lib
Target
SPIRV
MCTargetDesc
SPIRVMCTargetDesc.h
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//===-- SPIRVMCTargetDesc.h - SPIR-V Target Descriptions --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides SPIR-V specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVMCTARGETDESC_H
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#define LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVMCTARGETDESC_H
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#include "
llvm/Support/DataTypes.h
"
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#include <cassert>
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#include <memory>
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namespace
llvm
{
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class
MCAsmBackend
;
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class
MCCodeEmitter
;
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class
MCContext
;
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class
MCInstrInfo
;
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class
MCObjectTargetWriter
;
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class
MCRegisterInfo
;
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class
MCSubtargetInfo
;
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class
MCTargetOptions
;
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class
Target
;
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MCCodeEmitter
*
createSPIRVMCCodeEmitter
(
const
MCInstrInfo
&MCII,
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MCContext
&Ctx);
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MCAsmBackend
*
createSPIRVAsmBackend
(
const
Target
&
T
,
const
MCSubtargetInfo
&STI,
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const
MCRegisterInfo
&
MRI
,
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const
MCTargetOptions
&
Options
);
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}
// namespace llvm
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// Defines symbolic names for SPIR-V registers. This defines a mapping from
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// register name to register number.
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#define GET_REGINFO_ENUM
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#include "SPIRVGenRegisterInfo.inc"
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// Defines symbolic names for the SPIR-V instructions.
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#define GET_INSTRINFO_ENUM
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#define GET_INSTRINFO_MC_HELPER_DECLS
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#include "SPIRVGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "SPIRVGenSubtargetInfo.inc"
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namespace
llvm::SPIRV
{
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inline
unsigned
getIDFromRegister
(
unsigned
Reg
) {
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assert
(
Reg
& (1U << 31));
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return
Reg
& ~(1U << 31);
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}
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}
// namespace llvm::SPIRV
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#endif
// LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVMCTARGETDESC_H
MRI
unsigned const MachineRegisterInfo * MRI
Definition
AArch64AdvSIMDScalarPass.cpp:103
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Options
static LVOptions Options
Definition
LVOptions.cpp:25
Reg
Register Reg
Definition
MachineSink.cpp:2117
T
#define T
Definition
Mips16ISelLowering.cpp:353
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition
MCAsmBackend.h:55
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition
MCCodeEmitter.h:22
llvm::MCContext
Context object for machine code objects.
Definition
MCContext.h:83
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition
MCInstrInfo.h:27
llvm::MCObjectTargetWriter
Base class for classes that define behaviour that is specific to both the target and the object forma...
Definition
MCObjectWriter.h:136
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition
MCRegisterInfo.h:150
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition
MCSubtargetInfo.h:77
llvm::MCTargetOptions
Definition
MCTargetOptions.h:29
llvm::Target
Target - Wrapper for Target specific information.
Definition
TargetRegistry.h:146
DataTypes.h
llvm::SPIRV
Definition
SPIRVConvergenceRegionAnalysis.h:31
llvm::SPIRV::getIDFromRegister
unsigned getIDFromRegister(unsigned Reg)
Definition
SPIRVMCTargetDesc.h:53
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition
AddressRanges.h:18
llvm::createSPIRVMCCodeEmitter
MCCodeEmitter * createSPIRVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition
SPIRVMCCodeEmitter.cpp:52
llvm::createSPIRVAsmBackend
MCAsmBackend * createSPIRVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition
SPIRVAsmBackend.cpp:39
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