23 unsigned OpIdx1, OpIdx2;
24 unsigned Opcode =
MI.getOpcode();
26#define FROM_TO(FROM, TO, IDX1, IDX2) \
32#define TO_REV(FROM) FROM_TO(FROM, FROM##_REV, 0, 1)
42 MI.getNumOperands() != 3)
45 if (Opcode == X86::VMOVHLPSrr || Opcode == X86::VUNPCKHPDrr)
56 case X86::VCMPSSrri: {
57 switch (
MI.getOperand(3).getImm() & 0x7) {
72 FROM_TO(VMOVZPQILo2PQIrr, VMOVPQI2QIrr, 0, 1)
86#define TO_REV(FROM) FROM_TO(FROM, FROM##_REV, 0, 2)
106#define TO_IMM1(FROM) \
108 NewOpc = X86::FROM##1; \
110 case X86::FROM##i_EVEX: \
111 NewOpc = X86::FROM##1_EVEX; \
113 case X86::FROM##i_ND: \
114 NewOpc = X86::FROM##1_ND; \
116 switch (
MI.getOpcode()) {
136#define TO_IMM1(FROM) \
138 NewOpc = X86::FROM##1; \
140 case X86::FROM##i_EVEX: \
141 NewOpc = X86::FROM##1_EVEX; \
143 case X86::FROM##i_NF: \
144 NewOpc = X86::FROM##1_NF; \
146 case X86::FROM##i_ND: \
147 NewOpc = X86::FROM##1_ND; \
149 case X86::FROM##i_NF_ND: \
150 NewOpc = X86::FROM##1_NF_ND; \
197 MI.setOpcode(NewOpc);
205#define FROM_TO(FROM, TO1, TO2) \
210 switch (
MI.getOpcode()) {
213 FROM_TO(VPCMPBZ128rmi, VPCMPEQBZ128rm, VPCMPGTBZ128rm)
214 FROM_TO(VPCMPBZ128rmik, VPCMPEQBZ128rmk, VPCMPGTBZ128rmk)
215 FROM_TO(VPCMPBZ128rri, VPCMPEQBZ128rr, VPCMPGTBZ128rr)
216 FROM_TO(VPCMPBZ128rrik, VPCMPEQBZ128rrk, VPCMPGTBZ128rrk)
217 FROM_TO(VPCMPBZ256rmi, VPCMPEQBZ256rm, VPCMPGTBZ256rm)
218 FROM_TO(VPCMPBZ256rmik, VPCMPEQBZ256rmk, VPCMPGTBZ256rmk)
219 FROM_TO(VPCMPBZ256rri, VPCMPEQBZ256rr, VPCMPGTBZ256rr)
220 FROM_TO(VPCMPBZ256rrik, VPCMPEQBZ256rrk, VPCMPGTBZ256rrk)
221 FROM_TO(VPCMPBZrmi, VPCMPEQBZrm, VPCMPGTBZrm)
222 FROM_TO(VPCMPBZrmik, VPCMPEQBZrmk, VPCMPGTBZrmk)
223 FROM_TO(VPCMPBZrri, VPCMPEQBZrr, VPCMPGTBZrr)
224 FROM_TO(VPCMPBZrrik, VPCMPEQBZrrk, VPCMPGTBZrrk)
225 FROM_TO(VPCMPDZ128rmi, VPCMPEQDZ128rm, VPCMPGTDZ128rm)
226 FROM_TO(VPCMPDZ128rmib, VPCMPEQDZ128rmb, VPCMPGTDZ128rmb)
227 FROM_TO(VPCMPDZ128rmibk, VPCMPEQDZ128rmbk, VPCMPGTDZ128rmbk)
228 FROM_TO(VPCMPDZ128rmik, VPCMPEQDZ128rmk, VPCMPGTDZ128rmk)
229 FROM_TO(VPCMPDZ128rri, VPCMPEQDZ128rr, VPCMPGTDZ128rr)
230 FROM_TO(VPCMPDZ128rrik, VPCMPEQDZ128rrk, VPCMPGTDZ128rrk)
231 FROM_TO(VPCMPDZ256rmi, VPCMPEQDZ256rm, VPCMPGTDZ256rm)
232 FROM_TO(VPCMPDZ256rmib, VPCMPEQDZ256rmb, VPCMPGTDZ256rmb)
233 FROM_TO(VPCMPDZ256rmibk, VPCMPEQDZ256rmbk, VPCMPGTDZ256rmbk)
234 FROM_TO(VPCMPDZ256rmik, VPCMPEQDZ256rmk, VPCMPGTDZ256rmk)
235 FROM_TO(VPCMPDZ256rri, VPCMPEQDZ256rr, VPCMPGTDZ256rr)
236 FROM_TO(VPCMPDZ256rrik, VPCMPEQDZ256rrk, VPCMPGTDZ256rrk)
237 FROM_TO(VPCMPDZrmi, VPCMPEQDZrm, VPCMPGTDZrm)
238 FROM_TO(VPCMPDZrmib, VPCMPEQDZrmb, VPCMPGTDZrmb)
239 FROM_TO(VPCMPDZrmibk, VPCMPEQDZrmbk, VPCMPGTDZrmbk)
240 FROM_TO(VPCMPDZrmik, VPCMPEQDZrmk, VPCMPGTDZrmk)
241 FROM_TO(VPCMPDZrri, VPCMPEQDZrr, VPCMPGTDZrr)
242 FROM_TO(VPCMPDZrrik, VPCMPEQDZrrk, VPCMPGTDZrrk)
243 FROM_TO(VPCMPQZ128rmi, VPCMPEQQZ128rm, VPCMPGTQZ128rm)
244 FROM_TO(VPCMPQZ128rmib, VPCMPEQQZ128rmb, VPCMPGTQZ128rmb)
245 FROM_TO(VPCMPQZ128rmibk, VPCMPEQQZ128rmbk, VPCMPGTQZ128rmbk)
246 FROM_TO(VPCMPQZ128rmik, VPCMPEQQZ128rmk, VPCMPGTQZ128rmk)
247 FROM_TO(VPCMPQZ128rri, VPCMPEQQZ128rr, VPCMPGTQZ128rr)
248 FROM_TO(VPCMPQZ128rrik, VPCMPEQQZ128rrk, VPCMPGTQZ128rrk)
249 FROM_TO(VPCMPQZ256rmi, VPCMPEQQZ256rm, VPCMPGTQZ256rm)
250 FROM_TO(VPCMPQZ256rmib, VPCMPEQQZ256rmb, VPCMPGTQZ256rmb)
251 FROM_TO(VPCMPQZ256rmibk, VPCMPEQQZ256rmbk, VPCMPGTQZ256rmbk)
252 FROM_TO(VPCMPQZ256rmik, VPCMPEQQZ256rmk, VPCMPGTQZ256rmk)
253 FROM_TO(VPCMPQZ256rri, VPCMPEQQZ256rr, VPCMPGTQZ256rr)
254 FROM_TO(VPCMPQZ256rrik, VPCMPEQQZ256rrk, VPCMPGTQZ256rrk)
255 FROM_TO(VPCMPQZrmi, VPCMPEQQZrm, VPCMPGTQZrm)
256 FROM_TO(VPCMPQZrmib, VPCMPEQQZrmb, VPCMPGTQZrmb)
257 FROM_TO(VPCMPQZrmibk, VPCMPEQQZrmbk, VPCMPGTQZrmbk)
258 FROM_TO(VPCMPQZrmik, VPCMPEQQZrmk, VPCMPGTQZrmk)
259 FROM_TO(VPCMPQZrri, VPCMPEQQZrr, VPCMPGTQZrr)
260 FROM_TO(VPCMPQZrrik, VPCMPEQQZrrk, VPCMPGTQZrrk)
261 FROM_TO(VPCMPWZ128rmi, VPCMPEQWZ128rm, VPCMPGTWZ128rm)
262 FROM_TO(VPCMPWZ128rmik, VPCMPEQWZ128rmk, VPCMPGTWZ128rmk)
263 FROM_TO(VPCMPWZ128rri, VPCMPEQWZ128rr, VPCMPGTWZ128rr)
264 FROM_TO(VPCMPWZ128rrik, VPCMPEQWZ128rrk, VPCMPGTWZ128rrk)
265 FROM_TO(VPCMPWZ256rmi, VPCMPEQWZ256rm, VPCMPGTWZ256rm)
266 FROM_TO(VPCMPWZ256rmik, VPCMPEQWZ256rmk, VPCMPGTWZ256rmk)
267 FROM_TO(VPCMPWZ256rri, VPCMPEQWZ256rr, VPCMPGTWZ256rr)
268 FROM_TO(VPCMPWZ256rrik, VPCMPEQWZ256rrk, VPCMPGTWZ256rrk)
269 FROM_TO(VPCMPWZrmi, VPCMPEQWZrm, VPCMPGTWZrm)
270 FROM_TO(VPCMPWZrmik, VPCMPEQWZrmk, VPCMPGTWZrmk)
271 FROM_TO(VPCMPWZrri, VPCMPEQWZrr, VPCMPGTWZrr)
272 FROM_TO(VPCMPWZrrik, VPCMPEQWZrrk, VPCMPGTWZrrk)
276 int64_t Imm = LastOp.
getImm();
284 MI.setOpcode(NewOpc);
291#define FROM_TO(FROM, TO, R0, R1) \
293 if (MI.getOperand(0).getReg() != X86::R0 || \
294 MI.getOperand(1).getReg() != X86::R1) \
298 switch (
MI.getOpcode()) {
301 FROM_TO(MOVSX16rr8, CBW, AX, AL)
302 FROM_TO(MOVSX32rr16, CWDE, EAX, AX)
303 FROM_TO(MOVSX64rr32, CDQE, RAX, EAX)
307 MI.setOpcode(NewOpc);
316#define FROM_TO(FROM, TO) \
320 switch (
MI.getOpcode()) {
328 MI.setOpcode(NewOpc);
333 return Reg == X86::AL || Reg == X86::AX || Reg == X86::EAX || Reg == X86::RAX;
350 switch (
MI.getOpcode()) {
353 FROM_TO(MOV8mr_NOREX, MOV8o32a)
355 FROM_TO(MOV8rm_NOREX, MOV8ao32)
362 bool IsStore =
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg();
363 unsigned AddrBase = IsStore;
364 unsigned RegOp = IsStore ? 0 : 5;
365 unsigned AddrOp = AddrBase + 3;
367 unsigned Reg =
MI.getOperand(RegOp).getReg();
373 bool Absolute =
true;
374 if (
MI.getOperand(AddrOp).isExpr()) {
375 const MCExpr *MCE =
MI.getOperand(AddrOp).getExpr();
388 MI.setOpcode(NewOpc);
398 switch (
MI.getOpcode()) {
439 unsigned Reg =
MI.getOperand(0).getReg();
446 MI.setOpcode(NewOpc);
452#define ENTRY(LONG, SHORT) \
458#include "X86EncodingOptimizationForImmediate.def"
463#define ENTRY(LONG, SHORT) \
469#include "X86EncodingOptimizationForImmediate.def"
475#define ENTRY(LONG, SHORT) \
477 NewOpc = X86::SHORT; \
479 switch (
MI.getOpcode()) {
482#include "X86EncodingOptimizationForImmediate.def"
484 unsigned SkipOperands = X86::isCCMPCC(
MI.getOpcode()) ? 2 : 0;
485 MCOperand &LastOp =
MI.getOperand(
MI.getNumOperands() - 1 - SkipOperands);
490 }
else if (LastOp.
isImm()) {
491 if (!isInt<8>(LastOp.
getImm()))
494 MI.setOpcode(NewOpc);
502 return ShortImm || FixedReg;
Fixup Statepoint Caller Saved
static bool optimizeToShortImmediateForm(MCInst &MI)
#define FROM_TO(FROM, TO, IDX1, IDX2)
static bool optimizeToFixedRegisterForm(MCInst &MI)
Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with a short fixed-register form.
static bool isARegister(unsigned Reg)
Base class for the full range of assembler expressions which are needed for parsing.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
Instances of this class represent operands of the MCInst class.
const MCExpr * getExpr() const
Represent a reference to a symbol from inside an expression.
VariantKind getKind() const
bool isX86_64ExtendedReg(unsigned RegNo)
@ VEX
VEX - encoding using 0xC4/0xC5.
@ TB
TB - TwoByte - Set if this instruction has a two byte opcode, which starts with a 0x0F byte before th...
@ MRMSrcReg
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source,...
bool optimizeToFixedRegisterOrShortImmediateForm(MCInst &MI)
bool optimizeMOV(MCInst &MI, bool In64BitMode)
Simplify things like MOV32rm to MOV32o32a.
bool optimizeMOVSX(MCInst &MI)
bool optimizeVPCMPWithImmediateOneOrSix(MCInst &MI)
bool optimizeShiftRotateWithImmediateOne(MCInst &MI)
bool optimizeInstFromVEX3ToVEX2(MCInst &MI, const MCInstrDesc &Desc)
unsigned getOpcodeForLongImmediateForm(unsigned Opcode)
bool optimizeINCDEC(MCInst &MI, bool In64BitMode)
unsigned getOpcodeForShortImmediateForm(unsigned Opcode)
This is an optimization pass for GlobalISel generic memory operations.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Description of the encoding of one expression Op.