LLVM 22.0.0git
ARMDisassembler.cpp
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1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ARMBaseInstrInfo.h"
14#include "Utils/ARMBaseInfo.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDecoder.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrDesc.h"
21#include "llvm/MC/MCInstrInfo.h"
29#include <algorithm>
30#include <cassert>
31#include <cstdint>
32#include <vector>
33
34using namespace llvm;
35using namespace llvm::MCD;
36
37#define DEBUG_TYPE "arm-disassembler"
38
40
41namespace {
42
43// Handles the condition code status of instructions in IT blocks
44class ITStatus {
45public:
46 // Returns the condition code for instruction in IT block
47 unsigned getITCC() {
48 unsigned CC = ARMCC::AL;
49 if (instrInITBlock())
50 CC = ITStates.back();
51 return CC;
52 }
53
54 // Advances the IT block state to the next T or E
55 void advanceITState() { ITStates.pop_back(); }
56
57 // Returns true if the current instruction is in an IT block
58 bool instrInITBlock() { return !ITStates.empty(); }
59
60 // Returns true if current instruction is the last instruction in an IT block
61 bool instrLastInITBlock() { return ITStates.size() == 1; }
62
63 // Called when decoding an IT instruction. Sets the IT state for
64 // the following instructions that for the IT block. Firstcond
65 // corresponds to the field in the IT instruction encoding; Mask
66 // is in the MCOperand format in which 1 means 'else' and 0 'then'.
67 void setITState(char Firstcond, char Mask) {
68 // (3 - the number of trailing zeros) is the number of then / else.
69 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask);
70 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
71 assert(NumTZ <= 3 && "Invalid IT mask!");
72 // push condition codes onto the stack the correct order for the pops
73 for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
74 unsigned Else = (Mask >> Pos) & 1;
75 ITStates.push_back(CCBits ^ Else);
76 }
77 ITStates.push_back(CCBits);
78 }
79
80private:
81 std::vector<unsigned char> ITStates;
82};
83
84class VPTStatus {
85public:
86 unsigned getVPTPred() {
87 unsigned Pred = ARMVCC::None;
88 if (instrInVPTBlock())
89 Pred = VPTStates.back();
90 return Pred;
91 }
92
93 void advanceVPTState() { VPTStates.pop_back(); }
94
95 bool instrInVPTBlock() { return !VPTStates.empty(); }
96
97 bool instrLastInVPTBlock() { return VPTStates.size() == 1; }
98
99 void setVPTState(char Mask) {
100 // (3 - the number of trailing zeros) is the number of then / else.
101 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask);
102 assert(NumTZ <= 3 && "Invalid VPT mask!");
103 // push predicates onto the stack the correct order for the pops
104 for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
105 bool T = ((Mask >> Pos) & 1) == 0;
106 if (T)
107 VPTStates.push_back(ARMVCC::Then);
108 else
109 VPTStates.push_back(ARMVCC::Else);
110 }
111 VPTStates.push_back(ARMVCC::Then);
112 }
113
114private:
116};
117
118/// ARM disassembler for all ARM platforms.
119class ARMDisassembler : public MCDisassembler {
120public:
121 std::unique_ptr<const MCInstrInfo> MCII;
122 mutable ITStatus ITBlock;
123 mutable VPTStatus VPTBlock;
124
125 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
126 const MCInstrInfo *MCII)
127 : MCDisassembler(STI, Ctx), MCII(MCII) {
128 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions)
131 }
132
133 ~ARMDisassembler() override = default;
134
135 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
136 ArrayRef<uint8_t> Bytes, uint64_t Address,
137 raw_ostream &CStream) const override;
138
139 uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
140 uint64_t Address) const override;
141
142private:
143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
144 ArrayRef<uint8_t> Bytes, uint64_t Address,
145 raw_ostream &CStream) const;
146
147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
148 ArrayRef<uint8_t> Bytes, uint64_t Address,
149 raw_ostream &CStream) const;
150
151 bool isVectorPredicable(const MCInst &MI) const;
152 DecodeStatus AddThumbPredicate(MCInst&) const;
153 void UpdateThumbPredicate(DecodeStatus &S, MCInst &MI) const;
154
155 llvm::endianness InstructionEndianness;
156};
157
158} // end anonymous namespace
159
160typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
161 uint64_t Address,
162 const MCDisassembler *Decoder);
163
164/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
165/// immediate Value in the MCInst. The immediate Value has had any PC
166/// adjustment made by the caller. If the instruction is a branch instruction
167/// then isBranch is true, else false. If the getOpInfo() function was set as
168/// part of the setupForSymbolicDisassembly() call then that function is called
169/// to get any symbolic information at the Address for this instruction. If
170/// that returns non-zero then the symbolic information it returns is used to
171/// create an MCExpr and that is added as an operand to the MCInst. If
172/// getOpInfo() returns zero and isBranch is true then a symbol look up for
173/// Value is done and if a symbol is found an MCExpr is created with that, else
174/// an MCExpr with Value is created. This function returns true if it adds an
175/// operand to the MCInst and false otherwise.
176static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
177 bool isBranch, uint64_t InstSize,
178 MCInst &MI,
179 const MCDisassembler *Decoder) {
180 // FIXME: Does it make sense for value to be negative?
181 return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address,
182 isBranch, /*Offset=*/0, /*OpSize=*/0,
183 InstSize);
184}
185
186/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
187/// referenced by a load instruction with the base register that is the Pc.
188/// These can often be values in a literal pool near the Address of the
189/// instruction. The Address of the instruction and its immediate Value are
190/// used as a possible literal pool entry. The SymbolLookUp call back will
191/// return the name of a symbol referenced by the literal pool's entry if
192/// the referenced address is that of a symbol. Or it will return a pointer to
193/// a literal 'C' string if the referenced address of the literal pool's entry
194/// is an address into a section with 'C' string literals.
196 const MCDisassembler *Decoder) {
197 Decoder->tryAddingPcLoadReferenceComment(Value, Address);
198}
199
200// Register class decoding functions.
201
202static const uint16_t GPRDecoderTable[] = {
203 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
204 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
205 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
206 ARM::R12, ARM::SP, ARM::LR, ARM::PC
207};
208
210 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
211 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
212 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
213 ARM::R12, 0, ARM::LR, ARM::APSR
214};
215
216static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
217 uint64_t Address,
218 const MCDisassembler *Decoder) {
219 if (RegNo > 15)
221
222 unsigned Register = GPRDecoderTable[RegNo];
225}
226
227static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
228 uint64_t Address,
229 const MCDisassembler *Decoder) {
230 if (RegNo > 15)
232
233 unsigned Register = CLRMGPRDecoderTable[RegNo];
234 if (Register == 0)
236
239}
240
241static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
242 uint64_t Address,
243 const MCDisassembler *Decoder) {
245
246 if (RegNo == 15)
248
249 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
250
251 return S;
252}
253
254static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
255 uint64_t Address,
256 const MCDisassembler *Decoder) {
258
259 if (RegNo == 13)
261
262 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
263
264 return S;
265}
266
267static DecodeStatus
268DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
269 const MCDisassembler *Decoder) {
271
272 if (RegNo == 15)
273 {
274 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
276 }
277
278 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
279 return S;
280}
281
282static DecodeStatus
283DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
284 const MCDisassembler *Decoder) {
286
287 if (RegNo == 15)
288 {
289 Inst.addOperand(MCOperand::createReg(ARM::ZR));
291 }
292
293 if (RegNo == 13)
295
296 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
297 return S;
298}
299
300static DecodeStatus
301DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
302 const MCDisassembler *Decoder) {
304 if (RegNo == 13)
306 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
307 return S;
308}
309
310static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
311 uint64_t Address,
312 const MCDisassembler *Decoder) {
313 if (RegNo > 7)
315 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
316}
317
319 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
320 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
321};
322
323static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
324 uint64_t Address,
325 const MCDisassembler *Decoder) {
327
328 // According to the Arm ARM RegNo = 14 is undefined, but we return fail
329 // rather than SoftFail as there is no GPRPair table entry for index 7.
330 if (RegNo > 13)
332
333 if (RegNo & 1)
335
336 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
337 Inst.addOperand(MCOperand::createReg(RegisterPair));
338 return S;
339}
340
341static DecodeStatus
342DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
343 const MCDisassembler *Decoder) {
344 if (RegNo > 13)
346
347 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
348 Inst.addOperand(MCOperand::createReg(RegisterPair));
349
350 if ((RegNo & 1) || RegNo > 10)
353}
354
355static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
356 uint64_t Address,
357 const MCDisassembler *Decoder) {
358 if (RegNo != 13)
360
361 unsigned Register = GPRDecoderTable[RegNo];
364}
365
366static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
367 uint64_t Address,
368 const MCDisassembler *Decoder) {
369 unsigned Register = 0;
370 switch (RegNo) {
371 case 0:
372 Register = ARM::R0;
373 break;
374 case 1:
375 Register = ARM::R1;
376 break;
377 case 2:
378 Register = ARM::R2;
379 break;
380 case 3:
381 Register = ARM::R3;
382 break;
383 case 9:
384 Register = ARM::R9;
385 break;
386 case 12:
387 Register = ARM::R12;
388 break;
389 default:
391 }
392
395}
396
397static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
398 uint64_t Address,
399 const MCDisassembler *Decoder) {
401
402 const FeatureBitset &featureBits =
403 Decoder->getSubtargetInfo().getFeatureBits();
404
405 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
407
408 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
409 return S;
410}
411
412static const MCPhysReg SPRDecoderTable[] = {
413 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
414 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
415 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
416 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
417 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
418 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
419 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
420 ARM::S28, ARM::S29, ARM::S30, ARM::S31
421};
422
423static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
424 uint64_t Address,
425 const MCDisassembler *Decoder) {
426 if (RegNo > 31)
428
429 unsigned Register = SPRDecoderTable[RegNo];
432}
433
434static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
435 uint64_t Address,
436 const MCDisassembler *Decoder) {
437 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
438}
439
440static const MCPhysReg DPRDecoderTable[] = {
441 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
442 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
443 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
444 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
445 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
446 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
447 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
448 ARM::D28, ARM::D29, ARM::D30, ARM::D31
449};
450
451// Does this instruction/subtarget permit use of registers d16-d31?
452static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder) {
453 if (Inst.getOpcode() == ARM::VSCCLRMD || Inst.getOpcode() == ARM::VSCCLRMS)
454 return true;
455 const FeatureBitset &featureBits =
456 Decoder->getSubtargetInfo().getFeatureBits();
457 return featureBits[ARM::FeatureD32];
458}
459
460static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
461 uint64_t Address,
462 const MCDisassembler *Decoder) {
463 if (RegNo > (PermitsD32(Inst, Decoder) ? 31u : 15u))
465
466 unsigned Register = DPRDecoderTable[RegNo];
469}
470
471static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
472 uint64_t Address,
473 const MCDisassembler *Decoder) {
474 if (RegNo > 7)
476 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
477}
478
479static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
480 uint64_t Address,
481 const MCDisassembler *Decoder) {
482 if (RegNo > 15)
484 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
485}
486
488 uint64_t Address,
489 const MCDisassembler *Decoder) {
490 if (RegNo > 15)
492 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
493}
494
495static const MCPhysReg QPRDecoderTable[] = {
496 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
497 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
498 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
499 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
500};
501
502static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
503 uint64_t Address,
504 const MCDisassembler *Decoder) {
505 if (RegNo > 31 || (RegNo & 1) != 0)
507 RegNo >>= 1;
508
509 unsigned Register = QPRDecoderTable[RegNo];
512}
513
514static const MCPhysReg DPairDecoderTable[] = {
515 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
516 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
517 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
518 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
519 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
520 ARM::Q15
521};
522
523static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
524 uint64_t Address,
525 const MCDisassembler *Decoder) {
526 if (RegNo > 30)
528
529 unsigned Register = DPairDecoderTable[RegNo];
532}
533
535 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
536 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
537 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
538 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
539 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
540 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
541 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
542 ARM::D28_D30, ARM::D29_D31
543};
544
545static DecodeStatus
546DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
547 const MCDisassembler *Decoder) {
548 if (RegNo > 29)
550
551 unsigned Register = DPairSpacedDecoderTable[RegNo];
554}
555
556static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
557 uint64_t Address,
558 const MCDisassembler *Decoder) {
559 if (RegNo > 7)
561
562 unsigned Register = QPRDecoderTable[RegNo];
565}
566
567static const MCPhysReg QQPRDecoderTable[] = {
568 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
569 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
570};
571
572static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
573 uint64_t Address,
574 const MCDisassembler *Decoder) {
575 if (RegNo > 6)
577
578 unsigned Register = QQPRDecoderTable[RegNo];
581}
582
584 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
585 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
586};
587
588static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
589 uint64_t Address,
590 const MCDisassembler *Decoder) {
591 if (RegNo > 4)
593
594 unsigned Register = QQQQPRDecoderTable[RegNo];
597}
598
599// Operand decoding functions.
600
601static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
602 uint64_t Address,
603 const MCDisassembler *Decoder) {
605 if (Val == 0xF) return MCDisassembler::Fail;
606 // AL predicate is not allowed on Thumb1 branches.
607 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
609 const MCInstrInfo *MCII =
610 static_cast<const ARMDisassembler *>(Decoder)->MCII.get();
611 if (Val != ARMCC::AL && !MCII->get(Inst.getOpcode()).isPredicable())
614 if (Val == ARMCC::AL) {
615 Inst.addOperand(MCOperand::createReg(ARM::NoRegister));
616 } else
617 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
618 return S;
619}
620
621static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
622 uint64_t Address,
623 const MCDisassembler *Decoder) {
624 if (Val)
625 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
626 else
627 Inst.addOperand(MCOperand::createReg(ARM::NoRegister));
629}
630
631// This overload is called when decoding `s_cc_out` operand, which is not
632// encoded into instruction. It is only used in Thumb1 instructions.
634 const MCDisassembler *Decoder) {
635 const auto *D = static_cast<const ARMDisassembler *>(Decoder);
636 // Thumb1 instructions define CPSR unless they are inside an IT block.
637 MCRegister CCR = D->ITBlock.instrInITBlock() ? ARM::NoRegister : ARM::CPSR;
640}
641
643 const MCDisassembler *Decoder) {
644 const auto *D = static_cast<const ARMDisassembler *>(Decoder);
645 unsigned VCC = D->VPTBlock.getVPTPred();
646 MCRegister CondReg = VCC == ARMVCC::None ? ARM::NoRegister : ARM::P0;
647
648 Inst.addOperand(MCOperand::createImm(VCC)); // $cond
649 Inst.addOperand(MCOperand::createReg(CondReg)); // $cond_reg
650 Inst.addOperand(MCOperand::createReg(ARM::NoRegister)); // $tp_reg
651
653}
654
656 const MCDisassembler *Decoder) {
657 const auto *D = static_cast<const ARMDisassembler *>(Decoder);
658 unsigned VCC = D->VPTBlock.getVPTPred();
659 MCRegister CondReg = VCC == ARMVCC::None ? ARM::NoRegister : ARM::P0;
660
661 Inst.addOperand(MCOperand::createImm(VCC)); // $cond
662 Inst.addOperand(MCOperand::createReg(CondReg)); // $cond_reg
663 Inst.addOperand(MCOperand::createReg(ARM::NoRegister)); // $tp_reg
664
665 // The last sub-operand ($inactive) is tied to an output operand.
666 // The output operand has already been decoded, so just copy it.
667 const MCInstrDesc &MCID = D->MCII->get(Inst.getOpcode());
668 unsigned InactiveOpIdx = Inst.getNumOperands();
669 int TiedOpIdx = MCID.getOperandConstraint(InactiveOpIdx, MCOI::TIED_TO);
670 assert(TiedOpIdx >= 0 &&
671 "Inactive register in vpred_r is not tied to an output!");
672
673 // Make a copy of the operand to ensure it is not invalidated when MI grows.
674 Inst.addOperand(MCOperand(Inst.getOperand(TiedOpIdx))); // $inactive
675
677}
678
679static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
680 uint64_t Address,
681 const MCDisassembler *Decoder) {
683
684 unsigned Rm = fieldFromInstruction(Val, 0, 4);
685 unsigned type = fieldFromInstruction(Val, 5, 2);
686 unsigned imm = fieldFromInstruction(Val, 7, 5);
687
688 // Register-immediate
689 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
691
693 switch (type) {
694 case 0:
695 Shift = ARM_AM::lsl;
696 break;
697 case 1:
698 Shift = ARM_AM::lsr;
699 break;
700 case 2:
701 Shift = ARM_AM::asr;
702 break;
703 case 3:
704 Shift = ARM_AM::ror;
705 break;
706 }
707
708 if (Shift == ARM_AM::ror && imm == 0)
709 Shift = ARM_AM::rrx;
710
711 unsigned Op = Shift | (imm << 3);
713
714 return S;
715}
716
717static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
718 uint64_t Address,
719 const MCDisassembler *Decoder) {
721
722 unsigned Rm = fieldFromInstruction(Val, 0, 4);
723 unsigned type = fieldFromInstruction(Val, 5, 2);
724 unsigned Rs = fieldFromInstruction(Val, 8, 4);
725
726 // Register-register
727 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
729 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
731
733 switch (type) {
734 case 0:
735 Shift = ARM_AM::lsl;
736 break;
737 case 1:
738 Shift = ARM_AM::lsr;
739 break;
740 case 2:
741 Shift = ARM_AM::asr;
742 break;
743 case 3:
744 Shift = ARM_AM::ror;
745 break;
746 }
747
748 Inst.addOperand(MCOperand::createImm(Shift));
749
750 return S;
751}
752
753static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
754 uint64_t Address,
755 const MCDisassembler *Decoder) {
757
758 bool NeedDisjointWriteback = false;
759 MCRegister WritebackReg;
760 bool CLRM = false;
761 switch (Inst.getOpcode()) {
762 default:
763 break;
764 case ARM::LDMIA_UPD:
765 case ARM::LDMDB_UPD:
766 case ARM::LDMIB_UPD:
767 case ARM::LDMDA_UPD:
768 case ARM::t2LDMIA_UPD:
769 case ARM::t2LDMDB_UPD:
770 case ARM::t2STMIA_UPD:
771 case ARM::t2STMDB_UPD:
772 NeedDisjointWriteback = true;
773 WritebackReg = Inst.getOperand(0).getReg();
774 break;
775 case ARM::t2CLRM:
776 CLRM = true;
777 break;
778 }
779
780 // Empty register lists are not allowed.
781 if (Val == 0) return MCDisassembler::Fail;
782 for (unsigned i = 0; i < 16; ++i) {
783 if (Val & (1 << i)) {
784 if (CLRM) {
785 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
787 }
788 } else {
789 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
791 // Writeback not allowed if Rn is in the target list.
792 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
794 }
795 }
796 }
797
798 return S;
799}
800
801static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
802 uint64_t Address,
803 const MCDisassembler *Decoder) {
805
806 unsigned Vd = fieldFromInstruction(Val, 8, 5);
807 unsigned regs = fieldFromInstruction(Val, 0, 8);
808
809 // In case of unpredictable encoding, tweak the operands.
810 if (regs == 0 || (Vd + regs) > 32) {
811 regs = Vd + regs > 32 ? 32 - Vd : regs;
812 regs = std::max( 1u, regs);
814 }
815
816 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
818 for (unsigned i = 0; i < (regs - 1); ++i) {
819 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
821 }
822
823 return S;
824}
825
826static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
827 uint64_t Address,
828 const MCDisassembler *Decoder) {
830
831 unsigned Vd = fieldFromInstruction(Val, 8, 5);
832 unsigned regs = fieldFromInstruction(Val, 1, 7);
833
834 // In case of unpredictable encoding, tweak the operands.
835 unsigned MaxReg = PermitsD32(Inst, Decoder) ? 32 : 16;
836 if (regs == 0 || (Vd + regs) > MaxReg) {
837 regs = Vd + regs > MaxReg ? MaxReg - Vd : regs;
838 regs = std::max( 1u, regs);
839 regs = std::min(MaxReg, regs);
841 }
842
843 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
845 for (unsigned i = 0; i < (regs - 1); ++i) {
846 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
848 }
849
850 return S;
851}
852
854 uint64_t Address,
855 const MCDisassembler *Decoder) {
856 // This operand encodes a mask of contiguous zeros between a specified MSB
857 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
858 // the mask of all bits LSB-and-lower, and then xor them to create
859 // the mask of that's all ones on [msb, lsb]. Finally we not it to
860 // create the final mask.
861 unsigned msb = fieldFromInstruction(Val, 5, 5);
862 unsigned lsb = fieldFromInstruction(Val, 0, 5);
863
865 if (lsb > msb) {
867 // The check above will cause the warning for the "potentially undefined
868 // instruction encoding" but we can't build a bad MCOperand value here
869 // with a lsb > msb or else printing the MCInst will cause a crash.
870 lsb = msb;
871 }
872
873 uint32_t msb_mask = 0xFFFFFFFF;
874 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
875 uint32_t lsb_mask = (1U << lsb) - 1;
876
877 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
878 return S;
879}
880
881static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
882 uint64_t Address,
883 const MCDisassembler *Decoder) {
885
886 unsigned pred = fieldFromInstruction(Insn, 28, 4);
887 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
888 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
889 unsigned imm = fieldFromInstruction(Insn, 0, 8);
890 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
891 unsigned U = fieldFromInstruction(Insn, 23, 1);
892 const FeatureBitset &featureBits =
893 Decoder->getSubtargetInfo().getFeatureBits();
894
895 switch (Inst.getOpcode()) {
896 case ARM::LDC_OFFSET:
897 case ARM::LDC_PRE:
898 case ARM::LDC_POST:
899 case ARM::LDC_OPTION:
900 case ARM::LDCL_OFFSET:
901 case ARM::LDCL_PRE:
902 case ARM::LDCL_POST:
903 case ARM::LDCL_OPTION:
904 case ARM::STC_OFFSET:
905 case ARM::STC_PRE:
906 case ARM::STC_POST:
907 case ARM::STC_OPTION:
908 case ARM::STCL_OFFSET:
909 case ARM::STCL_PRE:
910 case ARM::STCL_POST:
911 case ARM::STCL_OPTION:
912 case ARM::t2LDC_OFFSET:
913 case ARM::t2LDC_PRE:
914 case ARM::t2LDC_POST:
915 case ARM::t2LDC_OPTION:
916 case ARM::t2LDCL_OFFSET:
917 case ARM::t2LDCL_PRE:
918 case ARM::t2LDCL_POST:
919 case ARM::t2LDCL_OPTION:
920 case ARM::t2STC_OFFSET:
921 case ARM::t2STC_PRE:
922 case ARM::t2STC_POST:
923 case ARM::t2STC_OPTION:
924 case ARM::t2STCL_OFFSET:
925 case ARM::t2STCL_PRE:
926 case ARM::t2STCL_POST:
927 case ARM::t2STCL_OPTION:
928 case ARM::t2LDC2_OFFSET:
929 case ARM::t2LDC2L_OFFSET:
930 case ARM::t2LDC2_PRE:
931 case ARM::t2LDC2L_PRE:
932 case ARM::t2STC2_OFFSET:
933 case ARM::t2STC2L_OFFSET:
934 case ARM::t2STC2_PRE:
935 case ARM::t2STC2L_PRE:
936 case ARM::LDC2_OFFSET:
937 case ARM::LDC2L_OFFSET:
938 case ARM::LDC2_PRE:
939 case ARM::LDC2L_PRE:
940 case ARM::STC2_OFFSET:
941 case ARM::STC2L_OFFSET:
942 case ARM::STC2_PRE:
943 case ARM::STC2L_PRE:
944 case ARM::t2LDC2_OPTION:
945 case ARM::t2STC2_OPTION:
946 case ARM::t2LDC2_POST:
947 case ARM::t2LDC2L_POST:
948 case ARM::t2STC2_POST:
949 case ARM::t2STC2L_POST:
950 case ARM::LDC2_POST:
951 case ARM::LDC2L_POST:
952 case ARM::STC2_POST:
953 case ARM::STC2L_POST:
954 if (coproc == 0xA || coproc == 0xB ||
955 (featureBits[ARM::HasV8_1MMainlineOps] &&
956 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
957 coproc == 0xE || coproc == 0xF)))
959 break;
960 default:
961 break;
962 }
963
964 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
966
967 Inst.addOperand(MCOperand::createImm(coproc));
969 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
971
972 switch (Inst.getOpcode()) {
973 case ARM::t2LDC2_OFFSET:
974 case ARM::t2LDC2L_OFFSET:
975 case ARM::t2LDC2_PRE:
976 case ARM::t2LDC2L_PRE:
977 case ARM::t2STC2_OFFSET:
978 case ARM::t2STC2L_OFFSET:
979 case ARM::t2STC2_PRE:
980 case ARM::t2STC2L_PRE:
981 case ARM::LDC2_OFFSET:
982 case ARM::LDC2L_OFFSET:
983 case ARM::LDC2_PRE:
984 case ARM::LDC2L_PRE:
985 case ARM::STC2_OFFSET:
986 case ARM::STC2L_OFFSET:
987 case ARM::STC2_PRE:
988 case ARM::STC2L_PRE:
989 case ARM::t2LDC_OFFSET:
990 case ARM::t2LDCL_OFFSET:
991 case ARM::t2LDC_PRE:
992 case ARM::t2LDCL_PRE:
993 case ARM::t2STC_OFFSET:
994 case ARM::t2STCL_OFFSET:
995 case ARM::t2STC_PRE:
996 case ARM::t2STCL_PRE:
997 case ARM::LDC_OFFSET:
998 case ARM::LDCL_OFFSET:
999 case ARM::LDC_PRE:
1000 case ARM::LDCL_PRE:
1001 case ARM::STC_OFFSET:
1002 case ARM::STCL_OFFSET:
1003 case ARM::STC_PRE:
1004 case ARM::STCL_PRE:
1005 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1007 break;
1008 case ARM::t2LDC2_POST:
1009 case ARM::t2LDC2L_POST:
1010 case ARM::t2STC2_POST:
1011 case ARM::t2STC2L_POST:
1012 case ARM::LDC2_POST:
1013 case ARM::LDC2L_POST:
1014 case ARM::STC2_POST:
1015 case ARM::STC2L_POST:
1016 case ARM::t2LDC_POST:
1017 case ARM::t2LDCL_POST:
1018 case ARM::t2STC_POST:
1019 case ARM::t2STCL_POST:
1020 case ARM::LDC_POST:
1021 case ARM::LDCL_POST:
1022 case ARM::STC_POST:
1023 case ARM::STCL_POST:
1024 imm |= U << 8;
1025 [[fallthrough]];
1026 default:
1027 // The 'option' variant doesn't encode 'U' in the immediate since
1028 // the immediate is unsigned [0,255].
1030 break;
1031 }
1032
1033 switch (Inst.getOpcode()) {
1034 case ARM::LDC_OFFSET:
1035 case ARM::LDC_PRE:
1036 case ARM::LDC_POST:
1037 case ARM::LDC_OPTION:
1038 case ARM::LDCL_OFFSET:
1039 case ARM::LDCL_PRE:
1040 case ARM::LDCL_POST:
1041 case ARM::LDCL_OPTION:
1042 case ARM::STC_OFFSET:
1043 case ARM::STC_PRE:
1044 case ARM::STC_POST:
1045 case ARM::STC_OPTION:
1046 case ARM::STCL_OFFSET:
1047 case ARM::STCL_PRE:
1048 case ARM::STCL_POST:
1049 case ARM::STCL_OPTION:
1050 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1051 return MCDisassembler::Fail;
1052 break;
1053 default:
1054 break;
1055 }
1056
1057 return S;
1058}
1059
1060static DecodeStatus
1061DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
1062 const MCDisassembler *Decoder) {
1064
1065 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1066 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1067 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1068 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1069 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1070 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1071 unsigned P = fieldFromInstruction(Insn, 24, 1);
1072 unsigned W = fieldFromInstruction(Insn, 21, 1);
1073
1074 // On stores, the writeback operand precedes Rt.
1075 switch (Inst.getOpcode()) {
1076 case ARM::STR_POST_IMM:
1077 case ARM::STR_POST_REG:
1078 case ARM::STRB_POST_IMM:
1079 case ARM::STRB_POST_REG:
1080 case ARM::STRT_POST_REG:
1081 case ARM::STRT_POST_IMM:
1082 case ARM::STRBT_POST_REG:
1083 case ARM::STRBT_POST_IMM:
1084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1085 return MCDisassembler::Fail;
1086 break;
1087 default:
1088 break;
1089 }
1090
1091 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1092 return MCDisassembler::Fail;
1093
1094 // On loads, the writeback operand comes after Rt.
1095 switch (Inst.getOpcode()) {
1096 case ARM::LDR_POST_IMM:
1097 case ARM::LDR_POST_REG:
1098 case ARM::LDRB_POST_IMM:
1099 case ARM::LDRB_POST_REG:
1100 case ARM::LDRBT_POST_REG:
1101 case ARM::LDRBT_POST_IMM:
1102 case ARM::LDRT_POST_REG:
1103 case ARM::LDRT_POST_IMM:
1104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1105 return MCDisassembler::Fail;
1106 break;
1107 default:
1108 break;
1109 }
1110
1111 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1112 return MCDisassembler::Fail;
1113
1115 if (!fieldFromInstruction(Insn, 23, 1))
1116 Op = ARM_AM::sub;
1117
1118 bool writeback = (P == 0) || (W == 1);
1119 unsigned idx_mode = 0;
1120 if (P && writeback)
1121 idx_mode = ARMII::IndexModePre;
1122 else if (!P && writeback)
1123 idx_mode = ARMII::IndexModePost;
1124
1125 if (writeback && (Rn == 15 || Rn == Rt))
1126 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1127
1128 if (reg) {
1129 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1130 return MCDisassembler::Fail;
1132 switch( fieldFromInstruction(Insn, 5, 2)) {
1133 case 0:
1134 Opc = ARM_AM::lsl;
1135 break;
1136 case 1:
1137 Opc = ARM_AM::lsr;
1138 break;
1139 case 2:
1140 Opc = ARM_AM::asr;
1141 break;
1142 case 3:
1143 Opc = ARM_AM::ror;
1144 break;
1145 default:
1146 return MCDisassembler::Fail;
1147 }
1148 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1149 if (Opc == ARM_AM::ror && amt == 0)
1150 Opc = ARM_AM::rrx;
1151 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1152
1154 } else {
1156 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1158 }
1159
1160 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1161 return MCDisassembler::Fail;
1162
1163 return S;
1164}
1165
1166static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1167 uint64_t Address,
1168 const MCDisassembler *Decoder) {
1170
1171 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1172 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1173 unsigned type = fieldFromInstruction(Val, 5, 2);
1174 unsigned imm = fieldFromInstruction(Val, 7, 5);
1175 unsigned U = fieldFromInstruction(Val, 12, 1);
1176
1178 switch (type) {
1179 case 0:
1180 ShOp = ARM_AM::lsl;
1181 break;
1182 case 1:
1183 ShOp = ARM_AM::lsr;
1184 break;
1185 case 2:
1186 ShOp = ARM_AM::asr;
1187 break;
1188 case 3:
1189 ShOp = ARM_AM::ror;
1190 break;
1191 }
1192
1193 if (ShOp == ARM_AM::ror && imm == 0)
1194 ShOp = ARM_AM::rrx;
1195
1196 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1197 return MCDisassembler::Fail;
1198 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1199 return MCDisassembler::Fail;
1200 unsigned shift;
1201 if (U)
1202 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1203 else
1204 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1205 Inst.addOperand(MCOperand::createImm(shift));
1206
1207 return S;
1208}
1209
1210static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
1211 uint64_t Address,
1212 const MCDisassembler *Decoder) {
1213 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB)
1214 return MCDisassembler::Fail;
1215
1216 // The "csync" operand is not encoded into the "tsb" instruction (as this is
1217 // the only available operand), but LLVM expects the instruction to have one
1218 // operand, so we need to add the csync when decoding.
1221}
1222
1224 uint64_t Address,
1225 const MCDisassembler *Decoder) {
1227
1228 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1229 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1230 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1231 unsigned type = fieldFromInstruction(Insn, 22, 1);
1232 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1233 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1234 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1235 unsigned W = fieldFromInstruction(Insn, 21, 1);
1236 unsigned P = fieldFromInstruction(Insn, 24, 1);
1237 unsigned Rt2 = Rt + 1;
1238
1239 bool writeback = (W == 1) | (P == 0);
1240
1241 // For {LD,ST}RD, Rt must be even, else undefined.
1242 switch (Inst.getOpcode()) {
1243 case ARM::STRD:
1244 case ARM::STRD_PRE:
1245 case ARM::STRD_POST:
1246 case ARM::LDRD:
1247 case ARM::LDRD_PRE:
1248 case ARM::LDRD_POST:
1249 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1250 break;
1251 default:
1252 break;
1253 }
1254 switch (Inst.getOpcode()) {
1255 case ARM::STRD:
1256 case ARM::STRD_PRE:
1257 case ARM::STRD_POST:
1258 if (P == 0 && W == 1)
1260
1261 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1263 if (type && Rm == 15)
1265 if (Rt2 == 15)
1267 if (!type && fieldFromInstruction(Insn, 8, 4))
1269 break;
1270 case ARM::STRH:
1271 case ARM::STRH_PRE:
1272 case ARM::STRH_POST:
1273 if (Rt == 15)
1275 if (writeback && (Rn == 15 || Rn == Rt))
1277 if (!type && Rm == 15)
1279 break;
1280 case ARM::LDRD:
1281 case ARM::LDRD_PRE:
1282 case ARM::LDRD_POST:
1283 if (type && Rn == 15) {
1284 if (Rt2 == 15)
1286 break;
1287 }
1288 if (P == 0 && W == 1)
1290 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1292 if (!type && writeback && Rn == 15)
1294 if (writeback && (Rn == Rt || Rn == Rt2))
1296 break;
1297 case ARM::LDRH:
1298 case ARM::LDRH_PRE:
1299 case ARM::LDRH_POST:
1300 if (type && Rn == 15) {
1301 if (Rt == 15)
1303 break;
1304 }
1305 if (Rt == 15)
1307 if (!type && Rm == 15)
1309 if (!type && writeback && (Rn == 15 || Rn == Rt))
1311 break;
1312 case ARM::LDRSH:
1313 case ARM::LDRSH_PRE:
1314 case ARM::LDRSH_POST:
1315 case ARM::LDRSB:
1316 case ARM::LDRSB_PRE:
1317 case ARM::LDRSB_POST:
1318 if (type && Rn == 15) {
1319 if (Rt == 15)
1321 break;
1322 }
1323 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1325 if (!type && (Rt == 15 || Rm == 15))
1327 if (!type && writeback && (Rn == 15 || Rn == Rt))
1329 break;
1330 default:
1331 break;
1332 }
1333
1334 if (writeback) { // Writeback
1335 if (P)
1336 U |= ARMII::IndexModePre << 9;
1337 else
1338 U |= ARMII::IndexModePost << 9;
1339
1340 // On stores, the writeback operand precedes Rt.
1341 switch (Inst.getOpcode()) {
1342 case ARM::STRD:
1343 case ARM::STRD_PRE:
1344 case ARM::STRD_POST:
1345 case ARM::STRH:
1346 case ARM::STRH_PRE:
1347 case ARM::STRH_POST:
1348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1349 return MCDisassembler::Fail;
1350 break;
1351 default:
1352 break;
1353 }
1354 }
1355
1356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1357 return MCDisassembler::Fail;
1358 switch (Inst.getOpcode()) {
1359 case ARM::STRD:
1360 case ARM::STRD_PRE:
1361 case ARM::STRD_POST:
1362 case ARM::LDRD:
1363 case ARM::LDRD_PRE:
1364 case ARM::LDRD_POST:
1365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1366 return MCDisassembler::Fail;
1367 break;
1368 default:
1369 break;
1370 }
1371
1372 if (writeback) {
1373 // On loads, the writeback operand comes after Rt.
1374 switch (Inst.getOpcode()) {
1375 case ARM::LDRD:
1376 case ARM::LDRD_PRE:
1377 case ARM::LDRD_POST:
1378 case ARM::LDRH:
1379 case ARM::LDRH_PRE:
1380 case ARM::LDRH_POST:
1381 case ARM::LDRSH:
1382 case ARM::LDRSH_PRE:
1383 case ARM::LDRSH_POST:
1384 case ARM::LDRSB:
1385 case ARM::LDRSB_PRE:
1386 case ARM::LDRSB_POST:
1387 case ARM::LDRHTr:
1388 case ARM::LDRSBTr:
1389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1390 return MCDisassembler::Fail;
1391 break;
1392 default:
1393 break;
1394 }
1395 }
1396
1397 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1398 return MCDisassembler::Fail;
1399
1400 if (type) {
1402 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1403 } else {
1404 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1405 return MCDisassembler::Fail;
1407 }
1408
1409 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1410 return MCDisassembler::Fail;
1411
1412 return S;
1413}
1414
1415static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1416 uint64_t Address,
1417 const MCDisassembler *Decoder) {
1419
1420 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1421 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1422 return MCDisassembler::Fail;
1423
1424 return S;
1425}
1426
1427static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1428 uint64_t Address,
1429 const MCDisassembler *Decoder) {
1430 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1431 unsigned M = fieldFromInstruction(Insn, 17, 1);
1432 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1433 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1434
1436
1437 // This decoder is called from multiple location that do not check
1438 // the full encoding is valid before they do.
1439 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1440 fieldFromInstruction(Insn, 16, 1) != 0 ||
1441 fieldFromInstruction(Insn, 20, 8) != 0x10)
1442 return MCDisassembler::Fail;
1443
1444 // imod == '01' --> UNPREDICTABLE
1445 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1446 // return failure here. The '01' imod value is unprintable, so there's
1447 // nothing useful we could do even if we returned UNPREDICTABLE.
1448
1449 if (imod == 1) return MCDisassembler::Fail;
1450
1451 if (imod && M) {
1452 Inst.setOpcode(ARM::CPS3p);
1453 Inst.addOperand(MCOperand::createImm(imod));
1454 Inst.addOperand(MCOperand::createImm(iflags));
1456 } else if (imod && !M) {
1457 Inst.setOpcode(ARM::CPS2p);
1458 Inst.addOperand(MCOperand::createImm(imod));
1459 Inst.addOperand(MCOperand::createImm(iflags));
1461 } else if (!imod && M) {
1462 Inst.setOpcode(ARM::CPS1p);
1464 if (iflags) S = MCDisassembler::SoftFail;
1465 } else {
1466 // imod == '00' && M == '0' --> UNPREDICTABLE
1467 Inst.setOpcode(ARM::CPS1p);
1470 }
1471
1472 return S;
1473}
1474
1475static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1476 uint64_t Address,
1477 const MCDisassembler *Decoder) {
1479
1480 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1481 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1482 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1483 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1484
1485 if (pred == 0xF)
1486 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1487
1488 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1489 return MCDisassembler::Fail;
1490 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1491 return MCDisassembler::Fail;
1492 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1493 return MCDisassembler::Fail;
1494 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1495 return MCDisassembler::Fail;
1496 return S;
1497}
1498
1499static DecodeStatus
1501 uint64_t Address,
1502 const MCDisassembler *Decoder) {
1504
1505 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1506 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1507 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1508
1509 if (pred == 0xF) {
1510 // Ambiguous with RFE and SRS
1511 switch (Inst.getOpcode()) {
1512 case ARM::LDMDA:
1513 Inst.setOpcode(ARM::RFEDA);
1514 break;
1515 case ARM::LDMDA_UPD:
1516 Inst.setOpcode(ARM::RFEDA_UPD);
1517 break;
1518 case ARM::LDMDB:
1519 Inst.setOpcode(ARM::RFEDB);
1520 break;
1521 case ARM::LDMDB_UPD:
1522 Inst.setOpcode(ARM::RFEDB_UPD);
1523 break;
1524 case ARM::LDMIA:
1525 Inst.setOpcode(ARM::RFEIA);
1526 break;
1527 case ARM::LDMIA_UPD:
1528 Inst.setOpcode(ARM::RFEIA_UPD);
1529 break;
1530 case ARM::LDMIB:
1531 Inst.setOpcode(ARM::RFEIB);
1532 break;
1533 case ARM::LDMIB_UPD:
1534 Inst.setOpcode(ARM::RFEIB_UPD);
1535 break;
1536 case ARM::STMDA:
1537 Inst.setOpcode(ARM::SRSDA);
1538 break;
1539 case ARM::STMDA_UPD:
1540 Inst.setOpcode(ARM::SRSDA_UPD);
1541 break;
1542 case ARM::STMDB:
1543 Inst.setOpcode(ARM::SRSDB);
1544 break;
1545 case ARM::STMDB_UPD:
1546 Inst.setOpcode(ARM::SRSDB_UPD);
1547 break;
1548 case ARM::STMIA:
1549 Inst.setOpcode(ARM::SRSIA);
1550 break;
1551 case ARM::STMIA_UPD:
1552 Inst.setOpcode(ARM::SRSIA_UPD);
1553 break;
1554 case ARM::STMIB:
1555 Inst.setOpcode(ARM::SRSIB);
1556 break;
1557 case ARM::STMIB_UPD:
1558 Inst.setOpcode(ARM::SRSIB_UPD);
1559 break;
1560 default:
1561 return MCDisassembler::Fail;
1562 }
1563
1564 // For stores (which become SRS's, the only operand is the mode.
1565 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1566 // Check SRS encoding constraints
1567 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1568 fieldFromInstruction(Insn, 20, 1) == 0))
1569 return MCDisassembler::Fail;
1570
1571 Inst.addOperand(
1573 return S;
1574 }
1575
1576 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1577 }
1578
1579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1580 return MCDisassembler::Fail;
1581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1582 return MCDisassembler::Fail; // Tied
1583 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1584 return MCDisassembler::Fail;
1585 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1586 return MCDisassembler::Fail;
1587
1588 return S;
1589}
1590
1591// Check for UNPREDICTABLE predicated ESB instruction
1592static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
1593 uint64_t Address,
1594 const MCDisassembler *Decoder) {
1595 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1596 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1597 const FeatureBitset &FeatureBits =
1598 Decoder->getSubtargetInfo().getFeatureBits();
1599
1601
1602 Inst.addOperand(MCOperand::createImm(imm8));
1603
1604 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1605 return MCDisassembler::Fail;
1606
1607 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
1608 // so all predicates should be allowed.
1609 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1611
1612 return S;
1613}
1614
1615static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1616 uint64_t Address,
1617 const MCDisassembler *Decoder) {
1618 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1619 unsigned M = fieldFromInstruction(Insn, 8, 1);
1620 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1621 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1622
1624
1625 // imod == '01' --> UNPREDICTABLE
1626 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1627 // return failure here. The '01' imod value is unprintable, so there's
1628 // nothing useful we could do even if we returned UNPREDICTABLE.
1629
1630 if (imod == 1) return MCDisassembler::Fail;
1631
1632 if (imod && M) {
1633 Inst.setOpcode(ARM::t2CPS3p);
1634 Inst.addOperand(MCOperand::createImm(imod));
1635 Inst.addOperand(MCOperand::createImm(iflags));
1637 } else if (imod && !M) {
1638 Inst.setOpcode(ARM::t2CPS2p);
1639 Inst.addOperand(MCOperand::createImm(imod));
1640 Inst.addOperand(MCOperand::createImm(iflags));
1642 } else if (!imod && M) {
1643 Inst.setOpcode(ARM::t2CPS1p);
1645 if (iflags) S = MCDisassembler::SoftFail;
1646 } else {
1647 // imod == '00' && M == '0' --> this is a HINT instruction
1648 int imm = fieldFromInstruction(Insn, 0, 8);
1649 // HINT are defined only for immediate in [0..4]
1650 if(imm > 4) return MCDisassembler::Fail;
1651 Inst.setOpcode(ARM::t2HINT);
1653 }
1654
1655 return S;
1656}
1657
1658static DecodeStatus
1659DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
1660 const MCDisassembler *Decoder) {
1661 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1662
1663 unsigned Opcode = ARM::t2HINT;
1664
1665 if (imm == 0x0D) {
1666 Opcode = ARM::t2PACBTI;
1667 } else if (imm == 0x1D) {
1668 Opcode = ARM::t2PAC;
1669 } else if (imm == 0x2D) {
1670 Opcode = ARM::t2AUT;
1671 } else if (imm == 0x0F) {
1672 Opcode = ARM::t2BTI;
1673 }
1674
1675 Inst.setOpcode(Opcode);
1676 if (Opcode == ARM::t2HINT) {
1678 }
1679
1681}
1682
1684 uint64_t Address,
1685 const MCDisassembler *Decoder) {
1687
1688 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
1689 unsigned imm = 0;
1690
1691 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
1692 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
1693 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1694 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
1695
1696 if (Inst.getOpcode() == ARM::t2MOVTi16)
1697 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1698 return MCDisassembler::Fail;
1699 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1700 return MCDisassembler::Fail;
1701
1702 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1704
1705 return S;
1706}
1707
1709 uint64_t Address,
1710 const MCDisassembler *Decoder) {
1712
1713 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1714 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1715 unsigned imm = 0;
1716
1717 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
1718 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1719
1720 if (Inst.getOpcode() == ARM::MOVTi16)
1721 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1722 return MCDisassembler::Fail;
1723
1724 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1725 return MCDisassembler::Fail;
1726
1727 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1729
1730 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1731 return MCDisassembler::Fail;
1732
1733 return S;
1734}
1735
1736static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
1737 uint64_t Address,
1738 const MCDisassembler *Decoder) {
1740
1741 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
1742 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
1743 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
1744 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
1745 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1746
1747 if (pred == 0xF)
1748 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1749
1750 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1751 return MCDisassembler::Fail;
1752 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1753 return MCDisassembler::Fail;
1754 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1755 return MCDisassembler::Fail;
1756 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1757 return MCDisassembler::Fail;
1758
1759 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1760 return MCDisassembler::Fail;
1761
1762 return S;
1763}
1764
1765static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
1766 uint64_t Address,
1767 const MCDisassembler *Decoder) {
1769
1770 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
1771
1772 const FeatureBitset &FeatureBits =
1773 Decoder->getSubtargetInfo().getFeatureBits();
1774
1775 if (!FeatureBits[ARM::HasV8_1aOps] ||
1776 !FeatureBits[ARM::HasV8Ops])
1777 return MCDisassembler::Fail;
1778
1779 // Decoder can be called from DecodeTST, which does not check the full
1780 // encoding is valid.
1781 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
1782 fieldFromInstruction(Insn, 4,4) != 0)
1783 return MCDisassembler::Fail;
1784 if (fieldFromInstruction(Insn, 10,10) != 0 ||
1785 fieldFromInstruction(Insn, 0,4) != 0)
1787
1788 Inst.setOpcode(ARM::SETPAN);
1790
1791 return S;
1792}
1793
1794static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
1795 uint64_t Address,
1796 const MCDisassembler *Decoder) {
1798
1799 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
1800 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1801 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1802
1803 if (Pred == 0xF)
1804 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
1805
1806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1807 return MCDisassembler::Fail;
1808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1809 return MCDisassembler::Fail;
1810 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
1811 return MCDisassembler::Fail;
1812
1813 return S;
1814}
1815
1817 uint64_t Address,
1818 const MCDisassembler *Decoder) {
1820
1821 unsigned add = fieldFromInstruction(Val, 12, 1);
1822 unsigned imm = fieldFromInstruction(Val, 0, 12);
1823 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1824
1825 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1826 return MCDisassembler::Fail;
1827
1828 if (!add) imm *= -1;
1829 if (imm == 0 && !add) imm = INT32_MIN;
1831 if (Rn == 15)
1832 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
1833
1834 return S;
1835}
1836
1837static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
1838 uint64_t Address,
1839 const MCDisassembler *Decoder) {
1841
1842 unsigned Rn = fieldFromInstruction(Val, 9, 4);
1843 // U == 1 to add imm, 0 to subtract it.
1844 unsigned U = fieldFromInstruction(Val, 8, 1);
1845 unsigned imm = fieldFromInstruction(Val, 0, 8);
1846
1847 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1848 return MCDisassembler::Fail;
1849
1850 if (U)
1852 else
1854
1855 return S;
1856}
1857
1859 uint64_t Address,
1860 const MCDisassembler *Decoder) {
1862
1863 unsigned Rn = fieldFromInstruction(Val, 9, 4);
1864 // U == 1 to add imm, 0 to subtract it.
1865 unsigned U = fieldFromInstruction(Val, 8, 1);
1866 unsigned imm = fieldFromInstruction(Val, 0, 8);
1867
1868 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1869 return MCDisassembler::Fail;
1870
1871 if (U)
1873 else
1875
1876 return S;
1877}
1878
1879static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
1880 uint64_t Address,
1881 const MCDisassembler *Decoder) {
1882 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1883}
1884
1885static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
1886 uint64_t Address,
1887 const MCDisassembler *Decoder) {
1889
1890 // Note the J1 and J2 values are from the encoded instruction. So here
1891 // change them to I1 and I2 values via as documented:
1892 // I1 = NOT(J1 EOR S);
1893 // I2 = NOT(J2 EOR S);
1894 // and build the imm32 with one trailing zero as documented:
1895 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
1896 unsigned S = fieldFromInstruction(Insn, 26, 1);
1897 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
1898 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
1899 unsigned I1 = !(J1 ^ S);
1900 unsigned I2 = !(J2 ^ S);
1901 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
1902 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
1903 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
1904 int imm32 = SignExtend32<25>(tmp << 1);
1905 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
1906 true, 4, Inst, Decoder))
1907 Inst.addOperand(MCOperand::createImm(imm32));
1908
1909 return Status;
1910}
1911
1913 uint64_t Address,
1914 const MCDisassembler *Decoder) {
1916
1917 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1918 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
1919
1920 if (pred == 0xF) {
1921 Inst.setOpcode(ARM::BLXi);
1922 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
1923 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
1924 true, 4, Inst, Decoder))
1926 return S;
1927 }
1928
1929 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
1930 true, 4, Inst, Decoder))
1932
1933 // We already have BL_pred for BL w/ predicate, no need to add addition
1934 // predicate opreands for BL
1935 if (Inst.getOpcode() != ARM::BL)
1936 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1937 return MCDisassembler::Fail;
1938
1939 return S;
1940}
1941
1942static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
1943 uint64_t Address,
1944 const MCDisassembler *Decoder) {
1946
1947 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1948 unsigned align = fieldFromInstruction(Val, 4, 2);
1949
1950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1951 return MCDisassembler::Fail;
1952 if (!align)
1954 else
1955 Inst.addOperand(MCOperand::createImm(4 << align));
1956
1957 return S;
1958}
1959
1960static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
1961 uint64_t Address,
1962 const MCDisassembler *Decoder) {
1964
1965 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1966 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
1967 unsigned wb = fieldFromInstruction(Insn, 16, 4);
1968 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1969 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
1970 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1971
1972 // First output register
1973 switch (Inst.getOpcode()) {
1974 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
1975 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
1976 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
1977 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
1978 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
1979 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
1980 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
1981 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
1982 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
1983 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
1984 return MCDisassembler::Fail;
1985 break;
1986 case ARM::VLD2b16:
1987 case ARM::VLD2b32:
1988 case ARM::VLD2b8:
1989 case ARM::VLD2b16wb_fixed:
1990 case ARM::VLD2b16wb_register:
1991 case ARM::VLD2b32wb_fixed:
1992 case ARM::VLD2b32wb_register:
1993 case ARM::VLD2b8wb_fixed:
1994 case ARM::VLD2b8wb_register:
1995 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
1996 return MCDisassembler::Fail;
1997 break;
1998 default:
1999 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2000 return MCDisassembler::Fail;
2001 }
2002
2003 // Second output register
2004 switch (Inst.getOpcode()) {
2005 case ARM::VLD3d8:
2006 case ARM::VLD3d16:
2007 case ARM::VLD3d32:
2008 case ARM::VLD3d8_UPD:
2009 case ARM::VLD3d16_UPD:
2010 case ARM::VLD3d32_UPD:
2011 case ARM::VLD4d8:
2012 case ARM::VLD4d16:
2013 case ARM::VLD4d32:
2014 case ARM::VLD4d8_UPD:
2015 case ARM::VLD4d16_UPD:
2016 case ARM::VLD4d32_UPD:
2017 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2018 return MCDisassembler::Fail;
2019 break;
2020 case ARM::VLD3q8:
2021 case ARM::VLD3q16:
2022 case ARM::VLD3q32:
2023 case ARM::VLD3q8_UPD:
2024 case ARM::VLD3q16_UPD:
2025 case ARM::VLD3q32_UPD:
2026 case ARM::VLD4q8:
2027 case ARM::VLD4q16:
2028 case ARM::VLD4q32:
2029 case ARM::VLD4q8_UPD:
2030 case ARM::VLD4q16_UPD:
2031 case ARM::VLD4q32_UPD:
2032 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2033 return MCDisassembler::Fail;
2034 break;
2035 default:
2036 break;
2037 }
2038
2039 // Third output register
2040 switch(Inst.getOpcode()) {
2041 case ARM::VLD3d8:
2042 case ARM::VLD3d16:
2043 case ARM::VLD3d32:
2044 case ARM::VLD3d8_UPD:
2045 case ARM::VLD3d16_UPD:
2046 case ARM::VLD3d32_UPD:
2047 case ARM::VLD4d8:
2048 case ARM::VLD4d16:
2049 case ARM::VLD4d32:
2050 case ARM::VLD4d8_UPD:
2051 case ARM::VLD4d16_UPD:
2052 case ARM::VLD4d32_UPD:
2053 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2054 return MCDisassembler::Fail;
2055 break;
2056 case ARM::VLD3q8:
2057 case ARM::VLD3q16:
2058 case ARM::VLD3q32:
2059 case ARM::VLD3q8_UPD:
2060 case ARM::VLD3q16_UPD:
2061 case ARM::VLD3q32_UPD:
2062 case ARM::VLD4q8:
2063 case ARM::VLD4q16:
2064 case ARM::VLD4q32:
2065 case ARM::VLD4q8_UPD:
2066 case ARM::VLD4q16_UPD:
2067 case ARM::VLD4q32_UPD:
2068 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2069 return MCDisassembler::Fail;
2070 break;
2071 default:
2072 break;
2073 }
2074
2075 // Fourth output register
2076 switch (Inst.getOpcode()) {
2077 case ARM::VLD4d8:
2078 case ARM::VLD4d16:
2079 case ARM::VLD4d32:
2080 case ARM::VLD4d8_UPD:
2081 case ARM::VLD4d16_UPD:
2082 case ARM::VLD4d32_UPD:
2083 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2084 return MCDisassembler::Fail;
2085 break;
2086 case ARM::VLD4q8:
2087 case ARM::VLD4q16:
2088 case ARM::VLD4q32:
2089 case ARM::VLD4q8_UPD:
2090 case ARM::VLD4q16_UPD:
2091 case ARM::VLD4q32_UPD:
2092 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2093 return MCDisassembler::Fail;
2094 break;
2095 default:
2096 break;
2097 }
2098
2099 // Writeback operand
2100 switch (Inst.getOpcode()) {
2101 case ARM::VLD1d8wb_fixed:
2102 case ARM::VLD1d16wb_fixed:
2103 case ARM::VLD1d32wb_fixed:
2104 case ARM::VLD1d64wb_fixed:
2105 case ARM::VLD1d8wb_register:
2106 case ARM::VLD1d16wb_register:
2107 case ARM::VLD1d32wb_register:
2108 case ARM::VLD1d64wb_register:
2109 case ARM::VLD1q8wb_fixed:
2110 case ARM::VLD1q16wb_fixed:
2111 case ARM::VLD1q32wb_fixed:
2112 case ARM::VLD1q64wb_fixed:
2113 case ARM::VLD1q8wb_register:
2114 case ARM::VLD1q16wb_register:
2115 case ARM::VLD1q32wb_register:
2116 case ARM::VLD1q64wb_register:
2117 case ARM::VLD1d8Twb_fixed:
2118 case ARM::VLD1d8Twb_register:
2119 case ARM::VLD1d16Twb_fixed:
2120 case ARM::VLD1d16Twb_register:
2121 case ARM::VLD1d32Twb_fixed:
2122 case ARM::VLD1d32Twb_register:
2123 case ARM::VLD1d64Twb_fixed:
2124 case ARM::VLD1d64Twb_register:
2125 case ARM::VLD1d8Qwb_fixed:
2126 case ARM::VLD1d8Qwb_register:
2127 case ARM::VLD1d16Qwb_fixed:
2128 case ARM::VLD1d16Qwb_register:
2129 case ARM::VLD1d32Qwb_fixed:
2130 case ARM::VLD1d32Qwb_register:
2131 case ARM::VLD1d64Qwb_fixed:
2132 case ARM::VLD1d64Qwb_register:
2133 case ARM::VLD2d8wb_fixed:
2134 case ARM::VLD2d16wb_fixed:
2135 case ARM::VLD2d32wb_fixed:
2136 case ARM::VLD2q8wb_fixed:
2137 case ARM::VLD2q16wb_fixed:
2138 case ARM::VLD2q32wb_fixed:
2139 case ARM::VLD2d8wb_register:
2140 case ARM::VLD2d16wb_register:
2141 case ARM::VLD2d32wb_register:
2142 case ARM::VLD2q8wb_register:
2143 case ARM::VLD2q16wb_register:
2144 case ARM::VLD2q32wb_register:
2145 case ARM::VLD2b8wb_fixed:
2146 case ARM::VLD2b16wb_fixed:
2147 case ARM::VLD2b32wb_fixed:
2148 case ARM::VLD2b8wb_register:
2149 case ARM::VLD2b16wb_register:
2150 case ARM::VLD2b32wb_register:
2152 break;
2153 case ARM::VLD3d8_UPD:
2154 case ARM::VLD3d16_UPD:
2155 case ARM::VLD3d32_UPD:
2156 case ARM::VLD3q8_UPD:
2157 case ARM::VLD3q16_UPD:
2158 case ARM::VLD3q32_UPD:
2159 case ARM::VLD4d8_UPD:
2160 case ARM::VLD4d16_UPD:
2161 case ARM::VLD4d32_UPD:
2162 case ARM::VLD4q8_UPD:
2163 case ARM::VLD4q16_UPD:
2164 case ARM::VLD4q32_UPD:
2165 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2166 return MCDisassembler::Fail;
2167 break;
2168 default:
2169 break;
2170 }
2171
2172 // AddrMode6 Base (register+alignment)
2173 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2174 return MCDisassembler::Fail;
2175
2176 // AddrMode6 Offset (register)
2177 switch (Inst.getOpcode()) {
2178 default:
2179 // The below have been updated to have explicit am6offset split
2180 // between fixed and register offset. For those instructions not
2181 // yet updated, we need to add an additional reg0 operand for the
2182 // fixed variant.
2183 //
2184 // The fixed offset encodes as Rm == 0xd, so we check for that.
2185 if (Rm == 0xd) {
2187 break;
2188 }
2189 // Fall through to handle the register offset variant.
2190 [[fallthrough]];
2191 case ARM::VLD1d8wb_fixed:
2192 case ARM::VLD1d16wb_fixed:
2193 case ARM::VLD1d32wb_fixed:
2194 case ARM::VLD1d64wb_fixed:
2195 case ARM::VLD1d8Twb_fixed:
2196 case ARM::VLD1d16Twb_fixed:
2197 case ARM::VLD1d32Twb_fixed:
2198 case ARM::VLD1d64Twb_fixed:
2199 case ARM::VLD1d8Qwb_fixed:
2200 case ARM::VLD1d16Qwb_fixed:
2201 case ARM::VLD1d32Qwb_fixed:
2202 case ARM::VLD1d64Qwb_fixed:
2203 case ARM::VLD1d8wb_register:
2204 case ARM::VLD1d16wb_register:
2205 case ARM::VLD1d32wb_register:
2206 case ARM::VLD1d64wb_register:
2207 case ARM::VLD1q8wb_fixed:
2208 case ARM::VLD1q16wb_fixed:
2209 case ARM::VLD1q32wb_fixed:
2210 case ARM::VLD1q64wb_fixed:
2211 case ARM::VLD1q8wb_register:
2212 case ARM::VLD1q16wb_register:
2213 case ARM::VLD1q32wb_register:
2214 case ARM::VLD1q64wb_register:
2215 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2216 // variant encodes Rm == 0xf. Anything else is a register offset post-
2217 // increment and we need to add the register operand to the instruction.
2218 if (Rm != 0xD && Rm != 0xF &&
2219 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2220 return MCDisassembler::Fail;
2221 break;
2222 case ARM::VLD2d8wb_fixed:
2223 case ARM::VLD2d16wb_fixed:
2224 case ARM::VLD2d32wb_fixed:
2225 case ARM::VLD2b8wb_fixed:
2226 case ARM::VLD2b16wb_fixed:
2227 case ARM::VLD2b32wb_fixed:
2228 case ARM::VLD2q8wb_fixed:
2229 case ARM::VLD2q16wb_fixed:
2230 case ARM::VLD2q32wb_fixed:
2231 break;
2232 }
2233
2234 return S;
2235}
2236
2237static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2238 uint64_t Address,
2239 const MCDisassembler *Decoder) {
2241
2242 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2243 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2244 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2245 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2246 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2247 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2248
2249 // Writeback Operand
2250 switch (Inst.getOpcode()) {
2251 case ARM::VST1d8wb_fixed:
2252 case ARM::VST1d16wb_fixed:
2253 case ARM::VST1d32wb_fixed:
2254 case ARM::VST1d64wb_fixed:
2255 case ARM::VST1d8wb_register:
2256 case ARM::VST1d16wb_register:
2257 case ARM::VST1d32wb_register:
2258 case ARM::VST1d64wb_register:
2259 case ARM::VST1q8wb_fixed:
2260 case ARM::VST1q16wb_fixed:
2261 case ARM::VST1q32wb_fixed:
2262 case ARM::VST1q64wb_fixed:
2263 case ARM::VST1q8wb_register:
2264 case ARM::VST1q16wb_register:
2265 case ARM::VST1q32wb_register:
2266 case ARM::VST1q64wb_register:
2267 case ARM::VST1d8Twb_fixed:
2268 case ARM::VST1d16Twb_fixed:
2269 case ARM::VST1d32Twb_fixed:
2270 case ARM::VST1d64Twb_fixed:
2271 case ARM::VST1d8Twb_register:
2272 case ARM::VST1d16Twb_register:
2273 case ARM::VST1d32Twb_register:
2274 case ARM::VST1d64Twb_register:
2275 case ARM::VST1d8Qwb_fixed:
2276 case ARM::VST1d16Qwb_fixed:
2277 case ARM::VST1d32Qwb_fixed:
2278 case ARM::VST1d64Qwb_fixed:
2279 case ARM::VST1d8Qwb_register:
2280 case ARM::VST1d16Qwb_register:
2281 case ARM::VST1d32Qwb_register:
2282 case ARM::VST1d64Qwb_register:
2283 case ARM::VST2d8wb_fixed:
2284 case ARM::VST2d16wb_fixed:
2285 case ARM::VST2d32wb_fixed:
2286 case ARM::VST2d8wb_register:
2287 case ARM::VST2d16wb_register:
2288 case ARM::VST2d32wb_register:
2289 case ARM::VST2q8wb_fixed:
2290 case ARM::VST2q16wb_fixed:
2291 case ARM::VST2q32wb_fixed:
2292 case ARM::VST2q8wb_register:
2293 case ARM::VST2q16wb_register:
2294 case ARM::VST2q32wb_register:
2295 case ARM::VST2b8wb_fixed:
2296 case ARM::VST2b16wb_fixed:
2297 case ARM::VST2b32wb_fixed:
2298 case ARM::VST2b8wb_register:
2299 case ARM::VST2b16wb_register:
2300 case ARM::VST2b32wb_register:
2301 if (Rm == 0xF)
2302 return MCDisassembler::Fail;
2304 break;
2305 case ARM::VST3d8_UPD:
2306 case ARM::VST3d16_UPD:
2307 case ARM::VST3d32_UPD:
2308 case ARM::VST3q8_UPD:
2309 case ARM::VST3q16_UPD:
2310 case ARM::VST3q32_UPD:
2311 case ARM::VST4d8_UPD:
2312 case ARM::VST4d16_UPD:
2313 case ARM::VST4d32_UPD:
2314 case ARM::VST4q8_UPD:
2315 case ARM::VST4q16_UPD:
2316 case ARM::VST4q32_UPD:
2317 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2318 return MCDisassembler::Fail;
2319 break;
2320 default:
2321 break;
2322 }
2323
2324 // AddrMode6 Base (register+alignment)
2325 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2326 return MCDisassembler::Fail;
2327
2328 // AddrMode6 Offset (register)
2329 switch (Inst.getOpcode()) {
2330 default:
2331 if (Rm == 0xD)
2333 else if (Rm != 0xF) {
2334 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2335 return MCDisassembler::Fail;
2336 }
2337 break;
2338 case ARM::VST1d8wb_fixed:
2339 case ARM::VST1d16wb_fixed:
2340 case ARM::VST1d32wb_fixed:
2341 case ARM::VST1d64wb_fixed:
2342 case ARM::VST1q8wb_fixed:
2343 case ARM::VST1q16wb_fixed:
2344 case ARM::VST1q32wb_fixed:
2345 case ARM::VST1q64wb_fixed:
2346 case ARM::VST1d8Twb_fixed:
2347 case ARM::VST1d16Twb_fixed:
2348 case ARM::VST1d32Twb_fixed:
2349 case ARM::VST1d64Twb_fixed:
2350 case ARM::VST1d8Qwb_fixed:
2351 case ARM::VST1d16Qwb_fixed:
2352 case ARM::VST1d32Qwb_fixed:
2353 case ARM::VST1d64Qwb_fixed:
2354 case ARM::VST2d8wb_fixed:
2355 case ARM::VST2d16wb_fixed:
2356 case ARM::VST2d32wb_fixed:
2357 case ARM::VST2q8wb_fixed:
2358 case ARM::VST2q16wb_fixed:
2359 case ARM::VST2q32wb_fixed:
2360 case ARM::VST2b8wb_fixed:
2361 case ARM::VST2b16wb_fixed:
2362 case ARM::VST2b32wb_fixed:
2363 break;
2364 }
2365
2366 // First input register
2367 switch (Inst.getOpcode()) {
2368 case ARM::VST1q16:
2369 case ARM::VST1q32:
2370 case ARM::VST1q64:
2371 case ARM::VST1q8:
2372 case ARM::VST1q16wb_fixed:
2373 case ARM::VST1q16wb_register:
2374 case ARM::VST1q32wb_fixed:
2375 case ARM::VST1q32wb_register:
2376 case ARM::VST1q64wb_fixed:
2377 case ARM::VST1q64wb_register:
2378 case ARM::VST1q8wb_fixed:
2379 case ARM::VST1q8wb_register:
2380 case ARM::VST2d16:
2381 case ARM::VST2d32:
2382 case ARM::VST2d8:
2383 case ARM::VST2d16wb_fixed:
2384 case ARM::VST2d16wb_register:
2385 case ARM::VST2d32wb_fixed:
2386 case ARM::VST2d32wb_register:
2387 case ARM::VST2d8wb_fixed:
2388 case ARM::VST2d8wb_register:
2389 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2390 return MCDisassembler::Fail;
2391 break;
2392 case ARM::VST2b16:
2393 case ARM::VST2b32:
2394 case ARM::VST2b8:
2395 case ARM::VST2b16wb_fixed:
2396 case ARM::VST2b16wb_register:
2397 case ARM::VST2b32wb_fixed:
2398 case ARM::VST2b32wb_register:
2399 case ARM::VST2b8wb_fixed:
2400 case ARM::VST2b8wb_register:
2401 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2402 return MCDisassembler::Fail;
2403 break;
2404 default:
2405 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2406 return MCDisassembler::Fail;
2407 }
2408
2409 // Second input register
2410 switch (Inst.getOpcode()) {
2411 case ARM::VST3d8:
2412 case ARM::VST3d16:
2413 case ARM::VST3d32:
2414 case ARM::VST3d8_UPD:
2415 case ARM::VST3d16_UPD:
2416 case ARM::VST3d32_UPD:
2417 case ARM::VST4d8:
2418 case ARM::VST4d16:
2419 case ARM::VST4d32:
2420 case ARM::VST4d8_UPD:
2421 case ARM::VST4d16_UPD:
2422 case ARM::VST4d32_UPD:
2423 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2424 return MCDisassembler::Fail;
2425 break;
2426 case ARM::VST3q8:
2427 case ARM::VST3q16:
2428 case ARM::VST3q32:
2429 case ARM::VST3q8_UPD:
2430 case ARM::VST3q16_UPD:
2431 case ARM::VST3q32_UPD:
2432 case ARM::VST4q8:
2433 case ARM::VST4q16:
2434 case ARM::VST4q32:
2435 case ARM::VST4q8_UPD:
2436 case ARM::VST4q16_UPD:
2437 case ARM::VST4q32_UPD:
2438 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2439 return MCDisassembler::Fail;
2440 break;
2441 default:
2442 break;
2443 }
2444
2445 // Third input register
2446 switch (Inst.getOpcode()) {
2447 case ARM::VST3d8:
2448 case ARM::VST3d16:
2449 case ARM::VST3d32:
2450 case ARM::VST3d8_UPD:
2451 case ARM::VST3d16_UPD:
2452 case ARM::VST3d32_UPD:
2453 case ARM::VST4d8:
2454 case ARM::VST4d16:
2455 case ARM::VST4d32:
2456 case ARM::VST4d8_UPD:
2457 case ARM::VST4d16_UPD:
2458 case ARM::VST4d32_UPD:
2459 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2460 return MCDisassembler::Fail;
2461 break;
2462 case ARM::VST3q8:
2463 case ARM::VST3q16:
2464 case ARM::VST3q32:
2465 case ARM::VST3q8_UPD:
2466 case ARM::VST3q16_UPD:
2467 case ARM::VST3q32_UPD:
2468 case ARM::VST4q8:
2469 case ARM::VST4q16:
2470 case ARM::VST4q32:
2471 case ARM::VST4q8_UPD:
2472 case ARM::VST4q16_UPD:
2473 case ARM::VST4q32_UPD:
2474 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2475 return MCDisassembler::Fail;
2476 break;
2477 default:
2478 break;
2479 }
2480
2481 // Fourth input register
2482 switch (Inst.getOpcode()) {
2483 case ARM::VST4d8:
2484 case ARM::VST4d16:
2485 case ARM::VST4d32:
2486 case ARM::VST4d8_UPD:
2487 case ARM::VST4d16_UPD:
2488 case ARM::VST4d32_UPD:
2489 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2490 return MCDisassembler::Fail;
2491 break;
2492 case ARM::VST4q8:
2493 case ARM::VST4q16:
2494 case ARM::VST4q32:
2495 case ARM::VST4q8_UPD:
2496 case ARM::VST4q16_UPD:
2497 case ARM::VST4q32_UPD:
2498 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2499 return MCDisassembler::Fail;
2500 break;
2501 default:
2502 break;
2503 }
2504
2505 return S;
2506}
2507
2508static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2509 uint64_t Address,
2510 const MCDisassembler *Decoder) {
2511 unsigned type = fieldFromInstruction(Insn, 8, 4);
2512 unsigned align = fieldFromInstruction(Insn, 4, 2);
2513 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2514 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2515 if (type == 10 && align == 3) return MCDisassembler::Fail;
2516
2517 unsigned load = fieldFromInstruction(Insn, 21, 1);
2518 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2519 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2520}
2521
2522static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2523 uint64_t Address,
2524 const MCDisassembler *Decoder) {
2525 unsigned size = fieldFromInstruction(Insn, 6, 2);
2526 if (size == 3) return MCDisassembler::Fail;
2527
2528 unsigned type = fieldFromInstruction(Insn, 8, 4);
2529 unsigned align = fieldFromInstruction(Insn, 4, 2);
2530 if (type == 8 && align == 3) return MCDisassembler::Fail;
2531 if (type == 9 && align == 3) return MCDisassembler::Fail;
2532
2533 unsigned load = fieldFromInstruction(Insn, 21, 1);
2534 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2535 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2536}
2537
2538static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2539 uint64_t Address,
2540 const MCDisassembler *Decoder) {
2541 unsigned size = fieldFromInstruction(Insn, 6, 2);
2542 if (size == 3) return MCDisassembler::Fail;
2543
2544 unsigned align = fieldFromInstruction(Insn, 4, 2);
2545 if (align & 2) return MCDisassembler::Fail;
2546
2547 unsigned load = fieldFromInstruction(Insn, 21, 1);
2548 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2549 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2550}
2551
2552static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2553 uint64_t Address,
2554 const MCDisassembler *Decoder) {
2555 unsigned size = fieldFromInstruction(Insn, 6, 2);
2556 if (size == 3) return MCDisassembler::Fail;
2557
2558 unsigned load = fieldFromInstruction(Insn, 21, 1);
2559 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2560 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2561}
2562
2564 uint64_t Address,
2565 const MCDisassembler *Decoder) {
2567
2568 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2569 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2570 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2571 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2572 unsigned align = fieldFromInstruction(Insn, 4, 1);
2573 unsigned size = fieldFromInstruction(Insn, 6, 2);
2574
2575 if (size == 0 && align == 1)
2576 return MCDisassembler::Fail;
2577 align *= (1 << size);
2578
2579 switch (Inst.getOpcode()) {
2580 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2581 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2582 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2583 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2584 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2585 return MCDisassembler::Fail;
2586 break;
2587 default:
2588 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2589 return MCDisassembler::Fail;
2590 break;
2591 }
2592 if (Rm != 0xF) {
2593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2594 return MCDisassembler::Fail;
2595 }
2596
2597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2598 return MCDisassembler::Fail;
2599 Inst.addOperand(MCOperand::createImm(align));
2600
2601 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2602 // variant encodes Rm == 0xf. Anything else is a register offset post-
2603 // increment and we need to add the register operand to the instruction.
2604 if (Rm != 0xD && Rm != 0xF &&
2605 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2606 return MCDisassembler::Fail;
2607
2608 return S;
2609}
2610
2612 uint64_t Address,
2613 const MCDisassembler *Decoder) {
2615
2616 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2617 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2618 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2619 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2620 unsigned align = fieldFromInstruction(Insn, 4, 1);
2621 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2622 align *= 2*size;
2623
2624 switch (Inst.getOpcode()) {
2625 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2626 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2627 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2628 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2629 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2630 return MCDisassembler::Fail;
2631 break;
2632 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2633 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2634 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2635 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2636 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2637 return MCDisassembler::Fail;
2638 break;
2639 default:
2640 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2641 return MCDisassembler::Fail;
2642 break;
2643 }
2644
2645 if (Rm != 0xF)
2647
2648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2649 return MCDisassembler::Fail;
2650 Inst.addOperand(MCOperand::createImm(align));
2651
2652 if (Rm != 0xD && Rm != 0xF) {
2653 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2654 return MCDisassembler::Fail;
2655 }
2656
2657 return S;
2658}
2659
2661 uint64_t Address,
2662 const MCDisassembler *Decoder) {
2664
2665 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2666 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2667 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2668 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2669 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2670
2671 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2672 return MCDisassembler::Fail;
2673 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2674 return MCDisassembler::Fail;
2675 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2676 return MCDisassembler::Fail;
2677 if (Rm != 0xF) {
2678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2679 return MCDisassembler::Fail;
2680 }
2681
2682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2683 return MCDisassembler::Fail;
2685
2686 if (Rm == 0xD)
2688 else if (Rm != 0xF) {
2689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2690 return MCDisassembler::Fail;
2691 }
2692
2693 return S;
2694}
2695
2697 uint64_t Address,
2698 const MCDisassembler *Decoder) {
2700
2701 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2702 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2703 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2704 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2705 unsigned size = fieldFromInstruction(Insn, 6, 2);
2706 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2707 unsigned align = fieldFromInstruction(Insn, 4, 1);
2708
2709 if (size == 0x3) {
2710 if (align == 0)
2711 return MCDisassembler::Fail;
2712 align = 16;
2713 } else {
2714 if (size == 2) {
2715 align *= 8;
2716 } else {
2717 size = 1 << size;
2718 align *= 4*size;
2719 }
2720 }
2721
2722 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2723 return MCDisassembler::Fail;
2724 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2725 return MCDisassembler::Fail;
2726 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2727 return MCDisassembler::Fail;
2728 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2729 return MCDisassembler::Fail;
2730 if (Rm != 0xF) {
2731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2732 return MCDisassembler::Fail;
2733 }
2734
2735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2736 return MCDisassembler::Fail;
2737 Inst.addOperand(MCOperand::createImm(align));
2738
2739 if (Rm == 0xD)
2741 else if (Rm != 0xF) {
2742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2743 return MCDisassembler::Fail;
2744 }
2745
2746 return S;
2747}
2748
2750 uint64_t Address,
2751 const MCDisassembler *Decoder) {
2753
2754 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2755 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2756 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2757 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2758 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2759 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2760 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2761 unsigned Q = fieldFromInstruction(Insn, 6, 1);
2762
2763 if (Q) {
2764 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2765 return MCDisassembler::Fail;
2766 } else {
2767 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2768 return MCDisassembler::Fail;
2769 }
2770
2772
2773 switch (Inst.getOpcode()) {
2774 case ARM::VORRiv4i16:
2775 case ARM::VORRiv2i32:
2776 case ARM::VBICiv4i16:
2777 case ARM::VBICiv2i32:
2778 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2779 return MCDisassembler::Fail;
2780 break;
2781 case ARM::VORRiv8i16:
2782 case ARM::VORRiv4i32:
2783 case ARM::VBICiv8i16:
2784 case ARM::VBICiv4i32:
2785 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2786 return MCDisassembler::Fail;
2787 break;
2788 default:
2789 break;
2790 }
2791
2792 return S;
2793}
2794
2796 uint64_t Address,
2797 const MCDisassembler *Decoder) {
2799
2800 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
2801 fieldFromInstruction(Insn, 13, 3));
2802 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
2803 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2804 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2805 imm |= fieldFromInstruction(Insn, 28, 1) << 7;
2806 imm |= cmode << 8;
2807 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2808
2809 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
2810 return MCDisassembler::Fail;
2811
2812 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
2813 return MCDisassembler::Fail;
2814
2816
2817 Check(S, DecodeVpredROperand(Inst, Decoder));
2818 return S;
2819}
2820
2822 uint64_t Address,
2823 const MCDisassembler *Decoder) {
2825
2826 unsigned Qd = fieldFromInstruction(Insn, 13, 3);
2827 Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
2828 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
2829 return MCDisassembler::Fail;
2830 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
2831
2832 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
2833 Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
2834 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
2835 return MCDisassembler::Fail;
2836 unsigned Qm = fieldFromInstruction(Insn, 1, 3);
2837 Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
2838 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
2839 return MCDisassembler::Fail;
2840 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
2841 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
2842
2843 Check(S, DecodeVpredROperand(Inst, Decoder));
2844 return S;
2845}
2846
2848 uint64_t Address,
2849 const MCDisassembler *Decoder) {
2851
2852 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2853 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2854 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2855 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2856 unsigned size = fieldFromInstruction(Insn, 18, 2);
2857
2858 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2859 return MCDisassembler::Fail;
2860 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2861 return MCDisassembler::Fail;
2863
2864 return S;
2865}
2866
2867static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
2868 uint64_t Address,
2869 const MCDisassembler *Decoder) {
2870 Inst.addOperand(MCOperand::createImm(8 - Val));
2872}
2873
2874static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
2875 uint64_t Address,
2876 const MCDisassembler *Decoder) {
2877 Inst.addOperand(MCOperand::createImm(16 - Val));
2879}
2880
2881static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
2882 uint64_t Address,
2883 const MCDisassembler *Decoder) {
2884 Inst.addOperand(MCOperand::createImm(32 - Val));
2886}
2887
2888static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
2889 uint64_t Address,
2890 const MCDisassembler *Decoder) {
2891 Inst.addOperand(MCOperand::createImm(64 - Val));
2893}
2894
2895static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
2896 uint64_t Address,
2897 const MCDisassembler *Decoder) {
2899
2900 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2901 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2902 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2903 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
2904 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2905 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2906 unsigned op = fieldFromInstruction(Insn, 6, 1);
2907
2908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2909 return MCDisassembler::Fail;
2910 if (op) {
2911 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2912 return MCDisassembler::Fail; // Writeback
2913 }
2914
2915 switch (Inst.getOpcode()) {
2916 case ARM::VTBL2:
2917 case ARM::VTBX2:
2918 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2919 return MCDisassembler::Fail;
2920 break;
2921 default:
2922 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2923 return MCDisassembler::Fail;
2924 }
2925
2926 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2927 return MCDisassembler::Fail;
2928
2929 return S;
2930}
2931
2933 uint64_t Address,
2934 const MCDisassembler *Decoder) {
2936
2937 unsigned dst = fieldFromInstruction(Insn, 8, 3);
2938 unsigned imm = fieldFromInstruction(Insn, 0, 8);
2939
2940 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2941 return MCDisassembler::Fail;
2942
2943 switch(Inst.getOpcode()) {
2944 default:
2945 return MCDisassembler::Fail;
2946 case ARM::tADR:
2947 break; // tADR does not explicitly represent the PC as an operand.
2948 case ARM::tADDrSPi:
2949 Inst.addOperand(MCOperand::createReg(ARM::SP));
2950 break;
2951 }
2952
2954 return S;
2955}
2956
2957static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
2958 uint64_t Address,
2959 const MCDisassembler *Decoder) {
2960 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
2961 true, 2, Inst, Decoder))
2964}
2965
2966static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
2967 uint64_t Address,
2968 const MCDisassembler *Decoder) {
2969 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
2970 true, 4, Inst, Decoder))
2973}
2974
2976 uint64_t Address,
2977 const MCDisassembler *Decoder) {
2978 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
2979 true, 2, Inst, Decoder))
2980 Inst.addOperand(MCOperand::createImm(Val << 1));
2982}
2983
2984static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
2985 uint64_t Address,
2986 const MCDisassembler *Decoder) {
2988
2989 unsigned Rn = fieldFromInstruction(Val, 0, 3);
2990 unsigned Rm = fieldFromInstruction(Val, 3, 3);
2991
2992 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2993 return MCDisassembler::Fail;
2994 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2995 return MCDisassembler::Fail;
2996
2997 return S;
2998}
2999
3000static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3001 uint64_t Address,
3002 const MCDisassembler *Decoder) {
3004
3005 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3006 unsigned imm = fieldFromInstruction(Val, 3, 5);
3007
3008 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3009 return MCDisassembler::Fail;
3011
3012 return S;
3013}
3014
3015static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3016 uint64_t Address,
3017 const MCDisassembler *Decoder) {
3018 unsigned imm = Val << 2;
3019
3021 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3022
3024}
3025
3026static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3027 uint64_t Address,
3028 const MCDisassembler *Decoder) {
3029 Inst.addOperand(MCOperand::createReg(ARM::SP));
3031
3033}
3034
3035static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3036 uint64_t Address,
3037 const MCDisassembler *Decoder) {
3039
3040 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3041 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3042 unsigned imm = fieldFromInstruction(Val, 0, 2);
3043
3044 // Thumb stores cannot use PC as dest register.
3045 switch (Inst.getOpcode()) {
3046 case ARM::t2STRHs:
3047 case ARM::t2STRBs:
3048 case ARM::t2STRs:
3049 if (Rn == 15)
3050 return MCDisassembler::Fail;
3051 break;
3052 default:
3053 break;
3054 }
3055
3056 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3057 return MCDisassembler::Fail;
3058 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3059 return MCDisassembler::Fail;
3061
3062 return S;
3063}
3064
3065static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3066 uint64_t Address,
3067 const MCDisassembler *Decoder) {
3069
3070 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3071 unsigned U = fieldFromInstruction(Insn, 23, 1);
3072 int imm = fieldFromInstruction(Insn, 0, 12);
3073
3074 const FeatureBitset &featureBits =
3075 Decoder->getSubtargetInfo().getFeatureBits();
3076
3077 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3078
3079 if (Rt == 15) {
3080 switch (Inst.getOpcode()) {
3081 case ARM::t2LDRBpci:
3082 case ARM::t2LDRHpci:
3083 Inst.setOpcode(ARM::t2PLDpci);
3084 break;
3085 case ARM::t2LDRSBpci:
3086 Inst.setOpcode(ARM::t2PLIpci);
3087 break;
3088 case ARM::t2LDRSHpci:
3089 return MCDisassembler::Fail;
3090 default:
3091 break;
3092 }
3093 }
3094
3095 switch(Inst.getOpcode()) {
3096 case ARM::t2PLDpci:
3097 break;
3098 case ARM::t2PLIpci:
3099 if (!hasV7Ops)
3100 return MCDisassembler::Fail;
3101 break;
3102 default:
3103 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3104 return MCDisassembler::Fail;
3105 }
3106
3107 if (!U) {
3108 // Special case for #-0.
3109 if (imm == 0)
3110 imm = INT32_MIN;
3111 else
3112 imm = -imm;
3113 }
3115
3116 return S;
3117}
3118
3119static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3120 uint64_t Address,
3121 const MCDisassembler *Decoder) {
3123
3124 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3125 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3126
3127 const FeatureBitset &featureBits =
3128 Decoder->getSubtargetInfo().getFeatureBits();
3129
3130 bool hasMP = featureBits[ARM::FeatureMP];
3131 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3132
3133 if (Rn == 15) {
3134 switch (Inst.getOpcode()) {
3135 case ARM::t2LDRBs:
3136 Inst.setOpcode(ARM::t2LDRBpci);
3137 break;
3138 case ARM::t2LDRHs:
3139 Inst.setOpcode(ARM::t2LDRHpci);
3140 break;
3141 case ARM::t2LDRSHs:
3142 Inst.setOpcode(ARM::t2LDRSHpci);
3143 break;
3144 case ARM::t2LDRSBs:
3145 Inst.setOpcode(ARM::t2LDRSBpci);
3146 break;
3147 case ARM::t2LDRs:
3148 Inst.setOpcode(ARM::t2LDRpci);
3149 break;
3150 case ARM::t2PLDs:
3151 Inst.setOpcode(ARM::t2PLDpci);
3152 break;
3153 case ARM::t2PLIs:
3154 Inst.setOpcode(ARM::t2PLIpci);
3155 break;
3156 default:
3157 return MCDisassembler::Fail;
3158 }
3159
3160 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3161 }
3162
3163 if (Rt == 15) {
3164 switch (Inst.getOpcode()) {
3165 case ARM::t2LDRSHs:
3166 return MCDisassembler::Fail;
3167 case ARM::t2LDRHs:
3168 Inst.setOpcode(ARM::t2PLDWs);
3169 break;
3170 case ARM::t2LDRSBs:
3171 Inst.setOpcode(ARM::t2PLIs);
3172 break;
3173 default:
3174 break;
3175 }
3176 }
3177
3178 switch (Inst.getOpcode()) {
3179 case ARM::t2PLDs:
3180 break;
3181 case ARM::t2PLIs:
3182 if (!hasV7Ops)
3183 return MCDisassembler::Fail;
3184 break;
3185 case ARM::t2PLDWs:
3186 if (!hasV7Ops || !hasMP)
3187 return MCDisassembler::Fail;
3188 break;
3189 default:
3190 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3191 return MCDisassembler::Fail;
3192 }
3193
3194 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3195 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3196 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3197 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3198 return MCDisassembler::Fail;
3199
3200 return S;
3201}
3202
3203static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
3204 const MCDisassembler *Decoder) {
3205 int imm = Val & 0xFF;
3206 if (Val == 0)
3207 imm = INT32_MIN;
3208 else if (!(Val & 0x100))
3209 imm *= -1;
3211
3213}
3214
3215static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3216 uint64_t Address,
3217 const MCDisassembler *Decoder) {
3219
3220 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3221 unsigned imm = fieldFromInstruction(Val, 0, 9);
3222
3223 // Thumb stores cannot use PC as dest register.
3224 switch (Inst.getOpcode()) {
3225 case ARM::t2STRT:
3226 case ARM::t2STRBT:
3227 case ARM::t2STRHT:
3228 case ARM::t2STRi8:
3229 case ARM::t2STRHi8:
3230 case ARM::t2STRBi8:
3231 if (Rn == 15)
3232 return MCDisassembler::Fail;
3233 break;
3234 default:
3235 break;
3236 }
3237
3238 // Some instructions always use an additive offset.
3239 switch (Inst.getOpcode()) {
3240 case ARM::t2LDRT:
3241 case ARM::t2LDRBT:
3242 case ARM::t2LDRHT:
3243 case ARM::t2LDRSBT:
3244 case ARM::t2LDRSHT:
3245 case ARM::t2STRT:
3246 case ARM::t2STRBT:
3247 case ARM::t2STRHT:
3248 imm |= 0x100;
3249 break;
3250 default:
3251 break;
3252 }
3253
3254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3255 return MCDisassembler::Fail;
3256 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3257 return MCDisassembler::Fail;
3258
3259 return S;
3260}
3261
3262static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3263 uint64_t Address,
3264 const MCDisassembler *Decoder) {
3266
3267 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3268 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3269 unsigned U = fieldFromInstruction(Insn, 9, 1);
3270 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3271 imm |= (U << 8);
3272 imm |= (Rn << 9);
3273 unsigned add = fieldFromInstruction(Insn, 9, 1);
3274
3275 const FeatureBitset &featureBits =
3276 Decoder->getSubtargetInfo().getFeatureBits();
3277
3278 bool hasMP = featureBits[ARM::FeatureMP];
3279 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3280
3281 if (Rn == 15) {
3282 switch (Inst.getOpcode()) {
3283 case ARM::t2LDRi8:
3284 Inst.setOpcode(ARM::t2LDRpci);
3285 break;
3286 case ARM::t2LDRBi8:
3287 Inst.setOpcode(ARM::t2LDRBpci);
3288 break;
3289 case ARM::t2LDRSBi8:
3290 Inst.setOpcode(ARM::t2LDRSBpci);
3291 break;
3292 case ARM::t2LDRHi8:
3293 Inst.setOpcode(ARM::t2LDRHpci);
3294 break;
3295 case ARM::t2LDRSHi8:
3296 Inst.setOpcode(ARM::t2LDRSHpci);
3297 break;
3298 case ARM::t2PLDi8:
3299 Inst.setOpcode(ARM::t2PLDpci);
3300 break;
3301 case ARM::t2PLIi8:
3302 Inst.setOpcode(ARM::t2PLIpci);
3303 break;
3304 default:
3305 return MCDisassembler::Fail;
3306 }
3307 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3308 }
3309
3310 if (Rt == 15) {
3311 switch (Inst.getOpcode()) {
3312 case ARM::t2LDRSHi8:
3313 return MCDisassembler::Fail;
3314 case ARM::t2LDRHi8:
3315 if (!add)
3316 Inst.setOpcode(ARM::t2PLDWi8);
3317 break;
3318 case ARM::t2LDRSBi8:
3319 Inst.setOpcode(ARM::t2PLIi8);
3320 break;
3321 default:
3322 break;
3323 }
3324 }
3325
3326 switch (Inst.getOpcode()) {
3327 case ARM::t2PLDi8:
3328 break;
3329 case ARM::t2PLIi8:
3330 if (!hasV7Ops)
3331 return MCDisassembler::Fail;
3332 break;
3333 case ARM::t2PLDWi8:
3334 if (!hasV7Ops || !hasMP)
3335 return MCDisassembler::Fail;
3336 break;
3337 default:
3338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3339 return MCDisassembler::Fail;
3340 }
3341
3342 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3343 return MCDisassembler::Fail;
3344 return S;
3345}
3346
3347static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3348 uint64_t Address,
3349 const MCDisassembler *Decoder) {
3351
3352 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3353 unsigned imm = fieldFromInstruction(Val, 0, 12);
3354
3355 // Thumb stores cannot use PC as dest register.
3356 switch (Inst.getOpcode()) {
3357 case ARM::t2STRi12:
3358 case ARM::t2STRBi12:
3359 case ARM::t2STRHi12:
3360 if (Rn == 15)
3361 return MCDisassembler::Fail;
3362 break;
3363 default:
3364 break;
3365 }
3366
3367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3368 return MCDisassembler::Fail;
3370
3371 return S;
3372}
3373
3374static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3375 uint64_t Address,
3376 const MCDisassembler *Decoder) {
3378
3379 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3380 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3381 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3382 imm |= (Rn << 13);
3383
3384 const FeatureBitset &featureBits =
3385 Decoder->getSubtargetInfo().getFeatureBits();
3386
3387 bool hasMP = featureBits[ARM::FeatureMP];
3388 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3389
3390 if (Rn == 15) {
3391 switch (Inst.getOpcode()) {
3392 case ARM::t2LDRi12:
3393 Inst.setOpcode(ARM::t2LDRpci);
3394 break;
3395 case ARM::t2LDRHi12:
3396 Inst.setOpcode(ARM::t2LDRHpci);
3397 break;
3398 case ARM::t2LDRSHi12:
3399 Inst.setOpcode(ARM::t2LDRSHpci);
3400 break;
3401 case ARM::t2LDRBi12:
3402 Inst.setOpcode(ARM::t2LDRBpci);
3403 break;
3404 case ARM::t2LDRSBi12:
3405 Inst.setOpcode(ARM::t2LDRSBpci);
3406 break;
3407 case ARM::t2PLDi12:
3408 Inst.setOpcode(ARM::t2PLDpci);
3409 break;
3410 case ARM::t2PLIi12:
3411 Inst.setOpcode(ARM::t2PLIpci);
3412 break;
3413 default:
3414 return MCDisassembler::Fail;
3415 }
3416 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3417 }
3418
3419 if (Rt == 15) {
3420 switch (Inst.getOpcode()) {
3421 case ARM::t2LDRSHi12:
3422 return MCDisassembler::Fail;
3423 case ARM::t2LDRHi12:
3424 Inst.setOpcode(ARM::t2PLDWi12);
3425 break;
3426 case ARM::t2LDRSBi12:
3427 Inst.setOpcode(ARM::t2PLIi12);
3428 break;
3429 default:
3430 break;
3431 }
3432 }
3433
3434 switch (Inst.getOpcode()) {
3435 case ARM::t2PLDi12:
3436 break;
3437 case ARM::t2PLIi12:
3438 if (!hasV7Ops)
3439 return MCDisassembler::Fail;
3440 break;
3441 case ARM::t2PLDWi12:
3442 if (!hasV7Ops || !hasMP)
3443 return MCDisassembler::Fail;
3444 break;
3445 default:
3446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3447 return MCDisassembler::Fail;
3448 }
3449
3450 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3451 return MCDisassembler::Fail;
3452 return S;
3453}
3454
3455static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
3456 const MCDisassembler *Decoder) {
3458
3459 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3460 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3461 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3462 imm |= (Rn << 9);
3463
3464 if (Rn == 15) {
3465 switch (Inst.getOpcode()) {
3466 case ARM::t2LDRT:
3467 Inst.setOpcode(ARM::t2LDRpci);
3468 break;
3469 case ARM::t2LDRBT:
3470 Inst.setOpcode(ARM::t2LDRBpci);
3471 break;
3472 case ARM::t2LDRHT:
3473 Inst.setOpcode(ARM::t2LDRHpci);
3474 break;
3475 case ARM::t2LDRSBT:
3476 Inst.setOpcode(ARM::t2LDRSBpci);
3477 break;
3478 case ARM::t2LDRSHT:
3479 Inst.setOpcode(ARM::t2LDRSHpci);
3480 break;
3481 default:
3482 return MCDisassembler::Fail;
3483 }
3484 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3485 }
3486
3487 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3488 return MCDisassembler::Fail;
3489 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3490 return MCDisassembler::Fail;
3491 return S;
3492}
3493
3494static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
3495 const MCDisassembler *Decoder) {
3496 if (Val == 0)
3497 Inst.addOperand(MCOperand::createImm(INT32_MIN));
3498 else {
3499 int imm = Val & 0xFF;
3500
3501 if (!(Val & 0x100)) imm *= -1;
3502 Inst.addOperand(MCOperand::createImm(imm * 4));
3503 }
3504
3506}
3507
3508static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
3509 const MCDisassembler *Decoder) {
3510 if (Val == 0)
3511 Inst.addOperand(MCOperand::createImm(INT32_MIN));
3512 else {
3513 int imm = Val & 0x7F;
3514
3515 if (!(Val & 0x80))
3516 imm *= -1;
3517 Inst.addOperand(MCOperand::createImm(imm * 4));
3518 }
3519
3521}
3522
3523static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3524 uint64_t Address,
3525 const MCDisassembler *Decoder) {
3527
3528 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3529 unsigned imm = fieldFromInstruction(Val, 0, 9);
3530
3531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3532 return MCDisassembler::Fail;
3533 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3534 return MCDisassembler::Fail;
3535
3536 return S;
3537}
3538
3539static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
3540 uint64_t Address,
3541 const MCDisassembler *Decoder) {
3543
3544 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3545 unsigned imm = fieldFromInstruction(Val, 0, 8);
3546
3547 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3548 return MCDisassembler::Fail;
3549 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
3550 return MCDisassembler::Fail;
3551
3552 return S;
3553}
3554
3556 uint64_t Address,
3557 const MCDisassembler *Decoder) {
3559
3560 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3561 unsigned imm = fieldFromInstruction(Val, 0, 8);
3562
3563 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3564 return MCDisassembler::Fail;
3565
3567
3568 return S;
3569}
3570
3571template <int shift>
3572static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
3573 const MCDisassembler *Decoder) {
3574 int imm = Val & 0x7F;
3575 if (Val == 0)
3576 imm = INT32_MIN;
3577 else if (!(Val & 0x80))
3578 imm *= -1;
3579 if (imm != INT32_MIN)
3580 imm *= (1U << shift);
3582
3584}
3585
3586template <int shift>
3587static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
3588 uint64_t Address,
3589 const MCDisassembler *Decoder) {
3591
3592 unsigned Rn = fieldFromInstruction(Val, 8, 3);
3593 unsigned imm = fieldFromInstruction(Val, 0, 8);
3594
3595 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3596 return MCDisassembler::Fail;
3597 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
3598 return MCDisassembler::Fail;
3599
3600 return S;
3601}
3602
3603template <int shift, int WriteBack>
3604static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
3605 uint64_t Address,
3606 const MCDisassembler *Decoder) {
3608
3609 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3610 unsigned imm = fieldFromInstruction(Val, 0, 8);
3611 if (WriteBack) {
3612 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3613 return MCDisassembler::Fail;
3614 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3615 return MCDisassembler::Fail;
3616 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
3617 return MCDisassembler::Fail;
3618
3619 return S;
3620}
3621
3622static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3623 uint64_t Address,
3624 const MCDisassembler *Decoder) {
3626
3627 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3628 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3629 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3630 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3631 addr |= Rn << 9;
3632 unsigned load = fieldFromInstruction(Insn, 20, 1);
3633
3634 if (Rn == 15) {
3635 switch (Inst.getOpcode()) {
3636 case ARM::t2LDR_PRE:
3637 case ARM::t2LDR_POST:
3638 Inst.setOpcode(ARM::t2LDRpci);
3639 break;
3640 case ARM::t2LDRB_PRE:
3641 case ARM::t2LDRB_POST:
3642 Inst.setOpcode(ARM::t2LDRBpci);
3643 break;
3644 case ARM::t2LDRH_PRE:
3645 case ARM::t2LDRH_POST:
3646 Inst.setOpcode(ARM::t2LDRHpci);
3647 break;
3648 case ARM::t2LDRSB_PRE:
3649 case ARM::t2LDRSB_POST:
3650 if (Rt == 15)
3651 Inst.setOpcode(ARM::t2PLIpci);
3652 else
3653 Inst.setOpcode(ARM::t2LDRSBpci);
3654 break;
3655 case ARM::t2LDRSH_PRE:
3656 case ARM::t2LDRSH_POST:
3657 Inst.setOpcode(ARM::t2LDRSHpci);
3658 break;
3659 default:
3660 return MCDisassembler::Fail;
3661 }
3662 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3663 }
3664
3665 if (!load) {
3666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3667 return MCDisassembler::Fail;
3668 }
3669
3670 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3671 return MCDisassembler::Fail;
3672
3673 if (load) {
3674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3675 return MCDisassembler::Fail;
3676 }
3677
3678 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3679 return MCDisassembler::Fail;
3680
3681 return S;
3682}
3683
3685 uint64_t Address,
3686 const MCDisassembler *Decoder) {
3687 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3688
3689 Inst.addOperand(MCOperand::createReg(ARM::SP));
3690 Inst.addOperand(MCOperand::createReg(ARM::SP));
3692
3694}
3695
3697 uint64_t Address,
3698 const MCDisassembler *Decoder) {
3700
3701 if (Inst.getOpcode() == ARM::tADDrSP) {
3702 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3703 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3704
3705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3706 return MCDisassembler::Fail;
3707 Inst.addOperand(MCOperand::createReg(ARM::SP));
3708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3709 return MCDisassembler::Fail;
3710 } else if (Inst.getOpcode() == ARM::tADDspr) {
3711 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3712
3713 Inst.addOperand(MCOperand::createReg(ARM::SP));
3714 Inst.addOperand(MCOperand::createReg(ARM::SP));
3715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3716 return MCDisassembler::Fail;
3717 }
3718
3719 return S;
3720}
3721
3723 uint64_t Address,
3724 const MCDisassembler *Decoder) {
3725 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3726 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3727
3728 Inst.addOperand(MCOperand::createImm(imod));
3729 Inst.addOperand(MCOperand::createImm(flags));
3730
3732}
3733
3734static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3735 uint64_t Address,
3736 const MCDisassembler *Decoder) {
3738 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3739 unsigned add = fieldFromInstruction(Insn, 4, 1);
3740
3741 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3742 return MCDisassembler::Fail;
3744
3745 return S;
3746}
3747
3748static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
3749 uint64_t Address,
3750 const MCDisassembler *Decoder) {
3752 unsigned Rn = fieldFromInstruction(Insn, 3, 4);
3753 unsigned Qm = fieldFromInstruction(Insn, 0, 3);
3754
3755 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3756 return MCDisassembler::Fail;
3757 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3758 return MCDisassembler::Fail;
3759
3760 return S;
3761}
3762
3763template <int shift>
3764static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
3765 uint64_t Address,
3766 const MCDisassembler *Decoder) {
3768 unsigned Qm = fieldFromInstruction(Insn, 8, 3);
3769 int imm = fieldFromInstruction(Insn, 0, 7);
3770
3771 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3772 return MCDisassembler::Fail;
3773
3774 if(!fieldFromInstruction(Insn, 7, 1)) {
3775 if (imm == 0)
3776 imm = INT32_MIN; // indicate -0
3777 else
3778 imm *= -1;
3779 }
3780 if (imm != INT32_MIN)
3781 imm *= (1U << shift);
3783
3784 return S;
3785}
3786
3787static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3788 uint64_t Address,
3789 const MCDisassembler *Decoder) {
3790 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3791 // Note only one trailing zero not two. Also the J1 and J2 values are from
3792 // the encoded instruction. So here change to I1 and I2 values via:
3793 // I1 = NOT(J1 EOR S);
3794 // I2 = NOT(J2 EOR S);
3795 // and build the imm32 with two trailing zeros as documented:
3796 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3797 unsigned S = (Val >> 23) & 1;
3798 unsigned J1 = (Val >> 22) & 1;
3799 unsigned J2 = (Val >> 21) & 1;
3800 unsigned I1 = !(J1 ^ S);
3801 unsigned I2 = !(J2 ^ S);
3802 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3803 int imm32 = SignExtend32<25>(tmp << 1);
3804
3805 if (!tryAddingSymbolicOperand(Address,
3806 (Address & ~2u) + imm32 + 4,
3807 true, 4, Inst, Decoder))
3808 Inst.addOperand(MCOperand::createImm(imm32));
3810}
3811
3812static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3813 uint64_t Address,
3814 const MCDisassembler *Decoder) {
3815 if (Val == 0xA || Val == 0xB)
3816 return MCDisassembler::Fail;
3817
3818 const FeatureBitset &featureBits =
3819 Decoder->getSubtargetInfo().getFeatureBits();
3820
3821 if (!isValidCoprocessorNumber(Val, featureBits))
3822 return MCDisassembler::Fail;
3823
3826}
3827
3828static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3829 uint64_t Address,
3830 const MCDisassembler *Decoder) {
3831 const FeatureBitset &FeatureBits =
3832 Decoder->getSubtargetInfo().getFeatureBits();
3834
3835 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3836 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3837
3838 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;
3839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3840 return MCDisassembler::Fail;
3841 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3842 return MCDisassembler::Fail;
3843 return S;
3844}
3845
3846static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3847 uint64_t Address,
3848 const MCDisassembler *Decoder) {
3849 if (Val & ~0xf)
3850 return MCDisassembler::Fail;
3851
3854}
3855
3857 uint64_t Address,
3858 const MCDisassembler *Decoder) {
3860
3861 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3862 if (pred == 0xE || pred == 0xF) {
3863 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3864 switch (opc) {
3865 default:
3866 return MCDisassembler::Fail;
3867 case 0xf3bf8f4:
3868 Inst.setOpcode(ARM::t2DSB);
3869 break;
3870 case 0xf3bf8f5:
3871 Inst.setOpcode(ARM::t2DMB);
3872 break;
3873 case 0xf3bf8f6:
3874 Inst.setOpcode(ARM::t2ISB);
3875 break;
3876 }
3877
3878 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3879 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3880 }
3881
3882 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3883 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3884 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3885 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3886 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3887
3888 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3889 return MCDisassembler::Fail;
3890 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3891 return MCDisassembler::Fail;
3892
3893 return S;
3894}
3895
3896// Decode a shifted immediate operand. These basically consist
3897// of an 8-bit value, and a 4-bit directive that specifies either
3898// a splat operation or a rotation.
3899static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
3900 const MCDisassembler *Decoder) {
3901 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3902 if (ctrl == 0) {
3903 unsigned byte = fieldFromInstruction(Val, 8, 2);
3904 unsigned imm = fieldFromInstruction(Val, 0, 8);
3905 switch (byte) {
3906 case 0:
3908 break;
3909 case 1:
3910 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
3911 break;
3912 case 2:
3913 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
3914 break;
3915 case 3:
3916 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
3917 (imm << 8) | imm));
3918 break;
3919 }
3920 } else {
3921 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3922 unsigned rot = fieldFromInstruction(Val, 7, 5);
3923 unsigned imm = llvm::rotr<uint32_t>(unrot, rot);
3925 }
3926
3928}
3929
3931 uint64_t Address,
3932 const MCDisassembler *Decoder) {
3933 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3934 true, 2, Inst, Decoder))
3937}
3938
3940 uint64_t Address,
3941 const MCDisassembler *Decoder) {
3942 // Val is passed in as S:J1:J2:imm10:imm11
3943 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3944 // the encoded instruction. So here change to I1 and I2 values via:
3945 // I1 = NOT(J1 EOR S);
3946 // I2 = NOT(J2 EOR S);
3947 // and build the imm32 with one trailing zero as documented:
3948 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3949 unsigned S = (Val >> 23) & 1;
3950 unsigned J1 = (Val >> 22) & 1;
3951 unsigned J2 = (Val >> 21) & 1;
3952 unsigned I1 = !(J1 ^ S);
3953 unsigned I2 = !(J2 ^ S);
3954 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3955 int imm32 = SignExtend32<25>(tmp << 1);
3956
3957 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3958 true, 4, Inst, Decoder))
3959 Inst.addOperand(MCOperand::createImm(imm32));
3961}
3962
3964 uint64_t Address,
3965 const MCDisassembler *Decoder) {
3966 if (Val & ~0xf)
3967 return MCDisassembler::Fail;
3968
3971}
3972
3973static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address,
3974 const MCDisassembler *Decoder) {
3976 const FeatureBitset &FeatureBits =
3977 Decoder->getSubtargetInfo().getFeatureBits();
3978
3979 if (FeatureBits[ARM::FeatureMClass]) {
3980 unsigned ValLow = Val & 0xff;
3981
3982 // Validate the SYSm value first.
3983 switch (ValLow) {
3984 case 0: // apsr
3985 case 1: // iapsr
3986 case 2: // eapsr
3987 case 3: // xpsr
3988 case 5: // ipsr
3989 case 6: // epsr
3990 case 7: // iepsr
3991 case 8: // msp
3992 case 9: // psp
3993 case 16: // primask
3994 case 20: // control
3995 break;
3996 case 17: // basepri
3997 case 18: // basepri_max
3998 case 19: // faultmask
3999 if (!(FeatureBits[ARM::HasV7Ops]))
4000 // Values basepri, basepri_max and faultmask are only valid for v7m.
4001 return MCDisassembler::Fail;
4002 break;
4003 case 0x8a: // msplim_ns
4004 case 0x8b: // psplim_ns
4005 case 0x91: // basepri_ns
4006 case 0x93: // faultmask_ns
4007 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4008 return MCDisassembler::Fail;
4009 [[fallthrough]];
4010 case 10: // msplim
4011 case 11: // psplim
4012 case 0x88: // msp_ns
4013 case 0x89: // psp_ns
4014 case 0x90: // primask_ns
4015 case 0x94: // control_ns
4016 case 0x98: // sp_ns
4017 if (!(FeatureBits[ARM::Feature8MSecExt]))
4018 return MCDisassembler::Fail;
4019 break;
4020 case 0x20: // pac_key_p_0
4021 case 0x21: // pac_key_p_1
4022 case 0x22: // pac_key_p_2
4023 case 0x23: // pac_key_p_3
4024 case 0x24: // pac_key_u_0
4025 case 0x25: // pac_key_u_1
4026 case 0x26: // pac_key_u_2
4027 case 0x27: // pac_key_u_3
4028 case 0xa0: // pac_key_p_0_ns
4029 case 0xa1: // pac_key_p_1_ns
4030 case 0xa2: // pac_key_p_2_ns
4031 case 0xa3: // pac_key_p_3_ns
4032 case 0xa4: // pac_key_u_0_ns
4033 case 0xa5: // pac_key_u_1_ns
4034 case 0xa6: // pac_key_u_2_ns
4035 case 0xa7: // pac_key_u_3_ns
4036 if (!(FeatureBits[ARM::FeaturePACBTI]))
4037 return MCDisassembler::Fail;
4038 break;
4039 default:
4040 // Architecturally defined as unpredictable
4042 break;
4043 }
4044
4045 if (Inst.getOpcode() == ARM::t2MSR_M) {
4046 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4047 if (!(FeatureBits[ARM::HasV7Ops])) {
4048 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4049 // unpredictable.
4050 if (Mask != 2)
4052 }
4053 else {
4054 // The ARMv7-M architecture stores an additional 2-bit mask value in
4055 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4056 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4057 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4058 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4059 // only if the processor includes the DSP extension.
4060 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4061 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4063 }
4064 }
4065 } else {
4066 // A/R class
4067 if (Val == 0)
4068 return MCDisassembler::Fail;
4069 }
4071 return S;
4072}
4073
4074static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4075 uint64_t Address,
4076 const MCDisassembler *Decoder) {
4077 unsigned R = fieldFromInstruction(Val, 5, 1);
4078 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4079
4080 // The table of encodings for these banked registers comes from B9.2.3 of the
4081 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4082 // neater. So by fiat, these values are UNPREDICTABLE:
4083 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4084 return MCDisassembler::Fail;
4085
4088}
4089
4090static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4091 uint64_t Address,
4092 const MCDisassembler *Decoder) {
4094
4095 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4096 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4097 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4098
4099 if (Rn == 0xF)
4101
4102 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4103 return MCDisassembler::Fail;
4104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4105 return MCDisassembler::Fail;
4106 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4107 return MCDisassembler::Fail;
4108
4109 return S;
4110}
4111
4112static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4113 uint64_t Address,
4114 const MCDisassembler *Decoder) {
4116
4117 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4118 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4119 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4120 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4121
4122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4123 return MCDisassembler::Fail;
4124
4125 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4127
4128 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4129 return MCDisassembler::Fail;
4130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4131 return MCDisassembler::Fail;
4132 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4133 return MCDisassembler::Fail;
4134
4135 return S;
4136}
4137
4138static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4139 uint64_t Address,
4140 const MCDisassembler *Decoder) {
4142
4143 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4144 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4145 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4146 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4147 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4148 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4149
4150 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4151
4152 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4153 return MCDisassembler::Fail;
4154 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4155 return MCDisassembler::Fail;
4156 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4157 return MCDisassembler::Fail;
4158 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4159 return MCDisassembler::Fail;
4160
4161 return S;
4162}
4163
4164static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4165 uint64_t Address,
4166 const MCDisassembler *Decoder) {
4168
4169 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4170 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4171 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4172 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4173 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4174 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4175 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4176
4177 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4178 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4179
4180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4181 return MCDisassembler::Fail;
4182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4183 return MCDisassembler::Fail;
4184 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4185 return MCDisassembler::Fail;
4186 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4187 return MCDisassembler::Fail;
4188
4189 return S;
4190}
4191
4192static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4193 uint64_t Address,
4194 const MCDisassembler *Decoder) {
4196
4197 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4198 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4199 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4200 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4201 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4202 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4203
4204 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4205
4206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4207 return MCDisassembler::Fail;
4208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4209 return MCDisassembler::Fail;
4210 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4211 return MCDisassembler::Fail;
4212 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4213 return MCDisassembler::Fail;
4214
4215 return S;
4216}
4217
4218static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4219 uint64_t Address,
4220 const MCDisassembler *Decoder) {
4222
4223 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4224 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4225 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4226 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4227 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4228 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4229
4230 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4231
4232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4233 return MCDisassembler::Fail;
4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4235 return MCDisassembler::Fail;
4236 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4237 return MCDisassembler::Fail;
4238 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4239 return MCDisassembler::Fail;
4240
4241 return S;
4242}
4243
4244static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4245 const MCDisassembler *Decoder) {
4247
4248 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4249 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4250 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4251 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4252 unsigned size = fieldFromInstruction(Insn, 10, 2);
4253
4254 unsigned align = 0;
4255 unsigned index = 0;
4256 switch (size) {
4257 default:
4258 return MCDisassembler::Fail;
4259 case 0:
4260 if (fieldFromInstruction(Insn, 4, 1))
4261 return MCDisassembler::Fail; // UNDEFINED
4262 index = fieldFromInstruction(Insn, 5, 3);
4263 break;
4264 case 1:
4265 if (fieldFromInstruction(Insn, 5, 1))
4266 return MCDisassembler::Fail; // UNDEFINED
4267 index = fieldFromInstruction(Insn, 6, 2);
4268 if (fieldFromInstruction(Insn, 4, 1))
4269 align = 2;
4270 break;
4271 case 2:
4272 if (fieldFromInstruction(Insn, 6, 1))
4273 return MCDisassembler::Fail; // UNDEFINED
4274 index = fieldFromInstruction(Insn, 7, 1);
4275
4276 switch (fieldFromInstruction(Insn, 4, 2)) {
4277 case 0 :
4278 align = 0; break;
4279 case 3:
4280 align = 4; break;
4281 default:
4282 return MCDisassembler::Fail;
4283 }
4284 break;
4285 }
4286
4287 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4288 return MCDisassembler::Fail;
4289 if (Rm != 0xF) { // Writeback
4290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4291 return MCDisassembler::Fail;
4292 }
4293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4294 return MCDisassembler::Fail;
4295 Inst.addOperand(MCOperand::createImm(align));
4296 if (Rm != 0xF) {
4297 if (Rm != 0xD) {
4298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4299 return MCDisassembler::Fail;
4300 } else
4302 }
4303
4304 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4305 return MCDisassembler::Fail;
4306 Inst.addOperand(MCOperand::createImm(index));
4307
4308 return S;
4309}
4310
4311static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4312 const MCDisassembler *Decoder) {
4314
4315 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4316 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4317 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4318 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4319 unsigned size = fieldFromInstruction(Insn, 10, 2);
4320
4321 unsigned align = 0;
4322 unsigned index = 0;
4323 switch (size) {
4324 default:
4325 return MCDisassembler::Fail;
4326 case 0:
4327 if (fieldFromInstruction(Insn, 4, 1))
4328 return MCDisassembler::Fail; // UNDEFINED
4329 index = fieldFromInstruction(Insn, 5, 3);
4330 break;
4331 case 1:
4332 if (fieldFromInstruction(Insn, 5, 1))
4333 return MCDisassembler::Fail; // UNDEFINED
4334 index = fieldFromInstruction(Insn, 6, 2);
4335 if (fieldFromInstruction(Insn, 4, 1))
4336 align = 2;
4337 break;
4338 case 2:
4339 if (fieldFromInstruction(Insn, 6, 1))
4340 return MCDisassembler::Fail; // UNDEFINED
4341 index = fieldFromInstruction(Insn, 7, 1);
4342
4343 switch (fieldFromInstruction(Insn, 4, 2)) {
4344 case 0:
4345 align = 0; break;
4346 case 3:
4347 align = 4; break;
4348 default:
4349 return MCDisassembler::Fail;
4350 }
4351 break;
4352 }
4353
4354 if (Rm != 0xF) { // Writeback
4355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4356 return MCDisassembler::Fail;
4357 }
4358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4359 return MCDisassembler::Fail;
4360 Inst.addOperand(MCOperand::createImm(align));
4361 if (Rm != 0xF) {
4362 if (Rm != 0xD) {
4363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4364 return MCDisassembler::Fail;
4365 } else
4367 }
4368
4369 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4370 return MCDisassembler::Fail;
4371 Inst.addOperand(MCOperand::createImm(index));
4372
4373 return S;
4374}
4375
4376static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4377 const MCDisassembler *Decoder) {
4379
4380 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4381 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4382 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4383 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4384 unsigned size = fieldFromInstruction(Insn, 10, 2);
4385
4386 unsigned align = 0;
4387 unsigned index = 0;
4388 unsigned inc = 1;
4389 switch (size) {
4390 default:
4391 return MCDisassembler::Fail;
4392 case 0:
4393 index = fieldFromInstruction(Insn, 5, 3);
4394 if (fieldFromInstruction(Insn, 4, 1))
4395 align = 2;
4396 break;
4397 case 1:
4398 index = fieldFromInstruction(Insn, 6, 2);
4399 if (fieldFromInstruction(Insn, 4, 1))
4400 align = 4;
4401 if (fieldFromInstruction(Insn, 5, 1))
4402 inc = 2;
4403 break;
4404 case 2:
4405 if (fieldFromInstruction(Insn, 5, 1))
4406 return MCDisassembler::Fail; // UNDEFINED
4407 index = fieldFromInstruction(Insn, 7, 1);
4408 if (fieldFromInstruction(Insn, 4, 1) != 0)
4409 align = 8;
4410 if (fieldFromInstruction(Insn, 6, 1))
4411 inc = 2;
4412 break;
4413 }
4414
4415 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4416 return MCDisassembler::Fail;
4417 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4418 return MCDisassembler::Fail;
4419 if (Rm != 0xF) { // Writeback
4420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4421 return MCDisassembler::Fail;
4422 }
4423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4424 return MCDisassembler::Fail;
4425 Inst.addOperand(MCOperand::createImm(align));
4426 if (Rm != 0xF) {
4427 if (Rm != 0xD) {
4428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4429 return MCDisassembler::Fail;
4430 } else
4432 }
4433
4434 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4435 return MCDisassembler::Fail;
4436 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4437 return MCDisassembler::Fail;
4438 Inst.addOperand(MCOperand::createImm(index));
4439
4440 return S;
4441}
4442
4443static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4444 const MCDisassembler *Decoder) {
4446
4447 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4448 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4449 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4450 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4451 unsigned size = fieldFromInstruction(Insn, 10, 2);
4452
4453 unsigned align = 0;
4454 unsigned index = 0;
4455 unsigned inc = 1;
4456 switch (size) {
4457 default:
4458 return MCDisassembler::Fail;
4459 case 0:
4460 index = fieldFromInstruction(Insn, 5, 3);
4461 if (fieldFromInstruction(Insn, 4, 1))
4462 align = 2;
4463 break;
4464 case 1:
4465 index = fieldFromInstruction(Insn, 6, 2);
4466 if (fieldFromInstruction(Insn, 4, 1))
4467 align = 4;
4468 if (fieldFromInstruction(Insn, 5, 1))
4469 inc = 2;
4470 break;
4471 case 2:
4472 if (fieldFromInstruction(Insn, 5, 1))
4473 return MCDisassembler::Fail; // UNDEFINED
4474 index = fieldFromInstruction(Insn, 7, 1);
4475 if (fieldFromInstruction(Insn, 4, 1) != 0)
4476 align = 8;
4477 if (fieldFromInstruction(Insn, 6, 1))
4478 inc = 2;
4479 break;
4480 }
4481
4482 if (Rm != 0xF) { // Writeback
4483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4484 return MCDisassembler::Fail;
4485 }
4486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4487 return MCDisassembler::Fail;
4488 Inst.addOperand(MCOperand::createImm(align));
4489 if (Rm != 0xF) {
4490 if (Rm != 0xD) {
4491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4492 return MCDisassembler::Fail;
4493 } else
4495 }
4496
4497 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4498 return MCDisassembler::Fail;
4499 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4500 return MCDisassembler::Fail;
4501 Inst.addOperand(MCOperand::createImm(index));
4502
4503 return S;
4504}
4505
4506static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4507 const MCDisassembler *Decoder) {
4509
4510 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4511 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4512 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4513 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4514 unsigned size = fieldFromInstruction(Insn, 10, 2);
4515
4516 unsigned align = 0;
4517 unsigned index = 0;
4518 unsigned inc = 1;
4519 switch (size) {
4520 default:
4521 return MCDisassembler::Fail;
4522 case 0:
4523 if (fieldFromInstruction(Insn, 4, 1))
4524 return MCDisassembler::Fail; // UNDEFINED
4525 index = fieldFromInstruction(Insn, 5, 3);
4526 break;
4527 case 1:
4528 if (fieldFromInstruction(Insn, 4, 1))
4529 return MCDisassembler::Fail; // UNDEFINED
4530 index = fieldFromInstruction(Insn, 6, 2);
4531 if (fieldFromInstruction(Insn, 5, 1))
4532 inc = 2;
4533 break;
4534 case 2:
4535 if (fieldFromInstruction(Insn, 4, 2))
4536 return MCDisassembler::Fail; // UNDEFINED
4537 index = fieldFromInstruction(Insn, 7, 1);
4538 if (fieldFromInstruction(Insn, 6, 1))
4539 inc = 2;
4540 break;
4541 }
4542
4543 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4544 return MCDisassembler::Fail;
4545 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4546 return MCDisassembler::Fail;
4547 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4548 return MCDisassembler::Fail;
4549
4550 if (Rm != 0xF) { // Writeback
4551 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4552 return MCDisassembler::Fail;
4553 }
4554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4555 return MCDisassembler::Fail;
4556 Inst.addOperand(MCOperand::createImm(align));
4557 if (Rm != 0xF) {
4558 if (Rm != 0xD) {
4559 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4560 return MCDisassembler::Fail;
4561 } else
4563 }
4564
4565 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4566 return MCDisassembler::Fail;
4567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4568 return MCDisassembler::Fail;
4569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4570 return MCDisassembler::Fail;
4571 Inst.addOperand(MCOperand::createImm(index));
4572
4573 return S;
4574}
4575
4576static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4577 const MCDisassembler *Decoder) {
4579
4580 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4581 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4582 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4583 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4584 unsigned size = fieldFromInstruction(Insn, 10, 2);
4585
4586 unsigned align = 0;
4587 unsigned index = 0;
4588 unsigned inc = 1;
4589 switch (size) {
4590 default:
4591 return MCDisassembler::Fail;
4592 case 0:
4593 if (fieldFromInstruction(Insn, 4, 1))
4594 return MCDisassembler::Fail; // UNDEFINED
4595 index = fieldFromInstruction(Insn, 5, 3);
4596 break;
4597 case 1:
4598 if (fieldFromInstruction(Insn, 4, 1))
4599 return MCDisassembler::Fail; // UNDEFINED
4600 index = fieldFromInstruction(Insn, 6, 2);
4601 if (fieldFromInstruction(Insn, 5, 1))
4602 inc = 2;
4603 break;
4604 case 2:
4605 if (fieldFromInstruction(Insn, 4, 2))
4606 return MCDisassembler::Fail; // UNDEFINED
4607 index = fieldFromInstruction(Insn, 7, 1);
4608 if (fieldFromInstruction(Insn, 6, 1))
4609 inc = 2;
4610 break;
4611 }
4612
4613 if (Rm != 0xF) { // Writeback
4614 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4615 return MCDisassembler::Fail;
4616 }
4617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4618 return MCDisassembler::Fail;
4619 Inst.addOperand(MCOperand::createImm(align));
4620 if (Rm != 0xF) {
4621 if (Rm != 0xD) {
4622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4623 return MCDisassembler::Fail;
4624 } else
4626 }
4627
4628 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4629 return MCDisassembler::Fail;
4630 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4631 return MCDisassembler::Fail;
4632 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4633 return MCDisassembler::Fail;
4634 Inst.addOperand(MCOperand::createImm(index));
4635
4636 return S;
4637}
4638
4639static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4640 const MCDisassembler *Decoder) {
4642
4643 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4644 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4645 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4646 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4647 unsigned size = fieldFromInstruction(Insn, 10, 2);
4648
4649 unsigned align = 0;
4650 unsigned index = 0;
4651 unsigned inc = 1;
4652 switch (size) {
4653 default:
4654 return MCDisassembler::Fail;
4655 case 0:
4656 if (fieldFromInstruction(Insn, 4, 1))
4657 align = 4;
4658 index = fieldFromInstruction(Insn, 5, 3);
4659 break;
4660 case 1:
4661 if (fieldFromInstruction(Insn, 4, 1))
4662 align = 8;
4663 index = fieldFromInstruction(Insn, 6, 2);
4664 if (fieldFromInstruction(Insn, 5, 1))
4665 inc = 2;
4666 break;
4667 case 2:
4668 switch (fieldFromInstruction(Insn, 4, 2)) {
4669 case 0:
4670 align = 0; break;
4671 case 3:
4672 return MCDisassembler::Fail;
4673 default:
4674 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4675 }
4676
4677 index = fieldFromInstruction(Insn, 7, 1);
4678 if (fieldFromInstruction(Insn, 6, 1))
4679 inc = 2;
4680 break;
4681 }
4682
4683 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4684 return MCDisassembler::Fail;
4685 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4686 return MCDisassembler::Fail;
4687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4688 return MCDisassembler::Fail;
4689 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4690 return MCDisassembler::Fail;
4691
4692 if (Rm != 0xF) { // Writeback
4693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4694 return MCDisassembler::Fail;
4695 }
4696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4697 return MCDisassembler::Fail;
4698 Inst.addOperand(MCOperand::createImm(align));
4699 if (Rm != 0xF) {
4700 if (Rm != 0xD) {
4701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4702 return MCDisassembler::Fail;
4703 } else
4705 }
4706
4707 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4708 return MCDisassembler::Fail;
4709 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4710 return MCDisassembler::Fail;
4711 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4712 return MCDisassembler::Fail;
4713 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4714 return MCDisassembler::Fail;
4715 Inst.addOperand(MCOperand::createImm(index));
4716
4717 return S;
4718}
4719
4720static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4721 const MCDisassembler *Decoder) {
4723
4724 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4725 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4726 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4727 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4728 unsigned size = fieldFromInstruction(Insn, 10, 2);
4729
4730 unsigned align = 0;
4731 unsigned index = 0;
4732 unsigned inc = 1;
4733 switch (size) {
4734 default:
4735 return MCDisassembler::Fail;
4736 case 0:
4737 if (fieldFromInstruction(Insn, 4, 1))
4738 align = 4;
4739 index = fieldFromInstruction(Insn, 5, 3);
4740 break;
4741 case 1:
4742 if (fieldFromInstruction(Insn, 4, 1))
4743 align = 8;
4744 index = fieldFromInstruction(Insn, 6, 2);
4745 if (fieldFromInstruction(Insn, 5, 1))
4746 inc = 2;
4747 break;
4748 case 2:
4749 switch (fieldFromInstruction(Insn, 4, 2)) {
4750 case 0:
4751 align = 0; break;
4752 case 3:
4753 return MCDisassembler::Fail;
4754 default:
4755 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4756 }
4757
4758 index = fieldFromInstruction(Insn, 7, 1);
4759 if (fieldFromInstruction(Insn, 6, 1))
4760 inc = 2;
4761 break;
4762 }
4763
4764 if (Rm != 0xF) { // Writeback
4765 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4766 return MCDisassembler::Fail;
4767 }
4768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4769 return MCDisassembler::Fail;
4770 Inst.addOperand(MCOperand::createImm(align));
4771 if (Rm != 0xF) {
4772 if (Rm != 0xD) {
4773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4774 return MCDisassembler::Fail;
4775 } else
4777 }
4778
4779 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4780 return MCDisassembler::Fail;
4781 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4782 return MCDisassembler::Fail;
4783 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4784 return MCDisassembler::Fail;
4785 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4786 return MCDisassembler::Fail;
4787 Inst.addOperand(MCOperand::createImm(index));
4788
4789 return S;
4790}
4791
4792static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
4793 const MCDisassembler *Decoder) {
4795 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4796 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4797 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4798 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4799 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4800
4801 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4803
4804 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4805 return MCDisassembler::Fail;
4806 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4807 return MCDisassembler::Fail;
4808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4809 return MCDisassembler::Fail;
4810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4811 return MCDisassembler::Fail;
4812 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4813 return MCDisassembler::Fail;
4814
4815 return S;
4816}
4817
4818static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
4819 const MCDisassembler *Decoder) {
4821 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4822 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4823 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4824 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4825 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4826
4827 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4829
4830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4831 return MCDisassembler::Fail;
4832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4833 return MCDisassembler::Fail;
4834 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4835 return MCDisassembler::Fail;
4836 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4837 return MCDisassembler::Fail;
4838 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4839 return MCDisassembler::Fail;
4840
4841 return S;
4842}
4843
4844static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address,
4845 const MCDisassembler *Decoder) {
4847 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4848 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4849
4850 if (pred == 0xF) {
4851 pred = 0xE;
4853 }
4854
4855 if (mask == 0x0)
4856 return MCDisassembler::Fail;
4857
4858 // IT masks are encoded as a sequence of replacement low-order bits
4859 // for the condition code. So if the low bit of the starting
4860 // condition code is 1, then we have to flip all the bits above the
4861 // terminating bit (which is the lowest 1 bit).
4862 if (pred & 1) {
4863 unsigned LowBit = mask & -mask;
4864 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
4865 mask ^= BitsAboveLowBit;
4866 }
4867
4868 Inst.addOperand(MCOperand::createImm(pred));
4869 Inst.addOperand(MCOperand::createImm(mask));
4870 return S;
4871}
4872
4874 uint64_t Address,
4875 const MCDisassembler *Decoder) {
4877
4878 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4879 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4880 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4881 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4882 unsigned W = fieldFromInstruction(Insn, 21, 1);
4883 unsigned U = fieldFromInstruction(Insn, 23, 1);
4884 unsigned P = fieldFromInstruction(Insn, 24, 1);
4885 bool writeback = (W == 1) | (P == 0);
4886
4887 addr |= (U << 8) | (Rn << 9);
4888
4889 if (writeback && (Rn == Rt || Rn == Rt2))
4891 if (Rt == Rt2)
4893
4894 // Rt
4895 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4896 return MCDisassembler::Fail;
4897 // Rt2
4898 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4899 return MCDisassembler::Fail;
4900 // Writeback operand
4901 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4902 return MCDisassembler::Fail;
4903 // addr
4904 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4905 return MCDisassembler::Fail;
4906
4907 return S;
4908}
4909
4911 uint64_t Address,
4912 const MCDisassembler *Decoder) {
4914
4915 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4916 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4917 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4918 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4919 unsigned W = fieldFromInstruction(Insn, 21, 1);
4920 unsigned U = fieldFromInstruction(Insn, 23, 1);
4921 unsigned P = fieldFromInstruction(Insn, 24, 1);
4922 bool writeback = (W == 1) | (P == 0);
4923
4924 addr |= (U << 8) | (Rn << 9);
4925
4926 if (writeback && (Rn == Rt || Rn == Rt2))
4928
4929 // Writeback operand
4930 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4931 return MCDisassembler::Fail;
4932 // Rt
4933 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4934 return MCDisassembler::Fail;
4935 // Rt2
4936 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4937 return MCDisassembler::Fail;
4938 // addr
4939 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4940 return MCDisassembler::Fail;
4941
4942 return S;
4943}
4944
4946 const MCDisassembler *Decoder) {
4947 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4948 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4949 if (sign1 != sign2) return MCDisassembler::Fail;
4950 const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
4951 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
4952 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
4953
4954 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4955 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4956 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4957 // If sign, then it is decreasing the address.
4958 if (sign1) {
4959 // Following ARMv7 Architecture Manual, when the offset
4960 // is zero, it is decoded as a subw, not as a adr.w
4961 if (!Val) {
4962 Inst.setOpcode(ARM::t2SUBri12);
4963 Inst.addOperand(MCOperand::createReg(ARM::PC));
4964 } else
4965 Val = -Val;
4966 }
4968 return S;
4969}
4970
4972 uint64_t Address,
4973 const MCDisassembler *Decoder) {
4975
4976 // Shift of "asr #32" is not allowed in Thumb2 mode.
4977 if (Val == 0x20) S = MCDisassembler::Fail;
4979 return S;
4980}
4981
4982static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
4983 const MCDisassembler *Decoder) {
4984 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4985 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4986 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4987 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4988
4989 if (pred == 0xF)
4990 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4991
4993
4994 if (Rt == Rn || Rn == Rt2)
4996
4997 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4998 return MCDisassembler::Fail;
4999 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5000 return MCDisassembler::Fail;
5001 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5002 return MCDisassembler::Fail;
5003 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5004 return MCDisassembler::Fail;
5005
5006 return S;
5007}
5008
5009static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
5010 const MCDisassembler *Decoder) {
5011 const FeatureBitset &featureBits =
5012 Decoder->getSubtargetInfo().getFeatureBits();
5013 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5014
5015 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5016 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5017 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5018 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5019 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5020 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5021 unsigned op = fieldFromInstruction(Insn, 5, 1);
5022
5024
5025 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5026 if (!(imm & 0x38)) {
5027 if (cmode == 0xF) {
5028 if (op == 1) return MCDisassembler::Fail;
5029 Inst.setOpcode(ARM::VMOVv2f32);
5030 }
5031 if (hasFullFP16) {
5032 if (cmode == 0xE) {
5033 if (op == 1) {
5034 Inst.setOpcode(ARM::VMOVv1i64);
5035 } else {
5036 Inst.setOpcode(ARM::VMOVv8i8);
5037 }
5038 }
5039 if (cmode == 0xD) {
5040 if (op == 1) {
5041 Inst.setOpcode(ARM::VMVNv2i32);
5042 } else {
5043 Inst.setOpcode(ARM::VMOVv2i32);
5044 }
5045 }
5046 if (cmode == 0xC) {
5047 if (op == 1) {
5048 Inst.setOpcode(ARM::VMVNv2i32);
5049 } else {
5050 Inst.setOpcode(ARM::VMOVv2i32);
5051 }
5052 }
5053 }
5054 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
5055 }
5056
5057 if (!(imm & 0x20)) return MCDisassembler::Fail;
5058
5059 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5060 return MCDisassembler::Fail;
5061 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5062 return MCDisassembler::Fail;
5063 Inst.addOperand(MCOperand::createImm(64 - imm));
5064
5065 return S;
5066}
5067
5068static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
5069 const MCDisassembler *Decoder) {
5070 const FeatureBitset &featureBits =
5071 Decoder->getSubtargetInfo().getFeatureBits();
5072 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5073
5074 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5075 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5076 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5077 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5078 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5079 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5080 unsigned op = fieldFromInstruction(Insn, 5, 1);
5081
5083
5084 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5085 if (!(imm & 0x38)) {
5086 if (cmode == 0xF) {
5087 if (op == 1) return MCDisassembler::Fail;
5088 Inst.setOpcode(ARM::VMOVv4f32);
5089 }
5090 if (hasFullFP16) {
5091 if (cmode == 0xE) {
5092 if (op == 1) {
5093 Inst.setOpcode(ARM::VMOVv2i64);
5094 } else {
5095 Inst.setOpcode(ARM::VMOVv16i8);
5096 }
5097 }
5098 if (cmode == 0xD) {
5099 if (op == 1) {
5100 Inst.setOpcode(ARM::VMVNv4i32);
5101 } else {
5102 Inst.setOpcode(ARM::VMOVv4i32);
5103 }
5104 }
5105 if (cmode == 0xC) {
5106 if (op == 1) {
5107 Inst.setOpcode(ARM::VMVNv4i32);
5108 } else {
5109 Inst.setOpcode(ARM::VMOVv4i32);
5110 }
5111 }
5112 }
5113 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
5114 }
5115
5116 if (!(imm & 0x20)) return MCDisassembler::Fail;
5117
5118 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5119 return MCDisassembler::Fail;
5120 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5121 return MCDisassembler::Fail;
5122 Inst.addOperand(MCOperand::createImm(64 - imm));
5123
5124 return S;
5125}
5126
5127static DecodeStatus
5129 uint64_t Address,
5130 const MCDisassembler *Decoder) {
5131 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5132 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5133 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
5134 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
5135 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5136 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5137 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
5138 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
5139
5141
5142 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
5143
5144 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5145 return MCDisassembler::Fail;
5146 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5147 return MCDisassembler::Fail;
5148 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
5149 return MCDisassembler::Fail;
5150 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5151 return MCDisassembler::Fail;
5152 // The lane index does not have any bits in the encoding, because it can only
5153 // be 0.
5155 Inst.addOperand(MCOperand::createImm(rotate));
5156
5157 return S;
5158}
5159
5160static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
5161 const MCDisassembler *Decoder) {
5163
5164 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5165 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5166 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5167 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5168 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5169
5170 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5172
5173 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5174 return MCDisassembler::Fail;
5175 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5176 return MCDisassembler::Fail;
5177 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5178 return MCDisassembler::Fail;
5179 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5180 return MCDisassembler::Fail;
5181 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5182 return MCDisassembler::Fail;
5183
5184 return S;
5185}
5186
5188 uint64_t Address,
5189 const MCDisassembler *Decoder) {
5191
5192 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5193 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5194 unsigned cop = fieldFromInstruction(Val, 8, 4);
5195 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5196 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5197
5198 if ((cop & ~0x1) == 0xa)
5199 return MCDisassembler::Fail;
5200
5201 if (Rt == Rt2)
5203
5204 // We have to check if the instruction is MRRC2
5205 // or MCRR2 when constructing the operands for
5206 // Inst. Reason is because MRRC2 stores to two
5207 // registers so it's tablegen desc has two
5208 // outputs whereas MCRR doesn't store to any
5209 // registers so all of it's operands are listed
5210 // as inputs, therefore the operand order for
5211 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5212 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5213
5214 if (Inst.getOpcode() == ARM::MRRC2) {
5215 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5216 return MCDisassembler::Fail;
5217 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5218 return MCDisassembler::Fail;
5219 }
5221 Inst.addOperand(MCOperand::createImm(opc1));
5222 if (Inst.getOpcode() == ARM::MCRR2) {
5223 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5224 return MCDisassembler::Fail;
5225 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5226 return MCDisassembler::Fail;
5227 }
5229
5230 return S;
5231}
5232
5233static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
5234 uint64_t Address,
5235 const MCDisassembler *Decoder) {
5236 const FeatureBitset &featureBits =
5237 Decoder->getSubtargetInfo().getFeatureBits();
5239
5240 // Add explicit operand for the destination sysreg, for cases where
5241 // we have to model it for code generation purposes.
5242 switch (Inst.getOpcode()) {
5243 case ARM::VMSR_FPSCR_NZCVQC:
5244 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5245 break;
5246 case ARM::VMSR_P0:
5247 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5248 break;
5249 }
5250
5251 if (Inst.getOpcode() != ARM::FMSTAT) {
5252 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5253
5254 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5255 if (Rt == 13 || Rt == 15)
5257 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
5258 } else
5259 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
5260 }
5261
5262 // Add explicit operand for the source sysreg, similarly to above.
5263 switch (Inst.getOpcode()) {
5264 case ARM::VMRS_FPSCR_NZCVQC:
5265 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5266 break;
5267 case ARM::VMRS_P0:
5268 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5269 break;
5270 }
5271
5272 if (featureBits[ARM::ModeThumb]) {
5275 } else {
5276 unsigned pred = fieldFromInstruction(Val, 28, 4);
5277 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5278 return MCDisassembler::Fail;
5279 }
5280
5281 return S;
5282}
5283
5284template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
5285static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
5286 uint64_t Address,
5287 const MCDisassembler *Decoder) {
5289 if (Val == 0 && !zeroPermitted)
5291
5292 uint64_t DecVal;
5293 if (isSigned)
5294 DecVal = SignExtend32<size + 1>(Val << 1);
5295 else
5296 DecVal = (Val << 1);
5297
5298 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
5299 Decoder))
5300 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));
5301 return S;
5302}
5303
5305 uint64_t Address,
5306 const MCDisassembler *Decoder) {
5307
5308 uint64_t LocImm = Inst.getOperand(0).getImm();
5309 Val = LocImm + (2 << Val);
5310 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
5311 Decoder))
5314}
5315
5316static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
5317 uint64_t Address,
5318 const MCDisassembler *Decoder) {
5319 if (Val >= ARMCC::AL) // also exclude the non-condition NV
5320 return MCDisassembler::Fail;
5323}
5324
5325static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
5326 const MCDisassembler *Decoder) {
5328
5329 if (Inst.getOpcode() == ARM::MVE_LCTP)
5330 return S;
5331
5332 unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
5333 fieldFromInstruction(Insn, 1, 10) << 1;
5334 switch (Inst.getOpcode()) {
5335 case ARM::t2LEUpdate:
5336 case ARM::MVE_LETP:
5337 Inst.addOperand(MCOperand::createReg(ARM::LR));
5338 Inst.addOperand(MCOperand::createReg(ARM::LR));
5339 [[fallthrough]];
5340 case ARM::t2LE:
5342 Inst, Imm, Address, Decoder)))
5343 return MCDisassembler::Fail;
5344 break;
5345 case ARM::t2WLS:
5346 case ARM::MVE_WLSTP_8:
5347 case ARM::MVE_WLSTP_16:
5348 case ARM::MVE_WLSTP_32:
5349 case ARM::MVE_WLSTP_64:
5350 Inst.addOperand(MCOperand::createReg(ARM::LR));
5351 if (!Check(S,
5353 Address, Decoder)) ||
5355 Inst, Imm, Address, Decoder)))
5356 return MCDisassembler::Fail;
5357 break;
5358 case ARM::t2DLS:
5359 case ARM::MVE_DLSTP_8:
5360 case ARM::MVE_DLSTP_16:
5361 case ARM::MVE_DLSTP_32:
5362 case ARM::MVE_DLSTP_64:
5363 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5364 if (Rn == 0xF) {
5365 // Enforce all the rest of the instruction bits in LCTP, which
5366 // won't have been reliably checked based on LCTP's own tablegen
5367 // record, because we came to this decode by a roundabout route.
5368 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
5369 if ((Insn & ~SBZMask) != CanonicalLCTP)
5370 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail
5371 if (Insn != CanonicalLCTP)
5372 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
5373
5374 Inst.setOpcode(ARM::MVE_LCTP);
5375 } else {
5376 Inst.addOperand(MCOperand::createReg(ARM::LR));
5377 if (!Check(S, DecoderGPRRegisterClass(Inst,
5378 fieldFromInstruction(Insn, 16, 4),
5379 Address, Decoder)))
5380 return MCDisassembler::Fail;
5381 }
5382 break;
5383 }
5384 return S;
5385}
5386
5387static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
5388 uint64_t Address,
5389 const MCDisassembler *Decoder) {
5391
5392 if (Val == 0)
5393 Val = 32;
5394
5396
5397 return S;
5398}
5399
5401 uint64_t Address,
5402 const MCDisassembler *Decoder) {
5403 if ((RegNo) + 1 > 11)
5404 return MCDisassembler::Fail;
5405
5406 unsigned Register = GPRDecoderTable[(RegNo) + 1];
5409}
5410
5412 uint64_t Address,
5413 const MCDisassembler *Decoder) {
5414 if ((RegNo) > 14)
5415 return MCDisassembler::Fail;
5416
5417 unsigned Register = GPRDecoderTable[(RegNo)];
5420}
5421
5422static DecodeStatus
5424 uint64_t Address,
5425 const MCDisassembler *Decoder) {
5426 if (RegNo == 15) {
5427 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
5429 }
5430
5431 unsigned Register = GPRDecoderTable[RegNo];
5433
5434 if (RegNo == 13)
5436
5438}
5439
5440static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
5441 const MCDisassembler *Decoder) {
5443
5446 unsigned regs = fieldFromInstruction(Insn, 0, 8);
5447 if (regs == 0) {
5448 // Register list contains only VPR
5449 } else if (Inst.getOpcode() == ARM::VSCCLRMD) {
5450 unsigned reglist = regs | (fieldFromInstruction(Insn, 12, 4) << 8) |
5451 (fieldFromInstruction(Insn, 22, 1) << 12);
5452 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {
5453 return MCDisassembler::Fail;
5454 }
5455 } else {
5456 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 1) |
5457 fieldFromInstruction(Insn, 22, 1);
5458 // Registers past s31 are permitted and treated as being half of a d
5459 // register, though both halves of each d register must be present.
5460 unsigned max_reg = Vd + regs;
5461 if (max_reg > 64 || (max_reg > 32 && (max_reg & 1)))
5463 unsigned max_sreg = std::min(32u, max_reg);
5464 unsigned max_dreg = std::min(32u, max_reg / 2);
5465 for (unsigned i = Vd; i < max_sreg; ++i)
5466 if (!Check(S, DecodeSPRRegisterClass(Inst, i, Address, Decoder)))
5467 return MCDisassembler::Fail;
5468 for (unsigned i = 16; i < max_dreg; ++i)
5469 if (!Check(S, DecodeDPRRegisterClass(Inst, i, Address, Decoder)))
5470 return MCDisassembler::Fail;
5471 }
5472 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5473
5474 return S;
5475}
5476
5477static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
5478 uint64_t Address,
5479 const MCDisassembler *Decoder) {
5481
5482 // Parse VPT mask and encode it in the MCInst as an immediate with the same
5483 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and
5484 // 't' as 0 and finish with a 1.
5485 unsigned Imm = 0;
5486 // We always start with a 't'.
5487 unsigned CurBit = 0;
5488 for (int i = 3; i >= 0; --i) {
5489 // If the bit we are looking at is not the same as last one, invert the
5490 // CurBit, if it is the same leave it as is.
5491 CurBit ^= (Val >> i) & 1U;
5492
5493 // Encode the CurBit at the right place in the immediate.
5494 Imm |= (CurBit << i);
5495
5496 // If we are done, finish the encoding with a 1.
5497 if ((Val & ~(~0U << i)) == 0) {
5498 Imm |= 1U << i;
5499 break;
5500 }
5501 }
5502
5504
5505 return S;
5506}
5507
5508static DecodeStatus
5510 const MCDisassembler *Decoder) {
5511 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
5513}
5514
5515static DecodeStatus
5517 const MCDisassembler *Decoder) {
5518 unsigned Code;
5519 switch (Val & 0x3) {
5520 case 0:
5521 Code = ARMCC::GE;
5522 break;
5523 case 1:
5524 Code = ARMCC::LT;
5525 break;
5526 case 2:
5527 Code = ARMCC::GT;
5528 break;
5529 case 3:
5530 Code = ARMCC::LE;
5531 break;
5532 }
5533 Inst.addOperand(MCOperand::createImm(Code));
5535}
5536
5537static DecodeStatus
5539 const MCDisassembler *Decoder) {
5540 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));
5542}
5543
5544static DecodeStatus
5546 const MCDisassembler *Decoder) {
5547 unsigned Code;
5548 switch (Val) {
5549 default:
5550 return MCDisassembler::Fail;
5551 case 0:
5552 Code = ARMCC::EQ;
5553 break;
5554 case 1:
5555 Code = ARMCC::NE;
5556 break;
5557 case 4:
5558 Code = ARMCC::GE;
5559 break;
5560 case 5:
5561 Code = ARMCC::LT;
5562 break;
5563 case 6:
5564 Code = ARMCC::GT;
5565 break;
5566 case 7:
5567 Code = ARMCC::LE;
5568 break;
5569 }
5570
5571 Inst.addOperand(MCOperand::createImm(Code));
5573}
5574
5575static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
5576 uint64_t Address,
5577 const MCDisassembler *Decoder) {
5579
5580 unsigned DecodedVal = 64 - Val;
5581
5582 switch (Inst.getOpcode()) {
5583 case ARM::MVE_VCVTf16s16_fix:
5584 case ARM::MVE_VCVTs16f16_fix:
5585 case ARM::MVE_VCVTf16u16_fix:
5586 case ARM::MVE_VCVTu16f16_fix:
5587 if (DecodedVal > 16)
5588 return MCDisassembler::Fail;
5589 break;
5590 case ARM::MVE_VCVTf32s32_fix:
5591 case ARM::MVE_VCVTs32f32_fix:
5592 case ARM::MVE_VCVTf32u32_fix:
5593 case ARM::MVE_VCVTu32f32_fix:
5594 if (DecodedVal > 32)
5595 return MCDisassembler::Fail;
5596 break;
5597 }
5598
5599 Inst.addOperand(MCOperand::createImm(64 - Val));
5600
5601 return S;
5602}
5603
5604static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
5605 switch (Opcode) {
5606 case ARM::VSTR_P0_off:
5607 case ARM::VSTR_P0_pre:
5608 case ARM::VSTR_P0_post:
5609 case ARM::VLDR_P0_off:
5610 case ARM::VLDR_P0_pre:
5611 case ARM::VLDR_P0_post:
5612 return ARM::P0;
5613 case ARM::VSTR_FPSCR_NZCVQC_off:
5614 case ARM::VSTR_FPSCR_NZCVQC_pre:
5615 case ARM::VSTR_FPSCR_NZCVQC_post:
5616 case ARM::VLDR_FPSCR_NZCVQC_off:
5617 case ARM::VLDR_FPSCR_NZCVQC_pre:
5618 case ARM::VLDR_FPSCR_NZCVQC_post:
5619 return ARM::FPSCR;
5620 default:
5621 return 0;
5622 }
5623}
5624
5625template <bool Writeback>
5626static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
5627 uint64_t Address,
5628 const MCDisassembler *Decoder) {
5629 switch (Inst.getOpcode()) {
5630 case ARM::VSTR_FPSCR_pre:
5631 case ARM::VSTR_FPSCR_NZCVQC_pre:
5632 case ARM::VLDR_FPSCR_pre:
5633 case ARM::VLDR_FPSCR_NZCVQC_pre:
5634 case ARM::VSTR_FPSCR_off:
5635 case ARM::VSTR_FPSCR_NZCVQC_off:
5636 case ARM::VLDR_FPSCR_off:
5637 case ARM::VLDR_FPSCR_NZCVQC_off:
5638 case ARM::VSTR_FPSCR_post:
5639 case ARM::VSTR_FPSCR_NZCVQC_post:
5640 case ARM::VLDR_FPSCR_post:
5641 case ARM::VLDR_FPSCR_NZCVQC_post:
5642 const FeatureBitset &featureBits =
5643 Decoder->getSubtargetInfo().getFeatureBits();
5644
5645 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
5646 return MCDisassembler::Fail;
5647 }
5648
5650 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
5651 Inst.addOperand(MCOperand::createReg(Sysreg));
5652 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5653 unsigned addr = fieldFromInstruction(Val, 0, 7) |
5654 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
5655
5656 if (Writeback) {
5657 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5658 return MCDisassembler::Fail;
5659 }
5660 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
5661 return MCDisassembler::Fail;
5662
5665
5666 return S;
5667}
5668
5669static inline DecodeStatus
5670DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address,
5671 const MCDisassembler *Decoder, unsigned Rn,
5672 OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
5674
5675 unsigned Qd = fieldFromInstruction(Val, 13, 3);
5676 unsigned addr = fieldFromInstruction(Val, 0, 7) |
5677 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
5678
5679 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
5680 return MCDisassembler::Fail;
5681 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
5682 return MCDisassembler::Fail;
5683 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
5684 return MCDisassembler::Fail;
5685
5686 Check(S, DecodeVpredNOperand(Inst, Decoder));
5687 return S;
5688}
5689
5690template <int shift>
5691static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
5692 uint64_t Address,
5693 const MCDisassembler *Decoder) {
5694 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
5695 fieldFromInstruction(Val, 16, 3),
5698}
5699
5700template <int shift>
5701static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
5702 uint64_t Address,
5703 const MCDisassembler *Decoder) {
5704 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
5705 fieldFromInstruction(Val, 16, 4),
5708}
5709
5710template <int shift>
5711static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
5712 uint64_t Address,
5713 const MCDisassembler *Decoder) {
5714 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
5715 fieldFromInstruction(Val, 17, 3),
5718}
5719
5720template <unsigned MinLog, unsigned MaxLog>
5721static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
5722 uint64_t Address,
5723 const MCDisassembler *Decoder) {
5725
5726 if (Val < MinLog || Val > MaxLog)
5727 return MCDisassembler::Fail;
5728
5729 Inst.addOperand(MCOperand::createImm(1LL << Val));
5730 return S;
5731}
5732
5733template <unsigned start>
5734static DecodeStatus
5736 const MCDisassembler *Decoder) {
5738
5739 Inst.addOperand(MCOperand::createImm(start + Val));
5740
5741 return S;
5742}
5743
5744static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
5745 uint64_t Address,
5746 const MCDisassembler *Decoder) {
5748 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
5749 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5750 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
5751 fieldFromInstruction(Insn, 13, 3));
5752 unsigned index = fieldFromInstruction(Insn, 4, 1);
5753
5754 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5755 return MCDisassembler::Fail;
5756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5757 return MCDisassembler::Fail;
5758 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
5759 return MCDisassembler::Fail;
5760 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
5761 return MCDisassembler::Fail;
5762 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
5763 return MCDisassembler::Fail;
5764
5765 return S;
5766}
5767
5768static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
5769 uint64_t Address,
5770 const MCDisassembler *Decoder) {
5772 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
5773 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5774 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
5775 fieldFromInstruction(Insn, 13, 3));
5776 unsigned index = fieldFromInstruction(Insn, 4, 1);
5777
5778 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
5779 return MCDisassembler::Fail;
5780 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
5781 return MCDisassembler::Fail;
5782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5783 return MCDisassembler::Fail;
5784 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5785 return MCDisassembler::Fail;
5786 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
5787 return MCDisassembler::Fail;
5788 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
5789 return MCDisassembler::Fail;
5790
5791 return S;
5792}
5793
5794static DecodeStatus
5795DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
5796 const MCDisassembler *Decoder) {
5798
5799 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1;
5800 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1;
5801 unsigned Rm = fieldFromInstruction(Insn, 12, 4);
5802
5803 if (RdaHi == 14) {
5804 // This value of RdaHi (really indicating pc, because RdaHi has to
5805 // be an odd-numbered register, so the low bit will be set by the
5806 // decode function below) indicates that we must decode as SQRSHR
5807 // or UQRSHL, which both have a single Rda register field with all
5808 // four bits.
5809 unsigned Rda = fieldFromInstruction(Insn, 16, 4);
5810
5811 switch (Inst.getOpcode()) {
5812 case ARM::MVE_ASRLr:
5813 case ARM::MVE_SQRSHRL:
5814 Inst.setOpcode(ARM::MVE_SQRSHR);
5815 break;
5816 case ARM::MVE_LSLLr:
5817 case ARM::MVE_UQRSHLL:
5818 Inst.setOpcode(ARM::MVE_UQRSHL);
5819 break;
5820 default:
5821 llvm_unreachable("Unexpected starting opcode!");
5822 }
5823
5824 // Rda as output parameter
5825 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
5826 return MCDisassembler::Fail;
5827
5828 // Rda again as input parameter
5829 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
5830 return MCDisassembler::Fail;
5831
5832 // Rm, the amount to shift by
5833 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
5834 return MCDisassembler::Fail;
5835
5836 if (fieldFromInstruction (Insn, 6, 3) != 4)
5838
5839 if (Rda == Rm)
5841
5842 return S;
5843 }
5844
5845 // Otherwise, we decode as whichever opcode our caller has already
5846 // put into Inst. Those all look the same:
5847
5848 // RdaLo,RdaHi as output parameters
5849 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
5850 return MCDisassembler::Fail;
5851 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
5852 return MCDisassembler::Fail;
5853
5854 // RdaLo,RdaHi again as input parameters
5855 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
5856 return MCDisassembler::Fail;
5857 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
5858 return MCDisassembler::Fail;
5859
5860 // Rm, the amount to shift by
5861 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
5862 return MCDisassembler::Fail;
5863
5864 if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
5865 Inst.getOpcode() == ARM::MVE_UQRSHLL) {
5866 unsigned Saturate = fieldFromInstruction(Insn, 7, 1);
5867 // Saturate, the bit position for saturation
5868 Inst.addOperand(MCOperand::createImm(Saturate));
5869 }
5870
5871 return S;
5872}
5873
5874static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
5875 uint64_t Address,
5876 const MCDisassembler *Decoder) {
5878 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
5879 fieldFromInstruction(Insn, 13, 3));
5880 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |
5881 fieldFromInstruction(Insn, 1, 3));
5882 unsigned imm6 = fieldFromInstruction(Insn, 16, 6);
5883
5884 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
5885 return MCDisassembler::Fail;
5886 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
5887 return MCDisassembler::Fail;
5888 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
5889 return MCDisassembler::Fail;
5890 Check(S, DecodeVpredROperand(Inst, Decoder));
5891 return S;
5892}
5893
5894template <bool scalar, OperandDecoder predicate_decoder>
5895static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
5896 const MCDisassembler *Decoder) {
5898 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5899 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
5900 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
5901 return MCDisassembler::Fail;
5902
5903 unsigned fc;
5904
5905 if (scalar) {
5906 fc = fieldFromInstruction(Insn, 12, 1) << 2 |
5907 fieldFromInstruction(Insn, 7, 1) |
5908 fieldFromInstruction(Insn, 5, 1) << 1;
5909 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5910 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
5911 return MCDisassembler::Fail;
5912 } else {
5913 fc = fieldFromInstruction(Insn, 12, 1) << 2 |
5914 fieldFromInstruction(Insn, 7, 1) |
5915 fieldFromInstruction(Insn, 0, 1) << 1;
5916 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
5917 fieldFromInstruction(Insn, 1, 3);
5918 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
5919 return MCDisassembler::Fail;
5920 }
5921
5922 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
5923 return MCDisassembler::Fail;
5924
5925 Check(S, DecodeVpredNOperand(Inst, Decoder));
5926 return S;
5927}
5928
5929static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
5930 const MCDisassembler *Decoder) {
5932 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5933 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5934 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5935 return MCDisassembler::Fail;
5936 Check(S, DecodeVpredNOperand(Inst, Decoder));
5937 return S;
5938}
5939
5940static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
5941 uint64_t Address,
5942 const MCDisassembler *Decoder) {
5944 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5945 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5946 Check(S, DecodeVpredNOperand(Inst, Decoder));
5947 return S;
5948}
5949
5950static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
5951 uint64_t Address,
5952 const MCDisassembler *Decoder) {
5953 const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
5954 const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5955 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 |
5956 fieldFromInstruction(Insn, 12, 3) << 8 |
5957 fieldFromInstruction(Insn, 0, 8);
5958 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1);
5959 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5960 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5961 unsigned S = fieldFromInstruction(Insn, 20, 1);
5962 if (sign1 != sign2)
5963 return MCDisassembler::Fail;
5964
5965 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
5967 if ((!Check(DS,
5968 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst
5969 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
5970 return MCDisassembler::Fail;
5971 if (TypeT3) {
5972 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
5973 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12
5974 } else {
5975 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
5976 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
5977 return MCDisassembler::Fail;
5978 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
5979 return MCDisassembler::Fail;
5980 }
5981
5982 return DS;
5983}
5984
5985static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
5986 uint64_t Address,
5987 const MCDisassembler *Decoder) {
5989
5990 const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5991 // Adding Rn, holding memory location to save/load to/from, the only argument
5992 // that is being encoded.
5993 // '$Rn' in the assembly.
5994 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5995 return MCDisassembler::Fail;
5996 // An optional predicate, '$p' in the assembly.
5997 DecodePredicateOperand(Inst, ARMCC::AL, Address, Decoder);
5998 // An immediate that represents a floating point registers list. '$regs' in
5999 // the assembly.
6000 Inst.addOperand(MCOperand::createImm(0)); // Arbitrary value, has no effect.
6001
6002 return S;
6003}
6004
6005#include "ARMGenDisassemblerTables.inc"
6006
6007// Post-decoding checks
6009 uint64_t Address, raw_ostream &CS,
6010 uint32_t Insn,
6011 DecodeStatus Result) {
6012 switch (MI.getOpcode()) {
6013 case ARM::HVC: {
6014 // HVC is undefined if condition = 0xf otherwise upredictable
6015 // if condition != 0xe
6016 uint32_t Cond = (Insn >> 28) & 0xF;
6017 if (Cond == 0xF)
6018 return MCDisassembler::Fail;
6019 if (Cond != 0xE)
6021 return Result;
6022 }
6023 case ARM::t2ADDri:
6024 case ARM::t2ADDri12:
6025 case ARM::t2ADDrr:
6026 case ARM::t2ADDrs:
6027 case ARM::t2SUBri:
6028 case ARM::t2SUBri12:
6029 case ARM::t2SUBrr:
6030 case ARM::t2SUBrs:
6031 if (MI.getOperand(0).getReg() == ARM::SP &&
6032 MI.getOperand(1).getReg() != ARM::SP)
6034 return Result;
6035 default: return Result;
6036 }
6037}
6038
6039uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
6040 uint64_t Address) const {
6041 // In Arm state, instructions are always 4 bytes wide, so there's no
6042 // point in skipping any smaller number of bytes if an instruction
6043 // can't be decoded.
6044 if (!STI.hasFeature(ARM::ModeThumb))
6045 return 4;
6046
6047 // In a Thumb instruction stream, a halfword is a standalone 2-byte
6048 // instruction if and only if its value is less than 0xE800.
6049 // Otherwise, it's the first halfword of a 4-byte instruction.
6050 //
6051 // So, if we can see the upcoming halfword, we can judge on that
6052 // basis, and maybe skip a whole 4-byte instruction that we don't
6053 // know how to decode, without accidentally trying to interpret its
6054 // second half as something else.
6055 //
6056 // If we don't have the instruction data available, we just have to
6057 // recommend skipping the minimum sensible distance, which is 2
6058 // bytes.
6059 if (Bytes.size() < 2)
6060 return 2;
6061
6062 uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
6063 Bytes.data(), InstructionEndianness);
6064 return Insn16 < 0xE800 ? 2 : 4;
6065}
6066
6067DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
6068 ArrayRef<uint8_t> Bytes,
6069 uint64_t Address,
6070 raw_ostream &CS) const {
6071 DecodeStatus S;
6072 if (STI.hasFeature(ARM::ModeThumb))
6073 S = getThumbInstruction(MI, Size, Bytes, Address, CS);
6074 else
6075 S = getARMInstruction(MI, Size, Bytes, Address, CS);
6076 if (S == DecodeStatus::Fail)
6077 return S;
6078
6079 // Verify that the decoded instruction has the correct number of operands.
6080 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
6081 if (!MCID.isVariadic() && MI.getNumOperands() != MCID.getNumOperands()) {
6082 reportFatalInternalError(MCII->getName(MI.getOpcode()) + ": expected " +
6083 Twine(MCID.getNumOperands()) + " operands, got " +
6084 Twine(MI.getNumOperands()) + "\n");
6085 }
6086
6087 return S;
6088}
6089
6090DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
6091 ArrayRef<uint8_t> Bytes,
6092 uint64_t Address,
6093 raw_ostream &CS) const {
6094 CommentStream = &CS;
6095
6096 assert(!STI.hasFeature(ARM::ModeThumb) &&
6097 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
6098 "mode!");
6099
6100 // We want to read exactly 4 bytes of data.
6101 if (Bytes.size() < 4) {
6102 Size = 0;
6103 return MCDisassembler::Fail;
6104 }
6105
6106 // Encoded as a 32-bit word in the stream.
6107 uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(),
6108 InstructionEndianness);
6109
6110 // Calling the auto-generated decoder function.
6112 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
6113 if (Result != MCDisassembler::Fail) {
6114 Size = 4;
6115 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
6116 }
6117
6118 struct DecodeTable {
6119 const uint8_t *P;
6120 bool DecodePred;
6121 };
6122
6123 const DecodeTable Tables[] = {
6124 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
6125 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
6126 {DecoderTableNEONDup32, false}, {DecoderTablev8NEON32, false},
6127 {DecoderTablev8Crypto32, false},
6128 };
6129
6130 for (auto Table : Tables) {
6131 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
6132 if (Result != MCDisassembler::Fail) {
6133 Size = 4;
6134 // Add a fake predicate operand, because we share these instruction
6135 // definitions with Thumb2 where these instructions are predicable.
6136 if (Table.DecodePred && MCII->get(MI.getOpcode()).isPredicable()) {
6137 MI.addOperand(MCOperand::createImm(ARMCC::AL));
6138 MI.addOperand(MCOperand::createReg(ARM::NoRegister));
6139 }
6140 return Result;
6141 }
6142 }
6143
6144 Result =
6145 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
6146 if (Result != MCDisassembler::Fail) {
6147 Size = 4;
6148 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
6149 }
6150
6151 Size = 4;
6152 return MCDisassembler::Fail;
6153}
6154
6155bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {
6156 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
6157 for (unsigned i = 0; i < MCID.NumOperands; ++i) {
6158 if (ARM::isVpred(MCID.operands()[i].OperandType))
6159 return true;
6160 }
6161 return false;
6162}
6163
6164// Most Thumb instructions don't have explicit predicates in the
6165// encoding, but rather get their predicates from IT context. We need
6166// to fix up the predicate operands using this context information as a
6167// post-pass.
6169ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
6171
6172 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
6173
6174 // A few instructions actually have predicates encoded in them. Don't
6175 // try to overwrite it if we're seeing one of those.
6176 switch (MI.getOpcode()) {
6177 case ARM::tBcc:
6178 case ARM::t2Bcc:
6179 case ARM::tCBZ:
6180 case ARM::tCBNZ:
6181 case ARM::tCPS:
6182 case ARM::t2CPS3p:
6183 case ARM::t2CPS2p:
6184 case ARM::t2CPS1p:
6185 case ARM::t2CSEL:
6186 case ARM::t2CSINC:
6187 case ARM::t2CSINV:
6188 case ARM::t2CSNEG:
6189 case ARM::tMOVSr:
6190 case ARM::tSETEND:
6191 // Some instructions (mostly conditional branches) are not
6192 // allowed in IT blocks.
6193 if (ITBlock.instrInITBlock())
6194 S = SoftFail;
6195 else
6196 return Success;
6197 break;
6198 case ARM::t2HINT:
6199 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
6200 S = SoftFail;
6201 break;
6202 case ARM::tB:
6203 case ARM::t2B:
6204 case ARM::t2TBB:
6205 case ARM::t2TBH:
6206 // Some instructions (mostly unconditional branches) can
6207 // only appears at the end of, or outside of, an IT.
6208 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
6209 S = SoftFail;
6210 break;
6211 default:
6212 break;
6213 }
6214
6215 // Warn on non-VPT predicable instruction in a VPT block and a VPT
6216 // predicable instruction in an IT block
6217 if ((!isVectorPredicable(MI) && VPTBlock.instrInVPTBlock()) ||
6218 (isVectorPredicable(MI) && ITBlock.instrInITBlock()))
6219 S = SoftFail;
6220
6221 // If we're in an IT block, base the predicate on that. Otherwise,
6222 // assume a predicate of AL.
6223 unsigned CC = ARMCC::AL;
6224 if (ITBlock.instrInITBlock()) {
6225 CC = ITBlock.getITCC();
6226 ITBlock.advanceITState();
6227 } else if (VPTBlock.instrInVPTBlock()) {
6228 VPTBlock.advanceVPTState();
6229 }
6230
6231 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
6232
6233 MCInst::iterator CCI = MI.begin();
6234 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++CCI) {
6235 if (MCID.operands()[i].isPredicate() || CCI == MI.end())
6236 break;
6237 }
6238
6239 if (MCID.isPredicable()) {
6240 CCI = MI.insert(CCI, MCOperand::createImm(CC));
6241 ++CCI;
6242 if (CC == ARMCC::AL)
6243 MI.insert(CCI, MCOperand::createReg(ARM::NoRegister));
6244 else
6245 MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
6246 } else if (CC != ARMCC::AL) {
6247 Check(S, SoftFail);
6248 }
6249
6250 return S;
6251}
6252
6253// Thumb VFP and some NEON instructions are a special case. Because we share
6254// their encodings between ARM and Thumb modes, and they are predicable in ARM
6255// mode, the auto-generated decoder will give them an (incorrect)
6256// predicate operand. We need to rewrite these operands based on the IT
6257// context as a post-pass.
6258void ARMDisassembler::UpdateThumbPredicate(DecodeStatus &S, MCInst &MI) const {
6259 unsigned CC;
6260 CC = ITBlock.getITCC();
6261 if (CC == 0xF)
6262 CC = ARMCC::AL;
6263 if (ITBlock.instrInITBlock())
6264 ITBlock.advanceITState();
6265 else if (VPTBlock.instrInVPTBlock()) {
6266 CC = VPTBlock.getVPTPred();
6267 VPTBlock.advanceVPTState();
6268 }
6269
6270 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
6271 ArrayRef<MCOperandInfo> OpInfo = MCID.operands();
6272 MCInst::iterator I = MI.begin();
6273 unsigned short NumOps = MCID.NumOperands;
6274 for (unsigned i = 0; i < NumOps; ++i, ++I) {
6275 if (OpInfo[i].isPredicate() ) {
6276 if (CC != ARMCC::AL && !MCID.isPredicable())
6277 Check(S, SoftFail);
6278 I->setImm(CC);
6279 ++I;
6280 if (CC == ARMCC::AL)
6281 I->setReg(ARM::NoRegister);
6282 else
6283 I->setReg(ARM::CPSR);
6284 return;
6285 }
6286 }
6287}
6288
6289DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
6290 ArrayRef<uint8_t> Bytes,
6291 uint64_t Address,
6292 raw_ostream &CS) const {
6293 CommentStream = &CS;
6294
6295 assert(STI.hasFeature(ARM::ModeThumb) &&
6296 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
6297
6298 // We want to read exactly 2 bytes of data.
6299 if (Bytes.size() < 2) {
6300 Size = 0;
6301 return MCDisassembler::Fail;
6302 }
6303
6304 uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
6305 Bytes.data(), InstructionEndianness);
6307 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
6308 if (Result != MCDisassembler::Fail) {
6309 Size = 2;
6310 Check(Result, AddThumbPredicate(MI));
6311 return Result;
6312 }
6313
6314 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
6315 STI);
6316 if (Result) {
6317 Size = 2;
6318 Check(Result, AddThumbPredicate(MI));
6319 return Result;
6320 }
6321
6322 Result =
6323 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
6324 if (Result != MCDisassembler::Fail) {
6325 Size = 2;
6326
6327 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
6328 // the Thumb predicate.
6329 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
6331
6332 Check(Result, AddThumbPredicate(MI));
6333
6334 // If we find an IT instruction, we need to parse its condition
6335 // code and mask operands so that we can apply them correctly
6336 // to the subsequent instructions.
6337 if (MI.getOpcode() == ARM::t2IT) {
6338 unsigned Firstcond = MI.getOperand(0).getImm();
6339 unsigned Mask = MI.getOperand(1).getImm();
6340 ITBlock.setITState(Firstcond, Mask);
6341
6342 // An IT instruction that would give a 'NV' predicate is unpredictable.
6343 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
6344 CS << "unpredictable IT predicate sequence";
6345 }
6346
6347 return Result;
6348 }
6349
6350 // We want to read exactly 4 bytes of data.
6351 if (Bytes.size() < 4) {
6352 Size = 0;
6353 return MCDisassembler::Fail;
6354 }
6355
6356 uint32_t Insn32 =
6357 (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>(
6358 Bytes.data() + 2, InstructionEndianness);
6359
6360 Result =
6361 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
6362 if (Result != MCDisassembler::Fail) {
6363 Size = 4;
6364
6365 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
6366 // the VPT predicate.
6367 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
6369
6370 Check(Result, AddThumbPredicate(MI));
6371
6372 if (isVPTOpcode(MI.getOpcode())) {
6373 unsigned Mask = MI.getOperand(0).getImm();
6374 VPTBlock.setVPTState(Mask);
6375 }
6376
6377 return Result;
6378 }
6379
6380 Result =
6381 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
6382 if (Result != MCDisassembler::Fail) {
6383 Size = 4;
6384 Check(Result, AddThumbPredicate(MI));
6385 return Result;
6386 }
6387
6388 Result =
6389 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
6390 if (Result != MCDisassembler::Fail) {
6391 Size = 4;
6392 Check(Result, AddThumbPredicate(MI));
6393 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);
6394 }
6395
6396 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
6397 Result =
6398 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
6399 if (Result != MCDisassembler::Fail) {
6400 Size = 4;
6401 UpdateThumbPredicate(Result, MI);
6402 return Result;
6403 }
6404 }
6405
6406 Result =
6407 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
6408 if (Result != MCDisassembler::Fail) {
6409 Size = 4;
6410 return Result;
6411 }
6412
6413 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
6414 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
6415 STI);
6416 if (Result != MCDisassembler::Fail) {
6417 Size = 4;
6418 UpdateThumbPredicate(Result, MI);
6419 return Result;
6420 }
6421 }
6422
6423 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
6424 uint32_t NEONLdStInsn = Insn32;
6425 NEONLdStInsn &= 0xF0FFFFFF;
6426 NEONLdStInsn |= 0x04000000;
6427 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
6428 Address, this, STI);
6429 if (Result != MCDisassembler::Fail) {
6430 Size = 4;
6431 Check(Result, AddThumbPredicate(MI));
6432 return Result;
6433 }
6434 }
6435
6436 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
6437 uint32_t NEONDataInsn = Insn32;
6438 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
6439 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
6440 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
6441 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
6442 Address, this, STI);
6443 if (Result != MCDisassembler::Fail) {
6444 Size = 4;
6445 Check(Result, AddThumbPredicate(MI));
6446 return Result;
6447 }
6448
6449 uint32_t NEONCryptoInsn = Insn32;
6450 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
6451 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
6452 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
6453 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
6454 Address, this, STI);
6455 if (Result != MCDisassembler::Fail) {
6456 Size = 4;
6457 return Result;
6458 }
6459
6460 uint32_t NEONv8Insn = Insn32;
6461 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
6462 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
6463 this, STI);
6464 if (Result != MCDisassembler::Fail) {
6465 Size = 4;
6466 return Result;
6467 }
6468 }
6469
6470 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
6471 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
6472 ? DecoderTableThumb2CDE32
6473 : DecoderTableThumb2CoProc32;
6474 Result =
6475 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);
6476 if (Result != MCDisassembler::Fail) {
6477 Size = 4;
6478 Check(Result, AddThumbPredicate(MI));
6479 return Result;
6480 }
6481
6482 // Advance IT state to prevent next instruction inheriting
6483 // the wrong IT state.
6484 if (ITBlock.instrInITBlock())
6485 ITBlock.advanceITState();
6486 Size = 0;
6487 return MCDisassembler::Fail;
6488}
6489
6491 const MCSubtargetInfo &STI,
6492 MCContext &Ctx) {
6493 return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo());
6494}
6495
6496extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
#define SoftFail
MCDisassembler::DecodeStatus DecodeStatus
#define Success
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
AMDGPU Mark last scratch load
static bool isVectorPredicable(const MCInstrDesc &MCID)
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t GPRPairDecoderTable[]
static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg QQPRDecoderTable[]
static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, const MCDisassembler *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler()
static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg DPairDecoderTable[]
static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg DPairSpacedDecoderTable[]
static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVpredNOperand(MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createARMDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode)
static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg QPRDecoderTable[]
static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg SPRDecoderTable[]
static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t CLRMGPRDecoderTable[]
static const MCPhysReg DPRDecoderTable[]
static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const MCDisassembler *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t GPRDecoderTable[]
static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVpredROperand(MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg QQQQPRDecoderTable[]
static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder, unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder)
static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, uint64_t Address, raw_ostream &CS, uint32_t Insn, DecodeStatus Result)
static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_ABI
Definition Compiler.h:213
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
static bool isNeg(Value *V)
Returns true if the operation is a negation of V, and it works for both integers and floats.
static bool isSigned(unsigned int Opcode)
#define Check(C,...)
#define op(i)
amode Optimize addressing mode
IRTranslator LLVM IR MI
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
#define I(x, y, z)
Definition MD5.cpp:58
#define T
#define P(N)
static bool isBranch(unsigned Opcode)
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition ArrayRef.h:147
const T * data() const
Definition ArrayRef.h:144
Container class for subtarget features.
Context object for machine code objects.
Definition MCContext.h:83
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
const MCSubtargetInfo & getSubtargetInfo() const
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
unsigned getNumOperands() const
Definition MCInst.h:212
SmallVectorImpl< MCOperand >::iterator iterator
Definition MCInst.h:220
unsigned getOpcode() const
Definition MCInst.h:202
void addOperand(const MCOperand Op)
Definition MCInst.h:215
iterator end()
Definition MCInst.h:229
void setOpcode(unsigned Op)
Definition MCInst.h:201
const MCOperand & getOperand(unsigned i) const
Definition MCInst.h:210
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned short NumOperands
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition MCInstrInfo.h:90
Instances of this class represent operands of the MCInst class.
Definition MCInst.h:40
int64_t getImm() const
Definition MCInst.h:84
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
MCRegister getReg() const
Returns the register number.
Definition MCInst.h:73
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
Wrapper class representing virtual and physical registers.
Definition Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition Value.h:75
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
getAM5Opc - This function encodes the addrmode5 opc field.
unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset)
getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
bool isVpred(OperandType op)
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
@ D16
Only 16 D registers.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)
Definition MCDecoder.h:37
value_type read(const void *memory, endianness endian)
Read a value of a particular endianness from memory.
Definition Endian.h:60
This is an optimization pass for GlobalISel generic memory operations.
constexpr T rotr(T V, int R)
Definition bit.h:357
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition STLExtras.h:1657
Target & getTheThumbBETarget()
static bool isVPTOpcode(int Opc)
LLVM_ABI void reportFatalInternalError(Error Err)
Report a fatal error that indicates a bug in LLVM.
Definition Error.cpp:177
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition bit.h:186
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition MathExtras.h:288
static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
Definition MathExtras.h:565
endianness
Definition bit.h:71
Target & getTheARMLETarget()
Target & getTheARMBETarget()
Target & getTheThumbLETarget()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.