1.7.5.1Copyright © 2003-2013 University of Illinois at Urbana-Champaign. All Rights Reserved.
LLVM API Documentation
00001 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 00010 #define DEBUG_TYPE "arm-disassembler" 00011 00012 #include "llvm/MC/MCDisassembler.h" 00013 #include "MCTargetDesc/ARMAddressingModes.h" 00014 #include "MCTargetDesc/ARMBaseInfo.h" 00015 #include "MCTargetDesc/ARMMCExpr.h" 00016 #include "llvm/MC/MCContext.h" 00017 #include "llvm/MC/MCExpr.h" 00018 #include "llvm/MC/MCFixedLenDisassembler.h" 00019 #include "llvm/MC/MCInst.h" 00020 #include "llvm/MC/MCInstrDesc.h" 00021 #include "llvm/MC/MCSubtargetInfo.h" 00022 #include "llvm/Support/Debug.h" 00023 #include "llvm/Support/ErrorHandling.h" 00024 #include "llvm/Support/LEB128.h" 00025 #include "llvm/Support/MemoryObject.h" 00026 #include "llvm/Support/TargetRegistry.h" 00027 #include "llvm/Support/raw_ostream.h" 00028 #include <vector> 00029 00030 using namespace llvm; 00031 00032 typedef MCDisassembler::DecodeStatus DecodeStatus; 00033 00034 namespace { 00035 // Handles the condition code status of instructions in IT blocks 00036 class ITStatus 00037 { 00038 public: 00039 // Returns the condition code for instruction in IT block 00040 unsigned getITCC() { 00041 unsigned CC = ARMCC::AL; 00042 if (instrInITBlock()) 00043 CC = ITStates.back(); 00044 return CC; 00045 } 00046 00047 // Advances the IT block state to the next T or E 00048 void advanceITState() { 00049 ITStates.pop_back(); 00050 } 00051 00052 // Returns true if the current instruction is in an IT block 00053 bool instrInITBlock() { 00054 return !ITStates.empty(); 00055 } 00056 00057 // Returns true if current instruction is the last instruction in an IT block 00058 bool instrLastInITBlock() { 00059 return ITStates.size() == 1; 00060 } 00061 00062 // Called when decoding an IT instruction. Sets the IT state for the following 00063 // instructions that for the IT block. Firstcond and Mask correspond to the 00064 // fields in the IT instruction encoding. 00065 void setITState(char Firstcond, char Mask) { 00066 // (3 - the number of trailing zeros) is the number of then / else. 00067 unsigned CondBit0 = Firstcond & 1; 00068 unsigned NumTZ = CountTrailingZeros_32(Mask); 00069 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 00070 assert(NumTZ <= 3 && "Invalid IT mask!"); 00071 // push condition codes onto the stack the correct order for the pops 00072 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 00073 bool T = ((Mask >> Pos) & 1) == CondBit0; 00074 if (T) 00075 ITStates.push_back(CCBits); 00076 else 00077 ITStates.push_back(CCBits ^ 1); 00078 } 00079 ITStates.push_back(CCBits); 00080 } 00081 00082 private: 00083 std::vector<unsigned char> ITStates; 00084 }; 00085 } 00086 00087 namespace { 00088 /// ARMDisassembler - ARM disassembler for all ARM platforms. 00089 class ARMDisassembler : public MCDisassembler { 00090 public: 00091 /// Constructor - Initializes the disassembler. 00092 /// 00093 ARMDisassembler(const MCSubtargetInfo &STI) : 00094 MCDisassembler(STI) { 00095 } 00096 00097 ~ARMDisassembler() { 00098 } 00099 00100 /// getInstruction - See MCDisassembler. 00101 DecodeStatus getInstruction(MCInst &instr, 00102 uint64_t &size, 00103 const MemoryObject ®ion, 00104 uint64_t address, 00105 raw_ostream &vStream, 00106 raw_ostream &cStream) const; 00107 }; 00108 00109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 00110 class ThumbDisassembler : public MCDisassembler { 00111 public: 00112 /// Constructor - Initializes the disassembler. 00113 /// 00114 ThumbDisassembler(const MCSubtargetInfo &STI) : 00115 MCDisassembler(STI) { 00116 } 00117 00118 ~ThumbDisassembler() { 00119 } 00120 00121 /// getInstruction - See MCDisassembler. 00122 DecodeStatus getInstruction(MCInst &instr, 00123 uint64_t &size, 00124 const MemoryObject ®ion, 00125 uint64_t address, 00126 raw_ostream &vStream, 00127 raw_ostream &cStream) const; 00128 00129 private: 00130 mutable ITStatus ITBlock; 00131 DecodeStatus AddThumbPredicate(MCInst&) const; 00132 void UpdateThumbVFPPredicate(MCInst&) const; 00133 }; 00134 } 00135 00136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 00137 switch (In) { 00138 case MCDisassembler::Success: 00139 // Out stays the same. 00140 return true; 00141 case MCDisassembler::SoftFail: 00142 Out = In; 00143 return true; 00144 case MCDisassembler::Fail: 00145 Out = In; 00146 return false; 00147 } 00148 llvm_unreachable("Invalid DecodeStatus!"); 00149 } 00150 00151 00152 // Forward declare these because the autogenerated code will reference them. 00153 // Definitions are further down. 00154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00155 uint64_t Address, const void *Decoder); 00156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 00157 unsigned RegNo, uint64_t Address, 00158 const void *Decoder); 00159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 00160 unsigned RegNo, uint64_t Address, 00161 const void *Decoder); 00162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00163 uint64_t Address, const void *Decoder); 00164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00165 uint64_t Address, const void *Decoder); 00166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00167 uint64_t Address, const void *Decoder); 00168 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 00169 uint64_t Address, const void *Decoder); 00170 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 00171 uint64_t Address, const void *Decoder); 00172 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 00173 uint64_t Address, const void *Decoder); 00174 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 00175 unsigned RegNo, 00176 uint64_t Address, 00177 const void *Decoder); 00178 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 00179 uint64_t Address, const void *Decoder); 00180 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 00181 uint64_t Address, const void *Decoder); 00182 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 00183 unsigned RegNo, uint64_t Address, 00184 const void *Decoder); 00185 00186 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 00187 uint64_t Address, const void *Decoder); 00188 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 00189 uint64_t Address, const void *Decoder); 00190 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 00191 uint64_t Address, const void *Decoder); 00192 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 00193 uint64_t Address, const void *Decoder); 00194 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 00195 uint64_t Address, const void *Decoder); 00196 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 00197 uint64_t Address, const void *Decoder); 00198 00199 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 00200 uint64_t Address, const void *Decoder); 00201 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 00202 uint64_t Address, const void *Decoder); 00203 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 00204 unsigned Insn, 00205 uint64_t Address, 00206 const void *Decoder); 00207 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 00208 uint64_t Address, const void *Decoder); 00209 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 00210 uint64_t Address, const void *Decoder); 00211 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 00212 uint64_t Address, const void *Decoder); 00213 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 00214 uint64_t Address, const void *Decoder); 00215 00216 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 00217 unsigned Insn, 00218 uint64_t Adddress, 00219 const void *Decoder); 00220 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 00221 uint64_t Address, const void *Decoder); 00222 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 00223 uint64_t Address, const void *Decoder); 00224 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 00225 uint64_t Address, const void *Decoder); 00226 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 00227 uint64_t Address, const void *Decoder); 00228 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 00229 uint64_t Address, const void *Decoder); 00230 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 00231 uint64_t Address, const void *Decoder); 00232 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 00233 uint64_t Address, const void *Decoder); 00234 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 00235 uint64_t Address, const void *Decoder); 00236 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 00237 uint64_t Address, const void *Decoder); 00238 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 00239 uint64_t Address, const void *Decoder); 00240 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 00241 uint64_t Address, const void *Decoder); 00242 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 00243 uint64_t Address, const void *Decoder); 00244 static DecodeStatus DecodeVST1Instruction(MCInst &Inst, unsigned Val, 00245 uint64_t Address, const void *Decoder); 00246 static DecodeStatus DecodeVST2Instruction(MCInst &Inst, unsigned Val, 00247 uint64_t Address, const void *Decoder); 00248 static DecodeStatus DecodeVST3Instruction(MCInst &Inst, unsigned Val, 00249 uint64_t Address, const void *Decoder); 00250 static DecodeStatus DecodeVST4Instruction(MCInst &Inst, unsigned Val, 00251 uint64_t Address, const void *Decoder); 00252 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 00253 uint64_t Address, const void *Decoder); 00254 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 00255 uint64_t Address, const void *Decoder); 00256 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 00257 uint64_t Address, const void *Decoder); 00258 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 00259 uint64_t Address, const void *Decoder); 00260 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 00261 uint64_t Address, const void *Decoder); 00262 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 00263 uint64_t Address, const void *Decoder); 00264 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 00265 uint64_t Address, const void *Decoder); 00266 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 00267 uint64_t Address, const void *Decoder); 00268 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 00269 uint64_t Address, const void *Decoder); 00270 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 00271 uint64_t Address, const void *Decoder); 00272 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 00273 uint64_t Address, const void *Decoder); 00274 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 00275 uint64_t Address, const void *Decoder); 00276 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 00277 uint64_t Address, const void *Decoder); 00278 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 00279 uint64_t Address, const void *Decoder); 00280 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 00281 uint64_t Address, const void *Decoder); 00282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 00283 uint64_t Address, const void *Decoder); 00284 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 00285 uint64_t Address, const void *Decoder); 00286 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 00287 uint64_t Address, const void *Decoder); 00288 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 00289 uint64_t Address, const void *Decoder); 00290 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 00291 uint64_t Address, const void *Decoder); 00292 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 00293 uint64_t Address, const void *Decoder); 00294 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 00295 uint64_t Address, const void *Decoder); 00296 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 00297 uint64_t Address, const void *Decoder); 00298 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 00299 uint64_t Address, const void *Decoder); 00300 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 00301 uint64_t Address, const void *Decoder); 00302 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 00303 uint64_t Address, const void *Decoder); 00304 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 00305 uint64_t Address, const void *Decoder); 00306 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 00307 uint64_t Address, const void *Decoder); 00308 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 00309 uint64_t Address, const void *Decoder); 00310 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 00311 uint64_t Address, const void *Decoder); 00312 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 00313 uint64_t Address, const void *Decoder); 00314 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 00315 uint64_t Address, const void *Decoder); 00316 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 00317 uint64_t Address, const void *Decoder); 00318 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 00319 uint64_t Address, const void *Decoder); 00320 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 00321 uint64_t Address, const void *Decoder); 00322 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 00323 const void *Decoder); 00324 00325 00326 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 00327 uint64_t Address, const void *Decoder); 00328 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 00329 uint64_t Address, const void *Decoder); 00330 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 00331 uint64_t Address, const void *Decoder); 00332 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 00333 uint64_t Address, const void *Decoder); 00334 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 00335 uint64_t Address, const void *Decoder); 00336 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 00337 uint64_t Address, const void *Decoder); 00338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 00339 uint64_t Address, const void *Decoder); 00340 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 00341 uint64_t Address, const void *Decoder); 00342 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 00343 uint64_t Address, const void *Decoder); 00344 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 00345 uint64_t Address, const void *Decoder); 00346 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 00347 uint64_t Address, const void *Decoder); 00348 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 00349 uint64_t Address, const void *Decoder); 00350 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 00351 uint64_t Address, const void *Decoder); 00352 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 00353 uint64_t Address, const void *Decoder); 00354 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 00355 uint64_t Address, const void *Decoder); 00356 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 00357 uint64_t Address, const void *Decoder); 00358 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 00359 uint64_t Address, const void *Decoder); 00360 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 00361 uint64_t Address, const void *Decoder); 00362 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 00363 uint64_t Address, const void *Decoder); 00364 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 00365 uint64_t Address, const void *Decoder); 00366 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 00367 uint64_t Address, const void *Decoder); 00368 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 00369 uint64_t Address, const void *Decoder); 00370 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 00371 uint64_t Address, const void *Decoder); 00372 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 00373 uint64_t Address, const void *Decoder); 00374 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 00375 uint64_t Address, const void *Decoder); 00376 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 00377 uint64_t Address, const void *Decoder); 00378 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 00379 uint64_t Address, const void *Decoder); 00380 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 00381 uint64_t Address, const void *Decoder); 00382 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 00383 uint64_t Address, const void *Decoder); 00384 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 00385 uint64_t Address, const void *Decoder); 00386 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 00387 uint64_t Address, const void *Decoder); 00388 00389 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 00390 uint64_t Address, const void *Decoder); 00391 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 00392 uint64_t Address, const void *Decoder); 00393 #include "ARMGenDisassemblerTables.inc" 00394 00395 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 00396 return new ARMDisassembler(STI); 00397 } 00398 00399 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 00400 return new ThumbDisassembler(STI); 00401 } 00402 00403 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 00404 const MemoryObject &Region, 00405 uint64_t Address, 00406 raw_ostream &os, 00407 raw_ostream &cs) const { 00408 CommentStream = &cs; 00409 00410 uint8_t bytes[4]; 00411 00412 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 00413 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 00414 00415 // We want to read exactly 4 bytes of data. 00416 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 00417 Size = 0; 00418 return MCDisassembler::Fail; 00419 } 00420 00421 // Encoded as a small-endian 32-bit word in the stream. 00422 uint32_t insn = (bytes[3] << 24) | 00423 (bytes[2] << 16) | 00424 (bytes[1] << 8) | 00425 (bytes[0] << 0); 00426 00427 // Calling the auto-generated decoder function. 00428 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 00429 Address, this, STI); 00430 if (result != MCDisassembler::Fail) { 00431 Size = 4; 00432 return result; 00433 } 00434 00435 // VFP and NEON instructions, similarly, are shared between ARM 00436 // and Thumb modes. 00437 MI.clear(); 00438 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 00439 if (result != MCDisassembler::Fail) { 00440 Size = 4; 00441 return result; 00442 } 00443 00444 MI.clear(); 00445 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 00446 this, STI); 00447 if (result != MCDisassembler::Fail) { 00448 Size = 4; 00449 // Add a fake predicate operand, because we share these instruction 00450 // definitions with Thumb2 where these instructions are predicable. 00451 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 00452 return MCDisassembler::Fail; 00453 return result; 00454 } 00455 00456 MI.clear(); 00457 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 00458 this, STI); 00459 if (result != MCDisassembler::Fail) { 00460 Size = 4; 00461 // Add a fake predicate operand, because we share these instruction 00462 // definitions with Thumb2 where these instructions are predicable. 00463 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 00464 return MCDisassembler::Fail; 00465 return result; 00466 } 00467 00468 MI.clear(); 00469 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 00470 this, STI); 00471 if (result != MCDisassembler::Fail) { 00472 Size = 4; 00473 // Add a fake predicate operand, because we share these instruction 00474 // definitions with Thumb2 where these instructions are predicable. 00475 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 00476 return MCDisassembler::Fail; 00477 return result; 00478 } 00479 00480 MI.clear(); 00481 00482 Size = 0; 00483 return MCDisassembler::Fail; 00484 } 00485 00486 namespace llvm { 00487 extern const MCInstrDesc ARMInsts[]; 00488 } 00489 00490 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 00491 /// immediate Value in the MCInst. The immediate Value has had any PC 00492 /// adjustment made by the caller. If the instruction is a branch instruction 00493 /// then isBranch is true, else false. If the getOpInfo() function was set as 00494 /// part of the setupForSymbolicDisassembly() call then that function is called 00495 /// to get any symbolic information at the Address for this instruction. If 00496 /// that returns non-zero then the symbolic information it returns is used to 00497 /// create an MCExpr and that is added as an operand to the MCInst. If 00498 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 00499 /// Value is done and if a symbol is found an MCExpr is created with that, else 00500 /// an MCExpr with Value is created. This function returns true if it adds an 00501 /// operand to the MCInst and false otherwise. 00502 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 00503 bool isBranch, uint64_t InstSize, 00504 MCInst &MI, const void *Decoder) { 00505 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 00506 // FIXME: Does it make sense for value to be negative? 00507 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 00508 /* Offset */ 0, InstSize); 00509 } 00510 00511 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 00512 /// referenced by a load instruction with the base register that is the Pc. 00513 /// These can often be values in a literal pool near the Address of the 00514 /// instruction. The Address of the instruction and its immediate Value are 00515 /// used as a possible literal pool entry. The SymbolLookUp call back will 00516 /// return the name of a symbol referenced by the literal pool's entry if 00517 /// the referenced address is that of a symbol. Or it will return a pointer to 00518 /// a literal 'C' string if the referenced address of the literal pool's entry 00519 /// is an address into a section with 'C' string literals. 00520 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 00521 const void *Decoder) { 00522 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 00523 Dis->tryAddingPcLoadReferenceComment(Value, Address); 00524 } 00525 00526 // Thumb1 instructions don't have explicit S bits. Rather, they 00527 // implicitly set CPSR. Since it's not represented in the encoding, the 00528 // auto-generated decoder won't inject the CPSR operand. We need to fix 00529 // that as a post-pass. 00530 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 00531 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 00532 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 00533 MCInst::iterator I = MI.begin(); 00534 for (unsigned i = 0; i < NumOps; ++i, ++I) { 00535 if (I == MI.end()) break; 00536 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 00537 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 00538 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 00539 return; 00540 } 00541 } 00542 00543 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 00544 } 00545 00546 // Most Thumb instructions don't have explicit predicates in the 00547 // encoding, but rather get their predicates from IT context. We need 00548 // to fix up the predicate operands using this context information as a 00549 // post-pass. 00550 MCDisassembler::DecodeStatus 00551 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 00552 MCDisassembler::DecodeStatus S = Success; 00553 00554 // A few instructions actually have predicates encoded in them. Don't 00555 // try to overwrite it if we're seeing one of those. 00556 switch (MI.getOpcode()) { 00557 case ARM::tBcc: 00558 case ARM::t2Bcc: 00559 case ARM::tCBZ: 00560 case ARM::tCBNZ: 00561 case ARM::tCPS: 00562 case ARM::t2CPS3p: 00563 case ARM::t2CPS2p: 00564 case ARM::t2CPS1p: 00565 case ARM::tMOVSr: 00566 case ARM::tSETEND: 00567 // Some instructions (mostly conditional branches) are not 00568 // allowed in IT blocks. 00569 if (ITBlock.instrInITBlock()) 00570 S = SoftFail; 00571 else 00572 return Success; 00573 break; 00574 case ARM::tB: 00575 case ARM::t2B: 00576 case ARM::t2TBB: 00577 case ARM::t2TBH: 00578 // Some instructions (mostly unconditional branches) can 00579 // only appears at the end of, or outside of, an IT. 00580 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 00581 S = SoftFail; 00582 break; 00583 default: 00584 break; 00585 } 00586 00587 // If we're in an IT block, base the predicate on that. Otherwise, 00588 // assume a predicate of AL. 00589 unsigned CC; 00590 CC = ITBlock.getITCC(); 00591 if (CC == 0xF) 00592 CC = ARMCC::AL; 00593 if (ITBlock.instrInITBlock()) 00594 ITBlock.advanceITState(); 00595 00596 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 00597 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 00598 MCInst::iterator I = MI.begin(); 00599 for (unsigned i = 0; i < NumOps; ++i, ++I) { 00600 if (I == MI.end()) break; 00601 if (OpInfo[i].isPredicate()) { 00602 I = MI.insert(I, MCOperand::CreateImm(CC)); 00603 ++I; 00604 if (CC == ARMCC::AL) 00605 MI.insert(I, MCOperand::CreateReg(0)); 00606 else 00607 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 00608 return S; 00609 } 00610 } 00611 00612 I = MI.insert(I, MCOperand::CreateImm(CC)); 00613 ++I; 00614 if (CC == ARMCC::AL) 00615 MI.insert(I, MCOperand::CreateReg(0)); 00616 else 00617 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 00618 00619 return S; 00620 } 00621 00622 // Thumb VFP instructions are a special case. Because we share their 00623 // encodings between ARM and Thumb modes, and they are predicable in ARM 00624 // mode, the auto-generated decoder will give them an (incorrect) 00625 // predicate operand. We need to rewrite these operands based on the IT 00626 // context as a post-pass. 00627 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 00628 unsigned CC; 00629 CC = ITBlock.getITCC(); 00630 if (ITBlock.instrInITBlock()) 00631 ITBlock.advanceITState(); 00632 00633 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 00634 MCInst::iterator I = MI.begin(); 00635 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 00636 for (unsigned i = 0; i < NumOps; ++i, ++I) { 00637 if (OpInfo[i].isPredicate() ) { 00638 I->setImm(CC); 00639 ++I; 00640 if (CC == ARMCC::AL) 00641 I->setReg(0); 00642 else 00643 I->setReg(ARM::CPSR); 00644 return; 00645 } 00646 } 00647 } 00648 00649 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 00650 const MemoryObject &Region, 00651 uint64_t Address, 00652 raw_ostream &os, 00653 raw_ostream &cs) const { 00654 CommentStream = &cs; 00655 00656 uint8_t bytes[4]; 00657 00658 assert((STI.getFeatureBits() & ARM::ModeThumb) && 00659 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 00660 00661 // We want to read exactly 2 bytes of data. 00662 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 00663 Size = 0; 00664 return MCDisassembler::Fail; 00665 } 00666 00667 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 00668 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 00669 Address, this, STI); 00670 if (result != MCDisassembler::Fail) { 00671 Size = 2; 00672 Check(result, AddThumbPredicate(MI)); 00673 return result; 00674 } 00675 00676 MI.clear(); 00677 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 00678 Address, this, STI); 00679 if (result) { 00680 Size = 2; 00681 bool InITBlock = ITBlock.instrInITBlock(); 00682 Check(result, AddThumbPredicate(MI)); 00683 AddThumb1SBit(MI, InITBlock); 00684 return result; 00685 } 00686 00687 MI.clear(); 00688 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 00689 Address, this, STI); 00690 if (result != MCDisassembler::Fail) { 00691 Size = 2; 00692 00693 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 00694 // the Thumb predicate. 00695 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 00696 result = MCDisassembler::SoftFail; 00697 00698 Check(result, AddThumbPredicate(MI)); 00699 00700 // If we find an IT instruction, we need to parse its condition 00701 // code and mask operands so that we can apply them correctly 00702 // to the subsequent instructions. 00703 if (MI.getOpcode() == ARM::t2IT) { 00704 00705 unsigned Firstcond = MI.getOperand(0).getImm(); 00706 unsigned Mask = MI.getOperand(1).getImm(); 00707 ITBlock.setITState(Firstcond, Mask); 00708 } 00709 00710 return result; 00711 } 00712 00713 // We want to read exactly 4 bytes of data. 00714 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 00715 Size = 0; 00716 return MCDisassembler::Fail; 00717 } 00718 00719 uint32_t insn32 = (bytes[3] << 8) | 00720 (bytes[2] << 0) | 00721 (bytes[1] << 24) | 00722 (bytes[0] << 16); 00723 MI.clear(); 00724 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 00725 this, STI); 00726 if (result != MCDisassembler::Fail) { 00727 Size = 4; 00728 bool InITBlock = ITBlock.instrInITBlock(); 00729 Check(result, AddThumbPredicate(MI)); 00730 AddThumb1SBit(MI, InITBlock); 00731 return result; 00732 } 00733 00734 MI.clear(); 00735 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 00736 this, STI); 00737 if (result != MCDisassembler::Fail) { 00738 Size = 4; 00739 Check(result, AddThumbPredicate(MI)); 00740 return result; 00741 } 00742 00743 MI.clear(); 00744 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 00745 if (result != MCDisassembler::Fail) { 00746 Size = 4; 00747 UpdateThumbVFPPredicate(MI); 00748 return result; 00749 } 00750 00751 MI.clear(); 00752 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 00753 this, STI); 00754 if (result != MCDisassembler::Fail) { 00755 Size = 4; 00756 Check(result, AddThumbPredicate(MI)); 00757 return result; 00758 } 00759 00760 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 00761 MI.clear(); 00762 uint32_t NEONLdStInsn = insn32; 00763 NEONLdStInsn &= 0xF0FFFFFF; 00764 NEONLdStInsn |= 0x04000000; 00765 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 00766 Address, this, STI); 00767 if (result != MCDisassembler::Fail) { 00768 Size = 4; 00769 Check(result, AddThumbPredicate(MI)); 00770 return result; 00771 } 00772 } 00773 00774 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 00775 MI.clear(); 00776 uint32_t NEONDataInsn = insn32; 00777 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 00778 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 00779 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 00780 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 00781 Address, this, STI); 00782 if (result != MCDisassembler::Fail) { 00783 Size = 4; 00784 Check(result, AddThumbPredicate(MI)); 00785 return result; 00786 } 00787 } 00788 00789 Size = 0; 00790 return MCDisassembler::Fail; 00791 } 00792 00793 00794 extern "C" void LLVMInitializeARMDisassembler() { 00795 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 00796 createARMDisassembler); 00797 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 00798 createThumbDisassembler); 00799 } 00800 00801 static const uint16_t GPRDecoderTable[] = { 00802 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 00803 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 00804 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 00805 ARM::R12, ARM::SP, ARM::LR, ARM::PC 00806 }; 00807 00808 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00809 uint64_t Address, const void *Decoder) { 00810 if (RegNo > 15) 00811 return MCDisassembler::Fail; 00812 00813 unsigned Register = GPRDecoderTable[RegNo]; 00814 Inst.addOperand(MCOperand::CreateReg(Register)); 00815 return MCDisassembler::Success; 00816 } 00817 00818 static DecodeStatus 00819 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 00820 uint64_t Address, const void *Decoder) { 00821 DecodeStatus S = MCDisassembler::Success; 00822 00823 if (RegNo == 15) 00824 S = MCDisassembler::SoftFail; 00825 00826 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 00827 00828 return S; 00829 } 00830 00831 static DecodeStatus 00832 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 00833 uint64_t Address, const void *Decoder) { 00834 DecodeStatus S = MCDisassembler::Success; 00835 00836 if (RegNo == 15) 00837 { 00838 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 00839 return MCDisassembler::Success; 00840 } 00841 00842 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 00843 return S; 00844 } 00845 00846 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00847 uint64_t Address, const void *Decoder) { 00848 if (RegNo > 7) 00849 return MCDisassembler::Fail; 00850 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 00851 } 00852 00853 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00854 uint64_t Address, const void *Decoder) { 00855 unsigned Register = 0; 00856 switch (RegNo) { 00857 case 0: 00858 Register = ARM::R0; 00859 break; 00860 case 1: 00861 Register = ARM::R1; 00862 break; 00863 case 2: 00864 Register = ARM::R2; 00865 break; 00866 case 3: 00867 Register = ARM::R3; 00868 break; 00869 case 9: 00870 Register = ARM::R9; 00871 break; 00872 case 12: 00873 Register = ARM::R12; 00874 break; 00875 default: 00876 return MCDisassembler::Fail; 00877 } 00878 00879 Inst.addOperand(MCOperand::CreateReg(Register)); 00880 return MCDisassembler::Success; 00881 } 00882 00883 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00884 uint64_t Address, const void *Decoder) { 00885 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 00886 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 00887 } 00888 00889 static const uint16_t SPRDecoderTable[] = { 00890 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 00891 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 00892 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 00893 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 00894 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 00895 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 00896 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 00897 ARM::S28, ARM::S29, ARM::S30, ARM::S31 00898 }; 00899 00900 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 00901 uint64_t Address, const void *Decoder) { 00902 if (RegNo > 31) 00903 return MCDisassembler::Fail; 00904 00905 unsigned Register = SPRDecoderTable[RegNo]; 00906 Inst.addOperand(MCOperand::CreateReg(Register)); 00907 return MCDisassembler::Success; 00908 } 00909 00910 static const uint16_t DPRDecoderTable[] = { 00911 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 00912 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 00913 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 00914 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 00915 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 00916 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 00917 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 00918 ARM::D28, ARM::D29, ARM::D30, ARM::D31 00919 }; 00920 00921 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 00922 uint64_t Address, const void *Decoder) { 00923 if (RegNo > 31) 00924 return MCDisassembler::Fail; 00925 00926 unsigned Register = DPRDecoderTable[RegNo]; 00927 Inst.addOperand(MCOperand::CreateReg(Register)); 00928 return MCDisassembler::Success; 00929 } 00930 00931 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 00932 uint64_t Address, const void *Decoder) { 00933 if (RegNo > 7) 00934 return MCDisassembler::Fail; 00935 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 00936 } 00937 00938 static DecodeStatus 00939 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 00940 uint64_t Address, const void *Decoder) { 00941 if (RegNo > 15) 00942 return MCDisassembler::Fail; 00943 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 00944 } 00945 00946 static const uint16_t QPRDecoderTable[] = { 00947 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 00948 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 00949 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 00950 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 00951 }; 00952 00953 00954 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 00955 uint64_t Address, const void *Decoder) { 00956 if (RegNo > 31 || (RegNo & 1) != 0) 00957 return MCDisassembler::Fail; 00958 RegNo >>= 1; 00959 00960 unsigned Register = QPRDecoderTable[RegNo]; 00961 Inst.addOperand(MCOperand::CreateReg(Register)); 00962 return MCDisassembler::Success; 00963 } 00964 00965 static const uint16_t DPairDecoderTable[] = { 00966 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 00967 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 00968 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 00969 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 00970 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 00971 ARM::Q15 00972 }; 00973 00974 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 00975 uint64_t Address, const void *Decoder) { 00976 if (RegNo > 30) 00977 return MCDisassembler::Fail; 00978 00979 unsigned Register = DPairDecoderTable[RegNo]; 00980 Inst.addOperand(MCOperand::CreateReg(Register)); 00981 return MCDisassembler::Success; 00982 } 00983 00984 static const uint16_t DPairSpacedDecoderTable[] = { 00985 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 00986 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 00987 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 00988 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 00989 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 00990 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 00991 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 00992 ARM::D28_D30, ARM::D29_D31 00993 }; 00994 00995 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 00996 unsigned RegNo, 00997 uint64_t Address, 00998 const void *Decoder) { 00999 if (RegNo > 29) 01000 return MCDisassembler::Fail; 01001 01002 unsigned Register = DPairSpacedDecoderTable[RegNo]; 01003 Inst.addOperand(MCOperand::CreateReg(Register)); 01004 return MCDisassembler::Success; 01005 } 01006 01007 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 01008 uint64_t Address, const void *Decoder) { 01009 if (Val == 0xF) return MCDisassembler::Fail; 01010 // AL predicate is not allowed on Thumb1 branches. 01011 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 01012 return MCDisassembler::Fail; 01013 Inst.addOperand(MCOperand::CreateImm(Val)); 01014 if (Val == ARMCC::AL) { 01015 Inst.addOperand(MCOperand::CreateReg(0)); 01016 } else 01017 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 01018 return MCDisassembler::Success; 01019 } 01020 01021 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 01022 uint64_t Address, const void *Decoder) { 01023 if (Val) 01024 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 01025 else 01026 Inst.addOperand(MCOperand::CreateReg(0)); 01027 return MCDisassembler::Success; 01028 } 01029 01030 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 01031 uint64_t Address, const void *Decoder) { 01032 uint32_t imm = Val & 0xFF; 01033 uint32_t rot = (Val & 0xF00) >> 7; 01034 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 01035 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 01036 return MCDisassembler::Success; 01037 } 01038 01039 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 01040 uint64_t Address, const void *Decoder) { 01041 DecodeStatus S = MCDisassembler::Success; 01042 01043 unsigned Rm = fieldFromInstruction(Val, 0, 4); 01044 unsigned type = fieldFromInstruction(Val, 5, 2); 01045 unsigned imm = fieldFromInstruction(Val, 7, 5); 01046 01047 // Register-immediate 01048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 01049 return MCDisassembler::Fail; 01050 01051 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 01052 switch (type) { 01053 case 0: 01054 Shift = ARM_AM::lsl; 01055 break; 01056 case 1: 01057 Shift = ARM_AM::lsr; 01058 break; 01059 case 2: 01060 Shift = ARM_AM::asr; 01061 break; 01062 case 3: 01063 Shift = ARM_AM::ror; 01064 break; 01065 } 01066 01067 if (Shift == ARM_AM::ror && imm == 0) 01068 Shift = ARM_AM::rrx; 01069 01070 unsigned Op = Shift | (imm << 3); 01071 Inst.addOperand(MCOperand::CreateImm(Op)); 01072 01073 return S; 01074 } 01075 01076 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 01077 uint64_t Address, const void *Decoder) { 01078 DecodeStatus S = MCDisassembler::Success; 01079 01080 unsigned Rm = fieldFromInstruction(Val, 0, 4); 01081 unsigned type = fieldFromInstruction(Val, 5, 2); 01082 unsigned Rs = fieldFromInstruction(Val, 8, 4); 01083 01084 // Register-register 01085 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 01086 return MCDisassembler::Fail; 01087 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 01088 return MCDisassembler::Fail; 01089 01090 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 01091 switch (type) { 01092 case 0: 01093 Shift = ARM_AM::lsl; 01094 break; 01095 case 1: 01096 Shift = ARM_AM::lsr; 01097 break; 01098 case 2: 01099 Shift = ARM_AM::asr; 01100 break; 01101 case 3: 01102 Shift = ARM_AM::ror; 01103 break; 01104 } 01105 01106 Inst.addOperand(MCOperand::CreateImm(Shift)); 01107 01108 return S; 01109 } 01110 01111 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 01112 uint64_t Address, const void *Decoder) { 01113 DecodeStatus S = MCDisassembler::Success; 01114 01115 bool writebackLoad = false; 01116 unsigned writebackReg = 0; 01117 switch (Inst.getOpcode()) { 01118 default: 01119 break; 01120 case ARM::LDMIA_UPD: 01121 case ARM::LDMDB_UPD: 01122 case ARM::LDMIB_UPD: 01123 case ARM::LDMDA_UPD: 01124 case ARM::t2LDMIA_UPD: 01125 case ARM::t2LDMDB_UPD: 01126 writebackLoad = true; 01127 writebackReg = Inst.getOperand(0).getReg(); 01128 break; 01129 } 01130 01131 // Empty register lists are not allowed. 01132 if (Val == 0) return MCDisassembler::Fail; 01133 for (unsigned i = 0; i < 16; ++i) { 01134 if (Val & (1 << i)) { 01135 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 01136 return MCDisassembler::Fail; 01137 // Writeback not allowed if Rn is in the target list. 01138 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 01139 Check(S, MCDisassembler::SoftFail); 01140 } 01141 } 01142 01143 return S; 01144 } 01145 01146 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 01147 uint64_t Address, const void *Decoder) { 01148 DecodeStatus S = MCDisassembler::Success; 01149 01150 unsigned Vd = fieldFromInstruction(Val, 8, 5); 01151 unsigned regs = fieldFromInstruction(Val, 0, 8); 01152 01153 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 01154 return MCDisassembler::Fail; 01155 for (unsigned i = 0; i < (regs - 1); ++i) { 01156 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 01157 return MCDisassembler::Fail; 01158 } 01159 01160 return S; 01161 } 01162 01163 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 01164 uint64_t Address, const void *Decoder) { 01165 DecodeStatus S = MCDisassembler::Success; 01166 01167 unsigned Vd = fieldFromInstruction(Val, 8, 5); 01168 unsigned regs = fieldFromInstruction(Val, 0, 8); 01169 01170 regs = regs >> 1; 01171 01172 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 01173 return MCDisassembler::Fail; 01174 for (unsigned i = 0; i < (regs - 1); ++i) { 01175 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 01176 return MCDisassembler::Fail; 01177 } 01178 01179 return S; 01180 } 01181 01182 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 01183 uint64_t Address, const void *Decoder) { 01184 // This operand encodes a mask of contiguous zeros between a specified MSB 01185 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 01186 // the mask of all bits LSB-and-lower, and then xor them to create 01187 // the mask of that's all ones on [msb, lsb]. Finally we not it to 01188 // create the final mask. 01189 unsigned msb = fieldFromInstruction(Val, 5, 5); 01190 unsigned lsb = fieldFromInstruction(Val, 0, 5); 01191 01192 DecodeStatus S = MCDisassembler::Success; 01193 if (lsb > msb) { 01194 Check(S, MCDisassembler::SoftFail); 01195 // The check above will cause the warning for the "potentially undefined 01196 // instruction encoding" but we can't build a bad MCOperand value here 01197 // with a lsb > msb or else printing the MCInst will cause a crash. 01198 lsb = msb; 01199 } 01200 01201 uint32_t msb_mask = 0xFFFFFFFF; 01202 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 01203 uint32_t lsb_mask = (1U << lsb) - 1; 01204 01205 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 01206 return S; 01207 } 01208 01209 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 01210 uint64_t Address, const void *Decoder) { 01211 DecodeStatus S = MCDisassembler::Success; 01212 01213 unsigned pred = fieldFromInstruction(Insn, 28, 4); 01214 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 01215 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 01216 unsigned imm = fieldFromInstruction(Insn, 0, 8); 01217 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 01218 unsigned U = fieldFromInstruction(Insn, 23, 1); 01219 01220 switch (Inst.getOpcode()) { 01221 case ARM::LDC_OFFSET: 01222 case ARM::LDC_PRE: 01223 case ARM::LDC_POST: 01224 case ARM::LDC_OPTION: 01225 case ARM::LDCL_OFFSET: 01226 case ARM::LDCL_PRE: 01227 case ARM::LDCL_POST: 01228 case ARM::LDCL_OPTION: 01229 case ARM::STC_OFFSET: 01230 case ARM::STC_PRE: 01231 case ARM::STC_POST: 01232 case ARM::STC_OPTION: 01233 case ARM::STCL_OFFSET: 01234 case ARM::STCL_PRE: 01235 case ARM::STCL_POST: 01236 case ARM::STCL_OPTION: 01237 case ARM::t2LDC_OFFSET: 01238 case ARM::t2LDC_PRE: 01239 case ARM::t2LDC_POST: 01240 case ARM::t2LDC_OPTION: 01241 case ARM::t2LDCL_OFFSET: 01242 case ARM::t2LDCL_PRE: 01243 case ARM::t2LDCL_POST: 01244 case ARM::t2LDCL_OPTION: 01245 case ARM::t2STC_OFFSET: 01246 case ARM::t2STC_PRE: 01247 case ARM::t2STC_POST: 01248 case ARM::t2STC_OPTION: 01249 case ARM::t2STCL_OFFSET: 01250 case ARM::t2STCL_PRE: 01251 case ARM::t2STCL_POST: 01252 case ARM::t2STCL_OPTION: 01253 if (coproc == 0xA || coproc == 0xB) 01254 return MCDisassembler::Fail; 01255 break; 01256 default: 01257 break; 01258 } 01259 01260 Inst.addOperand(MCOperand::CreateImm(coproc)); 01261 Inst.addOperand(MCOperand::CreateImm(CRd)); 01262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01263 return MCDisassembler::Fail; 01264 01265 switch (Inst.getOpcode()) { 01266 case ARM::t2LDC2_OFFSET: 01267 case ARM::t2LDC2L_OFFSET: 01268 case ARM::t2LDC2_PRE: 01269 case ARM::t2LDC2L_PRE: 01270 case ARM::t2STC2_OFFSET: 01271 case ARM::t2STC2L_OFFSET: 01272 case ARM::t2STC2_PRE: 01273 case ARM::t2STC2L_PRE: 01274 case ARM::LDC2_OFFSET: 01275 case ARM::LDC2L_OFFSET: 01276 case ARM::LDC2_PRE: 01277 case ARM::LDC2L_PRE: 01278 case ARM::STC2_OFFSET: 01279 case ARM::STC2L_OFFSET: 01280 case ARM::STC2_PRE: 01281 case ARM::STC2L_PRE: 01282 case ARM::t2LDC_OFFSET: 01283 case ARM::t2LDCL_OFFSET: 01284 case ARM::t2LDC_PRE: 01285 case ARM::t2LDCL_PRE: 01286 case ARM::t2STC_OFFSET: 01287 case ARM::t2STCL_OFFSET: 01288 case ARM::t2STC_PRE: 01289 case ARM::t2STCL_PRE: 01290 case ARM::LDC_OFFSET: 01291 case ARM::LDCL_OFFSET: 01292 case ARM::LDC_PRE: 01293 case ARM::LDCL_PRE: 01294 case ARM::STC_OFFSET: 01295 case ARM::STCL_OFFSET: 01296 case ARM::STC_PRE: 01297 case ARM::STCL_PRE: 01298 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 01299 Inst.addOperand(MCOperand::CreateImm(imm)); 01300 break; 01301 case ARM::t2LDC2_POST: 01302 case ARM::t2LDC2L_POST: 01303 case ARM::t2STC2_POST: 01304 case ARM::t2STC2L_POST: 01305 case ARM::LDC2_POST: 01306 case ARM::LDC2L_POST: 01307 case ARM::STC2_POST: 01308 case ARM::STC2L_POST: 01309 case ARM::t2LDC_POST: 01310 case ARM::t2LDCL_POST: 01311 case ARM::t2STC_POST: 01312 case ARM::t2STCL_POST: 01313 case ARM::LDC_POST: 01314 case ARM::LDCL_POST: 01315 case ARM::STC_POST: 01316 case ARM::STCL_POST: 01317 imm |= U << 8; 01318 // fall through. 01319 default: 01320 // The 'option' variant doesn't encode 'U' in the immediate since 01321 // the immediate is unsigned [0,255]. 01322 Inst.addOperand(MCOperand::CreateImm(imm)); 01323 break; 01324 } 01325 01326 switch (Inst.getOpcode()) { 01327 case ARM::LDC_OFFSET: 01328 case ARM::LDC_PRE: 01329 case ARM::LDC_POST: 01330 case ARM::LDC_OPTION: 01331 case ARM::LDCL_OFFSET: 01332 case ARM::LDCL_PRE: 01333 case ARM::LDCL_POST: 01334 case ARM::LDCL_OPTION: 01335 case ARM::STC_OFFSET: 01336 case ARM::STC_PRE: 01337 case ARM::STC_POST: 01338 case ARM::STC_OPTION: 01339 case ARM::STCL_OFFSET: 01340 case ARM::STCL_PRE: 01341 case ARM::STCL_POST: 01342 case ARM::STCL_OPTION: 01343 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 01344 return MCDisassembler::Fail; 01345 break; 01346 default: 01347 break; 01348 } 01349 01350 return S; 01351 } 01352 01353 static DecodeStatus 01354 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 01355 uint64_t Address, const void *Decoder) { 01356 DecodeStatus S = MCDisassembler::Success; 01357 01358 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 01359 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 01360 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 01361 unsigned imm = fieldFromInstruction(Insn, 0, 12); 01362 unsigned pred = fieldFromInstruction(Insn, 28, 4); 01363 unsigned reg = fieldFromInstruction(Insn, 25, 1); 01364 unsigned P = fieldFromInstruction(Insn, 24, 1); 01365 unsigned W = fieldFromInstruction(Insn, 21, 1); 01366 01367 // On stores, the writeback operand precedes Rt. 01368 switch (Inst.getOpcode()) { 01369 case ARM::STR_POST_IMM: 01370 case ARM::STR_POST_REG: 01371 case ARM::STRB_POST_IMM: 01372 case ARM::STRB_POST_REG: 01373 case ARM::STRT_POST_REG: 01374 case ARM::STRT_POST_IMM: 01375 case ARM::STRBT_POST_REG: 01376 case ARM::STRBT_POST_IMM: 01377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01378 return MCDisassembler::Fail; 01379 break; 01380 default: 01381 break; 01382 } 01383 01384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 01385 return MCDisassembler::Fail; 01386 01387 // On loads, the writeback operand comes after Rt. 01388 switch (Inst.getOpcode()) { 01389 case ARM::LDR_POST_IMM: 01390 case ARM::LDR_POST_REG: 01391 case ARM::LDRB_POST_IMM: 01392 case ARM::LDRB_POST_REG: 01393 case ARM::LDRBT_POST_REG: 01394 case ARM::LDRBT_POST_IMM: 01395 case ARM::LDRT_POST_REG: 01396 case ARM::LDRT_POST_IMM: 01397 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01398 return MCDisassembler::Fail; 01399 break; 01400 default: 01401 break; 01402 } 01403 01404 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01405 return MCDisassembler::Fail; 01406 01407 ARM_AM::AddrOpc Op = ARM_AM::add; 01408 if (!fieldFromInstruction(Insn, 23, 1)) 01409 Op = ARM_AM::sub; 01410 01411 bool writeback = (P == 0) || (W == 1); 01412 unsigned idx_mode = 0; 01413 if (P && writeback) 01414 idx_mode = ARMII::IndexModePre; 01415 else if (!P && writeback) 01416 idx_mode = ARMII::IndexModePost; 01417 01418 if (writeback && (Rn == 15 || Rn == Rt)) 01419 S = MCDisassembler::SoftFail; // UNPREDICTABLE 01420 01421 if (reg) { 01422 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 01423 return MCDisassembler::Fail; 01424 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 01425 switch( fieldFromInstruction(Insn, 5, 2)) { 01426 case 0: 01427 Opc = ARM_AM::lsl; 01428 break; 01429 case 1: 01430 Opc = ARM_AM::lsr; 01431 break; 01432 case 2: 01433 Opc = ARM_AM::asr; 01434 break; 01435 case 3: 01436 Opc = ARM_AM::ror; 01437 break; 01438 default: 01439 return MCDisassembler::Fail; 01440 } 01441 unsigned amt = fieldFromInstruction(Insn, 7, 5); 01442 if (Opc == ARM_AM::ror && amt == 0) 01443 Opc = ARM_AM::rrx; 01444 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 01445 01446 Inst.addOperand(MCOperand::CreateImm(imm)); 01447 } else { 01448 Inst.addOperand(MCOperand::CreateReg(0)); 01449 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 01450 Inst.addOperand(MCOperand::CreateImm(tmp)); 01451 } 01452 01453 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 01454 return MCDisassembler::Fail; 01455 01456 return S; 01457 } 01458 01459 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 01460 uint64_t Address, const void *Decoder) { 01461 DecodeStatus S = MCDisassembler::Success; 01462 01463 unsigned Rn = fieldFromInstruction(Val, 13, 4); 01464 unsigned Rm = fieldFromInstruction(Val, 0, 4); 01465 unsigned type = fieldFromInstruction(Val, 5, 2); 01466 unsigned imm = fieldFromInstruction(Val, 7, 5); 01467 unsigned U = fieldFromInstruction(Val, 12, 1); 01468 01469 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 01470 switch (type) { 01471 case 0: 01472 ShOp = ARM_AM::lsl; 01473 break; 01474 case 1: 01475 ShOp = ARM_AM::lsr; 01476 break; 01477 case 2: 01478 ShOp = ARM_AM::asr; 01479 break; 01480 case 3: 01481 ShOp = ARM_AM::ror; 01482 break; 01483 } 01484 01485 if (ShOp == ARM_AM::ror && imm == 0) 01486 ShOp = ARM_AM::rrx; 01487 01488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01489 return MCDisassembler::Fail; 01490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 01491 return MCDisassembler::Fail; 01492 unsigned shift; 01493 if (U) 01494 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 01495 else 01496 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 01497 Inst.addOperand(MCOperand::CreateImm(shift)); 01498 01499 return S; 01500 } 01501 01502 static DecodeStatus 01503 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 01504 uint64_t Address, const void *Decoder) { 01505 DecodeStatus S = MCDisassembler::Success; 01506 01507 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 01508 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 01509 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 01510 unsigned type = fieldFromInstruction(Insn, 22, 1); 01511 unsigned imm = fieldFromInstruction(Insn, 8, 4); 01512 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 01513 unsigned pred = fieldFromInstruction(Insn, 28, 4); 01514 unsigned W = fieldFromInstruction(Insn, 21, 1); 01515 unsigned P = fieldFromInstruction(Insn, 24, 1); 01516 unsigned Rt2 = Rt + 1; 01517 01518 bool writeback = (W == 1) | (P == 0); 01519 01520 // For {LD,ST}RD, Rt must be even, else undefined. 01521 switch (Inst.getOpcode()) { 01522 case ARM::STRD: 01523 case ARM::STRD_PRE: 01524 case ARM::STRD_POST: 01525 case ARM::LDRD: 01526 case ARM::LDRD_PRE: 01527 case ARM::LDRD_POST: 01528 if (Rt & 0x1) S = MCDisassembler::SoftFail; 01529 break; 01530 default: 01531 break; 01532 } 01533 switch (Inst.getOpcode()) { 01534 case ARM::STRD: 01535 case ARM::STRD_PRE: 01536 case ARM::STRD_POST: 01537 if (P == 0 && W == 1) 01538 S = MCDisassembler::SoftFail; 01539 01540 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 01541 S = MCDisassembler::SoftFail; 01542 if (type && Rm == 15) 01543 S = MCDisassembler::SoftFail; 01544 if (Rt2 == 15) 01545 S = MCDisassembler::SoftFail; 01546 if (!type && fieldFromInstruction(Insn, 8, 4)) 01547 S = MCDisassembler::SoftFail; 01548 break; 01549 case ARM::STRH: 01550 case ARM::STRH_PRE: 01551 case ARM::STRH_POST: 01552 if (Rt == 15) 01553 S = MCDisassembler::SoftFail; 01554 if (writeback && (Rn == 15 || Rn == Rt)) 01555 S = MCDisassembler::SoftFail; 01556 if (!type && Rm == 15) 01557 S = MCDisassembler::SoftFail; 01558 break; 01559 case ARM::LDRD: 01560 case ARM::LDRD_PRE: 01561 case ARM::LDRD_POST: 01562 if (type && Rn == 15){ 01563 if (Rt2 == 15) 01564 S = MCDisassembler::SoftFail; 01565 break; 01566 } 01567 if (P == 0 && W == 1) 01568 S = MCDisassembler::SoftFail; 01569 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 01570 S = MCDisassembler::SoftFail; 01571 if (!type && writeback && Rn == 15) 01572 S = MCDisassembler::SoftFail; 01573 if (writeback && (Rn == Rt || Rn == Rt2)) 01574 S = MCDisassembler::SoftFail; 01575 break; 01576 case ARM::LDRH: 01577 case ARM::LDRH_PRE: 01578 case ARM::LDRH_POST: 01579 if (type && Rn == 15){ 01580 if (Rt == 15) 01581 S = MCDisassembler::SoftFail; 01582 break; 01583 } 01584 if (Rt == 15) 01585 S = MCDisassembler::SoftFail; 01586 if (!type && Rm == 15) 01587 S = MCDisassembler::SoftFail; 01588 if (!type && writeback && (Rn == 15 || Rn == Rt)) 01589 S = MCDisassembler::SoftFail; 01590 break; 01591 case ARM::LDRSH: 01592 case ARM::LDRSH_PRE: 01593 case ARM::LDRSH_POST: 01594 case ARM::LDRSB: 01595 case ARM::LDRSB_PRE: 01596 case ARM::LDRSB_POST: 01597 if (type && Rn == 15){ 01598 if (Rt == 15) 01599 S = MCDisassembler::SoftFail; 01600 break; 01601 } 01602 if (type && (Rt == 15 || (writeback && Rn == Rt))) 01603 S = MCDisassembler::SoftFail; 01604 if (!type && (Rt == 15 || Rm == 15)) 01605 S = MCDisassembler::SoftFail; 01606 if (!type && writeback && (Rn == 15 || Rn == Rt)) 01607 S = MCDisassembler::SoftFail; 01608 break; 01609 default: 01610 break; 01611 } 01612 01613 if (writeback) { // Writeback 01614 if (P) 01615 U |= ARMII::IndexModePre << 9; 01616 else 01617 U |= ARMII::IndexModePost << 9; 01618 01619 // On stores, the writeback operand precedes Rt. 01620 switch (Inst.getOpcode()) { 01621 case ARM::STRD: 01622 case ARM::STRD_PRE: 01623 case ARM::STRD_POST: 01624 case ARM::STRH: 01625 case ARM::STRH_PRE: 01626 case ARM::STRH_POST: 01627 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01628 return MCDisassembler::Fail; 01629 break; 01630 default: 01631 break; 01632 } 01633 } 01634 01635 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 01636 return MCDisassembler::Fail; 01637 switch (Inst.getOpcode()) { 01638 case ARM::STRD: 01639 case ARM::STRD_PRE: 01640 case ARM::STRD_POST: 01641 case ARM::LDRD: 01642 case ARM::LDRD_PRE: 01643 case ARM::LDRD_POST: 01644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 01645 return MCDisassembler::Fail; 01646 break; 01647 default: 01648 break; 01649 } 01650 01651 if (writeback) { 01652 // On loads, the writeback operand comes after Rt. 01653 switch (Inst.getOpcode()) { 01654 case ARM::LDRD: 01655 case ARM::LDRD_PRE: 01656 case ARM::LDRD_POST: 01657 case ARM::LDRH: 01658 case ARM::LDRH_PRE: 01659 case ARM::LDRH_POST: 01660 case ARM::LDRSH: 01661 case ARM::LDRSH_PRE: 01662 case ARM::LDRSH_POST: 01663 case ARM::LDRSB: 01664 case ARM::LDRSB_PRE: 01665 case ARM::LDRSB_POST: 01666 case ARM::LDRHTr: 01667 case ARM::LDRSBTr: 01668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01669 return MCDisassembler::Fail; 01670 break; 01671 default: 01672 break; 01673 } 01674 } 01675 01676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01677 return MCDisassembler::Fail; 01678 01679 if (type) { 01680 Inst.addOperand(MCOperand::CreateReg(0)); 01681 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 01682 } else { 01683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 01684 return MCDisassembler::Fail; 01685 Inst.addOperand(MCOperand::CreateImm(U)); 01686 } 01687 01688 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 01689 return MCDisassembler::Fail; 01690 01691 return S; 01692 } 01693 01694 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 01695 uint64_t Address, const void *Decoder) { 01696 DecodeStatus S = MCDisassembler::Success; 01697 01698 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 01699 unsigned mode = fieldFromInstruction(Insn, 23, 2); 01700 01701 switch (mode) { 01702 case 0: 01703 mode = ARM_AM::da; 01704 break; 01705 case 1: 01706 mode = ARM_AM::ia; 01707 break; 01708 case 2: 01709 mode = ARM_AM::db; 01710 break; 01711 case 3: 01712 mode = ARM_AM::ib; 01713 break; 01714 } 01715 01716 Inst.addOperand(MCOperand::CreateImm(mode)); 01717 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01718 return MCDisassembler::Fail; 01719 01720 return S; 01721 } 01722 01723 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 01724 unsigned Insn, 01725 uint64_t Address, const void *Decoder) { 01726 DecodeStatus S = MCDisassembler::Success; 01727 01728 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 01729 unsigned pred = fieldFromInstruction(Insn, 28, 4); 01730 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 01731 01732 if (pred == 0xF) { 01733 switch (Inst.getOpcode()) { 01734 case ARM::LDMDA: 01735 Inst.setOpcode(ARM::RFEDA); 01736 break; 01737 case ARM::LDMDA_UPD: 01738 Inst.setOpcode(ARM::RFEDA_UPD); 01739 break; 01740 case ARM::LDMDB: 01741 Inst.setOpcode(ARM::RFEDB); 01742 break; 01743 case ARM::LDMDB_UPD: 01744 Inst.setOpcode(ARM::RFEDB_UPD); 01745 break; 01746 case ARM::LDMIA: 01747 Inst.setOpcode(ARM::RFEIA); 01748 break; 01749 case ARM::LDMIA_UPD: 01750 Inst.setOpcode(ARM::RFEIA_UPD); 01751 break; 01752 case ARM::LDMIB: 01753 Inst.setOpcode(ARM::RFEIB); 01754 break; 01755 case ARM::LDMIB_UPD: 01756 Inst.setOpcode(ARM::RFEIB_UPD); 01757 break; 01758 case ARM::STMDA: 01759 Inst.setOpcode(ARM::SRSDA); 01760 break; 01761 case ARM::STMDA_UPD: 01762 Inst.setOpcode(ARM::SRSDA_UPD); 01763 break; 01764 case ARM::STMDB: 01765 Inst.setOpcode(ARM::SRSDB); 01766 break; 01767 case ARM::STMDB_UPD: 01768 Inst.setOpcode(ARM::SRSDB_UPD); 01769 break; 01770 case ARM::STMIA: 01771 Inst.setOpcode(ARM::SRSIA); 01772 break; 01773 case ARM::STMIA_UPD: 01774 Inst.setOpcode(ARM::SRSIA_UPD); 01775 break; 01776 case ARM::STMIB: 01777 Inst.setOpcode(ARM::SRSIB); 01778 break; 01779 case ARM::STMIB_UPD: 01780 Inst.setOpcode(ARM::SRSIB_UPD); 01781 break; 01782 default: 01783 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 01784 } 01785 01786 // For stores (which become SRS's, the only operand is the mode. 01787 if (fieldFromInstruction(Insn, 20, 1) == 0) { 01788 Inst.addOperand( 01789 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 01790 return S; 01791 } 01792 01793 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 01794 } 01795 01796 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01797 return MCDisassembler::Fail; 01798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01799 return MCDisassembler::Fail; // Tied 01800 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 01801 return MCDisassembler::Fail; 01802 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 01803 return MCDisassembler::Fail; 01804 01805 return S; 01806 } 01807 01808 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 01809 uint64_t Address, const void *Decoder) { 01810 unsigned imod = fieldFromInstruction(Insn, 18, 2); 01811 unsigned M = fieldFromInstruction(Insn, 17, 1); 01812 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 01813 unsigned mode = fieldFromInstruction(Insn, 0, 5); 01814 01815 DecodeStatus S = MCDisassembler::Success; 01816 01817 // imod == '01' --> UNPREDICTABLE 01818 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 01819 // return failure here. The '01' imod value is unprintable, so there's 01820 // nothing useful we could do even if we returned UNPREDICTABLE. 01821 01822 if (imod == 1) return MCDisassembler::Fail; 01823 01824 if (imod && M) { 01825 Inst.setOpcode(ARM::CPS3p); 01826 Inst.addOperand(MCOperand::CreateImm(imod)); 01827 Inst.addOperand(MCOperand::CreateImm(iflags)); 01828 Inst.addOperand(MCOperand::CreateImm(mode)); 01829 } else if (imod && !M) { 01830 Inst.setOpcode(ARM::CPS2p); 01831 Inst.addOperand(MCOperand::CreateImm(imod)); 01832 Inst.addOperand(MCOperand::CreateImm(iflags)); 01833 if (mode) S = MCDisassembler::SoftFail; 01834 } else if (!imod && M) { 01835 Inst.setOpcode(ARM::CPS1p); 01836 Inst.addOperand(MCOperand::CreateImm(mode)); 01837 if (iflags) S = MCDisassembler::SoftFail; 01838 } else { 01839 // imod == '00' && M == '0' --> UNPREDICTABLE 01840 Inst.setOpcode(ARM::CPS1p); 01841 Inst.addOperand(MCOperand::CreateImm(mode)); 01842 S = MCDisassembler::SoftFail; 01843 } 01844 01845 return S; 01846 } 01847 01848 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 01849 uint64_t Address, const void *Decoder) { 01850 unsigned imod = fieldFromInstruction(Insn, 9, 2); 01851 unsigned M = fieldFromInstruction(Insn, 8, 1); 01852 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 01853 unsigned mode = fieldFromInstruction(Insn, 0, 5); 01854 01855 DecodeStatus S = MCDisassembler::Success; 01856 01857 // imod == '01' --> UNPREDICTABLE 01858 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 01859 // return failure here. The '01' imod value is unprintable, so there's 01860 // nothing useful we could do even if we returned UNPREDICTABLE. 01861 01862 if (imod == 1) return MCDisassembler::Fail; 01863 01864 if (imod && M) { 01865 Inst.setOpcode(ARM::t2CPS3p); 01866 Inst.addOperand(MCOperand::CreateImm(imod)); 01867 Inst.addOperand(MCOperand::CreateImm(iflags)); 01868 Inst.addOperand(MCOperand::CreateImm(mode)); 01869 } else if (imod && !M) { 01870 Inst.setOpcode(ARM::t2CPS2p); 01871 Inst.addOperand(MCOperand::CreateImm(imod)); 01872 Inst.addOperand(MCOperand::CreateImm(iflags)); 01873 if (mode) S = MCDisassembler::SoftFail; 01874 } else if (!imod && M) { 01875 Inst.setOpcode(ARM::t2CPS1p); 01876 Inst.addOperand(MCOperand::CreateImm(mode)); 01877 if (iflags) S = MCDisassembler::SoftFail; 01878 } else { 01879 // imod == '00' && M == '0' --> this is a HINT instruction 01880 int imm = fieldFromInstruction(Insn, 0, 8); 01881 // HINT are defined only for immediate in [0..4] 01882 if(imm > 4) return MCDisassembler::Fail; 01883 Inst.setOpcode(ARM::t2HINT); 01884 Inst.addOperand(MCOperand::CreateImm(imm)); 01885 } 01886 01887 return S; 01888 } 01889 01890 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 01891 uint64_t Address, const void *Decoder) { 01892 DecodeStatus S = MCDisassembler::Success; 01893 01894 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 01895 unsigned imm = 0; 01896 01897 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 01898 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 01899 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 01900 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 01901 01902 if (Inst.getOpcode() == ARM::t2MOVTi16) 01903 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 01904 return MCDisassembler::Fail; 01905 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 01906 return MCDisassembler::Fail; 01907 01908 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 01909 Inst.addOperand(MCOperand::CreateImm(imm)); 01910 01911 return S; 01912 } 01913 01914 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 01915 uint64_t Address, const void *Decoder) { 01916 DecodeStatus S = MCDisassembler::Success; 01917 01918 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 01919 unsigned pred = fieldFromInstruction(Insn, 28, 4); 01920 unsigned imm = 0; 01921 01922 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 01923 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 01924 01925 if (Inst.getOpcode() == ARM::MOVTi16) 01926 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 01927 return MCDisassembler::Fail; 01928 01929 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 01930 return MCDisassembler::Fail; 01931 01932 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 01933 Inst.addOperand(MCOperand::CreateImm(imm)); 01934 01935 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 01936 return MCDisassembler::Fail; 01937 01938 return S; 01939 } 01940 01941 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 01942 uint64_t Address, const void *Decoder) { 01943 DecodeStatus S = MCDisassembler::Success; 01944 01945 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 01946 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 01947 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 01948 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 01949 unsigned pred = fieldFromInstruction(Insn, 28, 4); 01950 01951 if (pred == 0xF) 01952 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 01953 01954 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 01955 return MCDisassembler::Fail; 01956 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 01957 return MCDisassembler::Fail; 01958 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 01959 return MCDisassembler::Fail; 01960 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 01961 return MCDisassembler::Fail; 01962 01963 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 01964 return MCDisassembler::Fail; 01965 01966 return S; 01967 } 01968 01969 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 01970 uint64_t Address, const void *Decoder) { 01971 DecodeStatus S = MCDisassembler::Success; 01972 01973 unsigned add = fieldFromInstruction(Val, 12, 1); 01974 unsigned imm = fieldFromInstruction(Val, 0, 12); 01975 unsigned Rn = fieldFromInstruction(Val, 13, 4); 01976 01977 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01978 return MCDisassembler::Fail; 01979 01980 if (!add) imm *= -1; 01981 if (imm == 0 && !add) imm = INT32_MIN; 01982 Inst.addOperand(MCOperand::CreateImm(imm)); 01983 if (Rn == 15) 01984 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 01985 01986 return S; 01987 } 01988 01989 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 01990 uint64_t Address, const void *Decoder) { 01991 DecodeStatus S = MCDisassembler::Success; 01992 01993 unsigned Rn = fieldFromInstruction(Val, 9, 4); 01994 unsigned U = fieldFromInstruction(Val, 8, 1); 01995 unsigned imm = fieldFromInstruction(Val, 0, 8); 01996 01997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01998 return MCDisassembler::Fail; 01999 02000 if (U) 02001 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 02002 else 02003 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 02004 02005 return S; 02006 } 02007 02008 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 02009 uint64_t Address, const void *Decoder) { 02010 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 02011 } 02012 02013 static DecodeStatus 02014 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 02015 uint64_t Address, const void *Decoder) { 02016 DecodeStatus Status = MCDisassembler::Success; 02017 02018 // Note the J1 and J2 values are from the encoded instruction. So here 02019 // change them to I1 and I2 values via as documented: 02020 // I1 = NOT(J1 EOR S); 02021 // I2 = NOT(J2 EOR S); 02022 // and build the imm32 with one trailing zero as documented: 02023 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 02024 unsigned S = fieldFromInstruction(Insn, 26, 1); 02025 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 02026 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 02027 unsigned I1 = !(J1 ^ S); 02028 unsigned I2 = !(J2 ^ S); 02029 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 02030 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 02031 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 02032 int imm32 = SignExtend32<24>(tmp << 1); 02033 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 02034 true, 4, Inst, Decoder)) 02035 Inst.addOperand(MCOperand::CreateImm(imm32)); 02036 02037 return Status; 02038 } 02039 02040 static DecodeStatus 02041 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 02042 uint64_t Address, const void *Decoder) { 02043 DecodeStatus S = MCDisassembler::Success; 02044 02045 unsigned pred = fieldFromInstruction(Insn, 28, 4); 02046 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 02047 02048 if (pred == 0xF) { 02049 Inst.setOpcode(ARM::BLXi); 02050 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 02051 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 02052 true, 4, Inst, Decoder)) 02053 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 02054 return S; 02055 } 02056 02057 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 02058 true, 4, Inst, Decoder)) 02059 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 02060 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 02061 return MCDisassembler::Fail; 02062 02063 return S; 02064 } 02065 02066 02067 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 02068 uint64_t Address, const void *Decoder) { 02069 DecodeStatus S = MCDisassembler::Success; 02070 02071 unsigned Rm = fieldFromInstruction(Val, 0, 4); 02072 unsigned align = fieldFromInstruction(Val, 4, 2); 02073 02074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02075 return MCDisassembler::Fail; 02076 if (!align) 02077 Inst.addOperand(MCOperand::CreateImm(0)); 02078 else 02079 Inst.addOperand(MCOperand::CreateImm(4 << align)); 02080 02081 return S; 02082 } 02083 02084 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 02085 uint64_t Address, const void *Decoder) { 02086 DecodeStatus S = MCDisassembler::Success; 02087 02088 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02089 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02090 unsigned wb = fieldFromInstruction(Insn, 16, 4); 02091 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02092 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 02093 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02094 02095 // First output register 02096 switch (Inst.getOpcode()) { 02097 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 02098 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 02099 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 02100 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 02101 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 02102 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 02103 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 02104 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 02105 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 02106 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 02107 return MCDisassembler::Fail; 02108 break; 02109 case ARM::VLD2b16: 02110 case ARM::VLD2b32: 02111 case ARM::VLD2b8: 02112 case ARM::VLD2b16wb_fixed: 02113 case ARM::VLD2b16wb_register: 02114 case ARM::VLD2b32wb_fixed: 02115 case ARM::VLD2b32wb_register: 02116 case ARM::VLD2b8wb_fixed: 02117 case ARM::VLD2b8wb_register: 02118 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 02119 return MCDisassembler::Fail; 02120 break; 02121 default: 02122 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02123 return MCDisassembler::Fail; 02124 } 02125 02126 // Second output register 02127 switch (Inst.getOpcode()) { 02128 case ARM::VLD3d8: 02129 case ARM::VLD3d16: 02130 case ARM::VLD3d32: 02131 case ARM::VLD3d8_UPD: 02132 case ARM::VLD3d16_UPD: 02133 case ARM::VLD3d32_UPD: 02134 case ARM::VLD4d8: 02135 case ARM::VLD4d16: 02136 case ARM::VLD4d32: 02137 case ARM::VLD4d8_UPD: 02138 case ARM::VLD4d16_UPD: 02139 case ARM::VLD4d32_UPD: 02140 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 02141 return MCDisassembler::Fail; 02142 break; 02143 case ARM::VLD3q8: 02144 case ARM::VLD3q16: 02145 case ARM::VLD3q32: 02146 case ARM::VLD3q8_UPD: 02147 case ARM::VLD3q16_UPD: 02148 case ARM::VLD3q32_UPD: 02149 case ARM::VLD4q8: 02150 case ARM::VLD4q16: 02151 case ARM::VLD4q32: 02152 case ARM::VLD4q8_UPD: 02153 case ARM::VLD4q16_UPD: 02154 case ARM::VLD4q32_UPD: 02155 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 02156 return MCDisassembler::Fail; 02157 default: 02158 break; 02159 } 02160 02161 // Third output register 02162 switch(Inst.getOpcode()) { 02163 case ARM::VLD3d8: 02164 case ARM::VLD3d16: 02165 case ARM::VLD3d32: 02166 case ARM::VLD3d8_UPD: 02167 case ARM::VLD3d16_UPD: 02168 case ARM::VLD3d32_UPD: 02169 case ARM::VLD4d8: 02170 case ARM::VLD4d16: 02171 case ARM::VLD4d32: 02172 case ARM::VLD4d8_UPD: 02173 case ARM::VLD4d16_UPD: 02174 case ARM::VLD4d32_UPD: 02175 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 02176 return MCDisassembler::Fail; 02177 break; 02178 case ARM::VLD3q8: 02179 case ARM::VLD3q16: 02180 case ARM::VLD3q32: 02181 case ARM::VLD3q8_UPD: 02182 case ARM::VLD3q16_UPD: 02183 case ARM::VLD3q32_UPD: 02184 case ARM::VLD4q8: 02185 case ARM::VLD4q16: 02186 case ARM::VLD4q32: 02187 case ARM::VLD4q8_UPD: 02188 case ARM::VLD4q16_UPD: 02189 case ARM::VLD4q32_UPD: 02190 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 02191 return MCDisassembler::Fail; 02192 break; 02193 default: 02194 break; 02195 } 02196 02197 // Fourth output register 02198 switch (Inst.getOpcode()) { 02199 case ARM::VLD4d8: 02200 case ARM::VLD4d16: 02201 case ARM::VLD4d32: 02202 case ARM::VLD4d8_UPD: 02203 case ARM::VLD4d16_UPD: 02204 case ARM::VLD4d32_UPD: 02205 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 02206 return MCDisassembler::Fail; 02207 break; 02208 case ARM::VLD4q8: 02209 case ARM::VLD4q16: 02210 case ARM::VLD4q32: 02211 case ARM::VLD4q8_UPD: 02212 case ARM::VLD4q16_UPD: 02213 case ARM::VLD4q32_UPD: 02214 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 02215 return MCDisassembler::Fail; 02216 break; 02217 default: 02218 break; 02219 } 02220 02221 // Writeback operand 02222 switch (Inst.getOpcode()) { 02223 case ARM::VLD1d8wb_fixed: 02224 case ARM::VLD1d16wb_fixed: 02225 case ARM::VLD1d32wb_fixed: 02226 case ARM::VLD1d64wb_fixed: 02227 case ARM::VLD1d8wb_register: 02228 case ARM::VLD1d16wb_register: 02229 case ARM::VLD1d32wb_register: 02230 case ARM::VLD1d64wb_register: 02231 case ARM::VLD1q8wb_fixed: 02232 case ARM::VLD1q16wb_fixed: 02233 case ARM::VLD1q32wb_fixed: 02234 case ARM::VLD1q64wb_fixed: 02235 case ARM::VLD1q8wb_register: 02236 case ARM::VLD1q16wb_register: 02237 case ARM::VLD1q32wb_register: 02238 case ARM::VLD1q64wb_register: 02239 case ARM::VLD1d8Twb_fixed: 02240 case ARM::VLD1d8Twb_register: 02241 case ARM::VLD1d16Twb_fixed: 02242 case ARM::VLD1d16Twb_register: 02243 case ARM::VLD1d32Twb_fixed: 02244 case ARM::VLD1d32Twb_register: 02245 case ARM::VLD1d64Twb_fixed: 02246 case ARM::VLD1d64Twb_register: 02247 case ARM::VLD1d8Qwb_fixed: 02248 case ARM::VLD1d8Qwb_register: 02249 case ARM::VLD1d16Qwb_fixed: 02250 case ARM::VLD1d16Qwb_register: 02251 case ARM::VLD1d32Qwb_fixed: 02252 case ARM::VLD1d32Qwb_register: 02253 case ARM::VLD1d64Qwb_fixed: 02254 case ARM::VLD1d64Qwb_register: 02255 case ARM::VLD2d8wb_fixed: 02256 case ARM::VLD2d16wb_fixed: 02257 case ARM::VLD2d32wb_fixed: 02258 case ARM::VLD2q8wb_fixed: 02259 case ARM::VLD2q16wb_fixed: 02260 case ARM::VLD2q32wb_fixed: 02261 case ARM::VLD2d8wb_register: 02262 case ARM::VLD2d16wb_register: 02263 case ARM::VLD2d32wb_register: 02264 case ARM::VLD2q8wb_register: 02265 case ARM::VLD2q16wb_register: 02266 case ARM::VLD2q32wb_register: 02267 case ARM::VLD2b8wb_fixed: 02268 case ARM::VLD2b16wb_fixed: 02269 case ARM::VLD2b32wb_fixed: 02270 case ARM::VLD2b8wb_register: 02271 case ARM::VLD2b16wb_register: 02272 case ARM::VLD2b32wb_register: 02273 Inst.addOperand(MCOperand::CreateImm(0)); 02274 break; 02275 case ARM::VLD3d8_UPD: 02276 case ARM::VLD3d16_UPD: 02277 case ARM::VLD3d32_UPD: 02278 case ARM::VLD3q8_UPD: 02279 case ARM::VLD3q16_UPD: 02280 case ARM::VLD3q32_UPD: 02281 case ARM::VLD4d8_UPD: 02282 case ARM::VLD4d16_UPD: 02283 case ARM::VLD4d32_UPD: 02284 case ARM::VLD4q8_UPD: 02285 case ARM::VLD4q16_UPD: 02286 case ARM::VLD4q32_UPD: 02287 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 02288 return MCDisassembler::Fail; 02289 break; 02290 default: 02291 break; 02292 } 02293 02294 // AddrMode6 Base (register+alignment) 02295 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 02296 return MCDisassembler::Fail; 02297 02298 // AddrMode6 Offset (register) 02299 switch (Inst.getOpcode()) { 02300 default: 02301 // The below have been updated to have explicit am6offset split 02302 // between fixed and register offset. For those instructions not 02303 // yet updated, we need to add an additional reg0 operand for the 02304 // fixed variant. 02305 // 02306 // The fixed offset encodes as Rm == 0xd, so we check for that. 02307 if (Rm == 0xd) { 02308 Inst.addOperand(MCOperand::CreateReg(0)); 02309 break; 02310 } 02311 // Fall through to handle the register offset variant. 02312 case ARM::VLD1d8wb_fixed: 02313 case ARM::VLD1d16wb_fixed: 02314 case ARM::VLD1d32wb_fixed: 02315 case ARM::VLD1d64wb_fixed: 02316 case ARM::VLD1d8Twb_fixed: 02317 case ARM::VLD1d16Twb_fixed: 02318 case ARM::VLD1d32Twb_fixed: 02319 case ARM::VLD1d64Twb_fixed: 02320 case ARM::VLD1d8Qwb_fixed: 02321 case ARM::VLD1d16Qwb_fixed: 02322 case ARM::VLD1d32Qwb_fixed: 02323 case ARM::VLD1d64Qwb_fixed: 02324 case ARM::VLD1d8wb_register: 02325 case ARM::VLD1d16wb_register: 02326 case ARM::VLD1d32wb_register: 02327 case ARM::VLD1d64wb_register: 02328 case ARM::VLD1q8wb_fixed: 02329 case ARM::VLD1q16wb_fixed: 02330 case ARM::VLD1q32wb_fixed: 02331 case ARM::VLD1q64wb_fixed: 02332 case ARM::VLD1q8wb_register: 02333 case ARM::VLD1q16wb_register: 02334 case ARM::VLD1q32wb_register: 02335 case ARM::VLD1q64wb_register: 02336 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 02337 // variant encodes Rm == 0xf. Anything else is a register offset post- 02338 // increment and we need to add the register operand to the instruction. 02339 if (Rm != 0xD && Rm != 0xF && 02340 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02341 return MCDisassembler::Fail; 02342 break; 02343 case ARM::VLD2d8wb_fixed: 02344 case ARM::VLD2d16wb_fixed: 02345 case ARM::VLD2d32wb_fixed: 02346 case ARM::VLD2b8wb_fixed: 02347 case ARM::VLD2b16wb_fixed: 02348 case ARM::VLD2b32wb_fixed: 02349 case ARM::VLD2q8wb_fixed: 02350 case ARM::VLD2q16wb_fixed: 02351 case ARM::VLD2q32wb_fixed: 02352 break; 02353 } 02354 02355 return S; 02356 } 02357 02358 static DecodeStatus DecodeVST1Instruction(MCInst& Inst, unsigned Insn, 02359 uint64_t Addr, const void* Decoder) { 02360 unsigned type = fieldFromInstruction(Insn, 8, 4); 02361 unsigned align = fieldFromInstruction(Insn, 4, 2); 02362 if(type == 7 && (align & 2)) return MCDisassembler::Fail; 02363 if(type == 10 && align == 3) return MCDisassembler::Fail; 02364 if(type == 6 && (align & 2)) return MCDisassembler::Fail; 02365 02366 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 02367 } 02368 02369 static DecodeStatus DecodeVST2Instruction(MCInst& Inst, unsigned Insn, 02370 uint64_t Addr, const void* Decoder) { 02371 unsigned size = fieldFromInstruction(Insn, 6, 2); 02372 if(size == 3) return MCDisassembler::Fail; 02373 02374 unsigned type = fieldFromInstruction(Insn, 8, 4); 02375 unsigned align = fieldFromInstruction(Insn, 4, 2); 02376 if(type == 8 && align == 3) return MCDisassembler::Fail; 02377 if(type == 9 && align == 3) return MCDisassembler::Fail; 02378 02379 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 02380 } 02381 02382 static DecodeStatus DecodeVST3Instruction(MCInst& Inst, unsigned Insn, 02383 uint64_t Addr, const void* Decoder) { 02384 unsigned size = fieldFromInstruction(Insn, 6, 2); 02385 if(size == 3) return MCDisassembler::Fail; 02386 02387 unsigned align = fieldFromInstruction(Insn, 4, 2); 02388 if(align & 2) return MCDisassembler::Fail; 02389 02390 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 02391 } 02392 02393 static DecodeStatus DecodeVST4Instruction(MCInst& Inst, unsigned Insn, 02394 uint64_t Addr, const void* Decoder) { 02395 unsigned size = fieldFromInstruction(Insn, 6, 2); 02396 if(size == 3) return MCDisassembler::Fail; 02397 02398 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 02399 } 02400 02401 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 02402 uint64_t Address, const void *Decoder) { 02403 DecodeStatus S = MCDisassembler::Success; 02404 02405 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02406 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02407 unsigned wb = fieldFromInstruction(Insn, 16, 4); 02408 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02409 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 02410 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02411 02412 // Writeback Operand 02413 switch (Inst.getOpcode()) { 02414 case ARM::VST1d8wb_fixed: 02415 case ARM::VST1d16wb_fixed: 02416 case ARM::VST1d32wb_fixed: 02417 case ARM::VST1d64wb_fixed: 02418 case ARM::VST1d8wb_register: 02419 case ARM::VST1d16wb_register: 02420 case ARM::VST1d32wb_register: 02421 case ARM::VST1d64wb_register: 02422 case ARM::VST1q8wb_fixed: 02423 case ARM::VST1q16wb_fixed: 02424 case ARM::VST1q32wb_fixed: 02425 case ARM::VST1q64wb_fixed: 02426 case ARM::VST1q8wb_register: 02427 case ARM::VST1q16wb_register: 02428 case ARM::VST1q32wb_register: 02429 case ARM::VST1q64wb_register: 02430 case ARM::VST1d8Twb_fixed: 02431 case ARM::VST1d16Twb_fixed: 02432 case ARM::VST1d32Twb_fixed: 02433 case ARM::VST1d64Twb_fixed: 02434 case ARM::VST1d8Twb_register: 02435 case ARM::VST1d16Twb_register: 02436 case ARM::VST1d32Twb_register: 02437 case ARM::VST1d64Twb_register: 02438 case ARM::VST1d8Qwb_fixed: 02439 case ARM::VST1d16Qwb_fixed: 02440 case ARM::VST1d32Qwb_fixed: 02441 case ARM::VST1d64Qwb_fixed: 02442 case ARM::VST1d8Qwb_register: 02443 case ARM::VST1d16Qwb_register: 02444 case ARM::VST1d32Qwb_register: 02445 case ARM::VST1d64Qwb_register: 02446 case ARM::VST2d8wb_fixed: 02447 case ARM::VST2d16wb_fixed: 02448 case ARM::VST2d32wb_fixed: 02449 case ARM::VST2d8wb_register: 02450 case ARM::VST2d16wb_register: 02451 case ARM::VST2d32wb_register: 02452 case ARM::VST2q8wb_fixed: 02453 case ARM::VST2q16wb_fixed: 02454 case ARM::VST2q32wb_fixed: 02455 case ARM::VST2q8wb_register: 02456 case ARM::VST2q16wb_register: 02457 case ARM::VST2q32wb_register: 02458 case ARM::VST2b8wb_fixed: 02459 case ARM::VST2b16wb_fixed: 02460 case ARM::VST2b32wb_fixed: 02461 case ARM::VST2b8wb_register: 02462 case ARM::VST2b16wb_register: 02463 case ARM::VST2b32wb_register: 02464 if (Rm == 0xF) 02465 return MCDisassembler::Fail; 02466 Inst.addOperand(MCOperand::CreateImm(0)); 02467 break; 02468 case ARM::VST3d8_UPD: 02469 case ARM::VST3d16_UPD: 02470 case ARM::VST3d32_UPD: 02471 case ARM::VST3q8_UPD: 02472 case ARM::VST3q16_UPD: 02473 case ARM::VST3q32_UPD: 02474 case ARM::VST4d8_UPD: 02475 case ARM::VST4d16_UPD: 02476 case ARM::VST4d32_UPD: 02477 case ARM::VST4q8_UPD: 02478 case ARM::VST4q16_UPD: 02479 case ARM::VST4q32_UPD: 02480 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 02481 return MCDisassembler::Fail; 02482 break; 02483 default: 02484 break; 02485 } 02486 02487 // AddrMode6 Base (register+alignment) 02488 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 02489 return MCDisassembler::Fail; 02490 02491 // AddrMode6 Offset (register) 02492 switch (Inst.getOpcode()) { 02493 default: 02494 if (Rm == 0xD) 02495 Inst.addOperand(MCOperand::CreateReg(0)); 02496 else if (Rm != 0xF) { 02497 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02498 return MCDisassembler::Fail; 02499 } 02500 break; 02501 case ARM::VST1d8wb_fixed: 02502 case ARM::VST1d16wb_fixed: 02503 case ARM::VST1d32wb_fixed: 02504 case ARM::VST1d64wb_fixed: 02505 case ARM::VST1q8wb_fixed: 02506 case ARM::VST1q16wb_fixed: 02507 case ARM::VST1q32wb_fixed: 02508 case ARM::VST1q64wb_fixed: 02509 case ARM::VST1d8Twb_fixed: 02510 case ARM::VST1d16Twb_fixed: 02511 case ARM::VST1d32Twb_fixed: 02512 case ARM::VST1d64Twb_fixed: 02513 case ARM::VST1d8Qwb_fixed: 02514 case ARM::VST1d16Qwb_fixed: 02515 case ARM::VST1d32Qwb_fixed: 02516 case ARM::VST1d64Qwb_fixed: 02517 case ARM::VST2d8wb_fixed: 02518 case ARM::VST2d16wb_fixed: 02519 case ARM::VST2d32wb_fixed: 02520 case ARM::VST2q8wb_fixed: 02521 case ARM::VST2q16wb_fixed: 02522 case ARM::VST2q32wb_fixed: 02523 case ARM::VST2b8wb_fixed: 02524 case ARM::VST2b16wb_fixed: 02525 case ARM::VST2b32wb_fixed: 02526 break; 02527 } 02528 02529 02530 // First input register 02531 switch (Inst.getOpcode()) { 02532 case ARM::VST1q16: 02533 case ARM::VST1q32: 02534 case ARM::VST1q64: 02535 case ARM::VST1q8: 02536 case ARM::VST1q16wb_fixed: 02537 case ARM::VST1q16wb_register: 02538 case ARM::VST1q32wb_fixed: 02539 case ARM::VST1q32wb_register: 02540 case ARM::VST1q64wb_fixed: 02541 case ARM::VST1q64wb_register: 02542 case ARM::VST1q8wb_fixed: 02543 case ARM::VST1q8wb_register: 02544 case ARM::VST2d16: 02545 case ARM::VST2d32: 02546 case ARM::VST2d8: 02547 case ARM::VST2d16wb_fixed: 02548 case ARM::VST2d16wb_register: 02549 case ARM::VST2d32wb_fixed: 02550 case ARM::VST2d32wb_register: 02551 case ARM::VST2d8wb_fixed: 02552 case ARM::VST2d8wb_register: 02553 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 02554 return MCDisassembler::Fail; 02555 break; 02556 case ARM::VST2b16: 02557 case ARM::VST2b32: 02558 case ARM::VST2b8: 02559 case ARM::VST2b16wb_fixed: 02560 case ARM::VST2b16wb_register: 02561 case ARM::VST2b32wb_fixed: 02562 case ARM::VST2b32wb_register: 02563 case ARM::VST2b8wb_fixed: 02564 case ARM::VST2b8wb_register: 02565 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 02566 return MCDisassembler::Fail; 02567 break; 02568 default: 02569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02570 return MCDisassembler::Fail; 02571 } 02572 02573 // Second input register 02574 switch (Inst.getOpcode()) { 02575 case ARM::VST3d8: 02576 case ARM::VST3d16: 02577 case ARM::VST3d32: 02578 case ARM::VST3d8_UPD: 02579 case ARM::VST3d16_UPD: 02580 case ARM::VST3d32_UPD: 02581 case ARM::VST4d8: 02582 case ARM::VST4d16: 02583 case ARM::VST4d32: 02584 case ARM::VST4d8_UPD: 02585 case ARM::VST4d16_UPD: 02586 case ARM::VST4d32_UPD: 02587 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 02588 return MCDisassembler::Fail; 02589 break; 02590 case ARM::VST3q8: 02591 case ARM::VST3q16: 02592 case ARM::VST3q32: 02593 case ARM::VST3q8_UPD: 02594 case ARM::VST3q16_UPD: 02595 case ARM::VST3q32_UPD: 02596 case ARM::VST4q8: 02597 case ARM::VST4q16: 02598 case ARM::VST4q32: 02599 case ARM::VST4q8_UPD: 02600 case ARM::VST4q16_UPD: 02601 case ARM::VST4q32_UPD: 02602 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 02603 return MCDisassembler::Fail; 02604 break; 02605 default: 02606 break; 02607 } 02608 02609 // Third input register 02610 switch (Inst.getOpcode()) { 02611 case ARM::VST3d8: 02612 case ARM::VST3d16: 02613 case ARM::VST3d32: 02614 case ARM::VST3d8_UPD: 02615 case ARM::VST3d16_UPD: 02616 case ARM::VST3d32_UPD: 02617 case ARM::VST4d8: 02618 case ARM::VST4d16: 02619 case ARM::VST4d32: 02620 case ARM::VST4d8_UPD: 02621 case ARM::VST4d16_UPD: 02622 case ARM::VST4d32_UPD: 02623 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 02624 return MCDisassembler::Fail; 02625 break; 02626 case ARM::VST3q8: 02627 case ARM::VST3q16: 02628 case ARM::VST3q32: 02629 case ARM::VST3q8_UPD: 02630 case ARM::VST3q16_UPD: 02631 case ARM::VST3q32_UPD: 02632 case ARM::VST4q8: 02633 case ARM::VST4q16: 02634 case ARM::VST4q32: 02635 case ARM::VST4q8_UPD: 02636 case ARM::VST4q16_UPD: 02637 case ARM::VST4q32_UPD: 02638 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 02639 return MCDisassembler::Fail; 02640 break; 02641 default: 02642 break; 02643 } 02644 02645 // Fourth input register 02646 switch (Inst.getOpcode()) { 02647 case ARM::VST4d8: 02648 case ARM::VST4d16: 02649 case ARM::VST4d32: 02650 case ARM::VST4d8_UPD: 02651 case ARM::VST4d16_UPD: 02652 case ARM::VST4d32_UPD: 02653 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 02654 return MCDisassembler::Fail; 02655 break; 02656 case ARM::VST4q8: 02657 case ARM::VST4q16: 02658 case ARM::VST4q32: 02659 case ARM::VST4q8_UPD: 02660 case ARM::VST4q16_UPD: 02661 case ARM::VST4q32_UPD: 02662 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 02663 return MCDisassembler::Fail; 02664 break; 02665 default: 02666 break; 02667 } 02668 02669 return S; 02670 } 02671 02672 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 02673 uint64_t Address, const void *Decoder) { 02674 DecodeStatus S = MCDisassembler::Success; 02675 02676 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02677 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02678 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02679 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02680 unsigned align = fieldFromInstruction(Insn, 4, 1); 02681 unsigned size = fieldFromInstruction(Insn, 6, 2); 02682 02683 if (size == 0 && align == 1) 02684 return MCDisassembler::Fail; 02685 align *= (1 << size); 02686 02687 switch (Inst.getOpcode()) { 02688 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 02689 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 02690 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 02691 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 02692 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 02693 return MCDisassembler::Fail; 02694 break; 02695 default: 02696 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02697 return MCDisassembler::Fail; 02698 break; 02699 } 02700 if (Rm != 0xF) { 02701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02702 return MCDisassembler::Fail; 02703 } 02704 02705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02706 return MCDisassembler::Fail; 02707 Inst.addOperand(MCOperand::CreateImm(align)); 02708 02709 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 02710 // variant encodes Rm == 0xf. Anything else is a register offset post- 02711 // increment and we need to add the register operand to the instruction. 02712 if (Rm != 0xD && Rm != 0xF && 02713 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02714 return MCDisassembler::Fail; 02715 02716 return S; 02717 } 02718 02719 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 02720 uint64_t Address, const void *Decoder) { 02721 DecodeStatus S = MCDisassembler::Success; 02722 02723 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02724 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02725 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02726 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02727 unsigned align = fieldFromInstruction(Insn, 4, 1); 02728 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 02729 align *= 2*size; 02730 02731 switch (Inst.getOpcode()) { 02732 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 02733 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 02734 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 02735 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 02736 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 02737 return MCDisassembler::Fail; 02738 break; 02739 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 02740 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 02741 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 02742 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 02743 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 02744 return MCDisassembler::Fail; 02745 break; 02746 default: 02747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02748 return MCDisassembler::Fail; 02749 break; 02750 } 02751 02752 if (Rm != 0xF) 02753 Inst.addOperand(MCOperand::CreateImm(0)); 02754 02755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02756 return MCDisassembler::Fail; 02757 Inst.addOperand(MCOperand::CreateImm(align)); 02758 02759 if (Rm != 0xD && Rm != 0xF) { 02760 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02761 return MCDisassembler::Fail; 02762 } 02763 02764 return S; 02765 } 02766 02767 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 02768 uint64_t Address, const void *Decoder) { 02769 DecodeStatus S = MCDisassembler::Success; 02770 02771 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02772 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02773 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02774 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02775 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 02776 02777 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02778 return MCDisassembler::Fail; 02779 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 02780 return MCDisassembler::Fail; 02781 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 02782 return MCDisassembler::Fail; 02783 if (Rm != 0xF) { 02784 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02785 return MCDisassembler::Fail; 02786 } 02787 02788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02789 return MCDisassembler::Fail; 02790 Inst.addOperand(MCOperand::CreateImm(0)); 02791 02792 if (Rm == 0xD) 02793 Inst.addOperand(MCOperand::CreateReg(0)); 02794 else if (Rm != 0xF) { 02795 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02796 return MCDisassembler::Fail; 02797 } 02798 02799 return S; 02800 } 02801 02802 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 02803 uint64_t Address, const void *Decoder) { 02804 DecodeStatus S = MCDisassembler::Success; 02805 02806 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02807 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02808 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02809 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02810 unsigned size = fieldFromInstruction(Insn, 6, 2); 02811 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 02812 unsigned align = fieldFromInstruction(Insn, 4, 1); 02813 02814 if (size == 0x3) { 02815 if (align == 0) 02816 return MCDisassembler::Fail; 02817 size = 4; 02818 align = 16; 02819 } else { 02820 if (size == 2) { 02821 size = 1 << size; 02822 align *= 8; 02823 } else { 02824 size = 1 << size; 02825 align *= 4*size; 02826 } 02827 } 02828 02829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02830 return MCDisassembler::Fail; 02831 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 02832 return MCDisassembler::Fail; 02833 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 02834 return MCDisassembler::Fail; 02835 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 02836 return MCDisassembler::Fail; 02837 if (Rm != 0xF) { 02838 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02839 return MCDisassembler::Fail; 02840 } 02841 02842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02843 return MCDisassembler::Fail; 02844 Inst.addOperand(MCOperand::CreateImm(align)); 02845 02846 if (Rm == 0xD) 02847 Inst.addOperand(MCOperand::CreateReg(0)); 02848 else if (Rm != 0xF) { 02849 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02850 return MCDisassembler::Fail; 02851 } 02852 02853 return S; 02854 } 02855 02856 static DecodeStatus 02857 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 02858 uint64_t Address, const void *Decoder) { 02859 DecodeStatus S = MCDisassembler::Success; 02860 02861 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02862 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02863 unsigned imm = fieldFromInstruction(Insn, 0, 4); 02864 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 02865 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 02866 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 02867 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 02868 unsigned Q = fieldFromInstruction(Insn, 6, 1); 02869 02870 if (Q) { 02871 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 02872 return MCDisassembler::Fail; 02873 } else { 02874 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02875 return MCDisassembler::Fail; 02876 } 02877 02878 Inst.addOperand(MCOperand::CreateImm(imm)); 02879 02880 switch (Inst.getOpcode()) { 02881 case ARM::VORRiv4i16: 02882 case ARM::VORRiv2i32: 02883 case ARM::VBICiv4i16: 02884 case ARM::VBICiv2i32: 02885 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02886 return MCDisassembler::Fail; 02887 break; 02888 case ARM::VORRiv8i16: 02889 case ARM::VORRiv4i32: 02890 case ARM::VBICiv8i16: 02891 case ARM::VBICiv4i32: 02892 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 02893 return MCDisassembler::Fail; 02894 break; 02895 default: 02896 break; 02897 } 02898 02899 return S; 02900 } 02901 02902 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 02903 uint64_t Address, const void *Decoder) { 02904 DecodeStatus S = MCDisassembler::Success; 02905 02906 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02907 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02908 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02909 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 02910 unsigned size = fieldFromInstruction(Insn, 18, 2); 02911 02912 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 02913 return MCDisassembler::Fail; 02914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 02915 return MCDisassembler::Fail; 02916 Inst.addOperand(MCOperand::CreateImm(8 << size)); 02917 02918 return S; 02919 } 02920 02921 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 02922 uint64_t Address, const void *Decoder) { 02923 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 02924 return MCDisassembler::Success; 02925 } 02926 02927 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 02928 uint64_t Address, const void *Decoder) { 02929 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 02930 return MCDisassembler::Success; 02931 } 02932 02933 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 02934 uint64_t Address, const void *Decoder) { 02935 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 02936 return MCDisassembler::Success; 02937 } 02938 02939 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 02940 uint64_t Address, const void *Decoder) { 02941 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 02942 return MCDisassembler::Success; 02943 } 02944 02945 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 02946 uint64_t Address, const void *Decoder) { 02947 DecodeStatus S = MCDisassembler::Success; 02948 02949 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02950 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02951 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02952 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 02953 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02954 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 02955 unsigned op = fieldFromInstruction(Insn, 6, 1); 02956 02957 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02958 return MCDisassembler::Fail; 02959 if (op) { 02960 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02961 return MCDisassembler::Fail; // Writeback 02962 } 02963 02964 switch (Inst.getOpcode()) { 02965 case ARM::VTBL2: 02966 case ARM::VTBX2: 02967 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 02968 return MCDisassembler::Fail; 02969 break; 02970 default: 02971 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 02972 return MCDisassembler::Fail; 02973 } 02974 02975 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 02976 return MCDisassembler::Fail; 02977 02978 return S; 02979 } 02980 02981 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 02982 uint64_t Address, const void *Decoder) { 02983 DecodeStatus S = MCDisassembler::Success; 02984 02985 unsigned dst = fieldFromInstruction(Insn, 8, 3); 02986 unsigned imm = fieldFromInstruction(Insn, 0, 8); 02987 02988 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 02989 return MCDisassembler::Fail; 02990 02991 switch(Inst.getOpcode()) { 02992 default: 02993 return MCDisassembler::Fail; 02994 case ARM::tADR: 02995 break; // tADR does not explicitly represent the PC as an operand. 02996 case ARM::tADDrSPi: 02997 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 02998 break; 02999 } 03000 03001 Inst.addOperand(MCOperand::CreateImm(imm)); 03002 return S; 03003 } 03004 03005 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 03006 uint64_t Address, const void *Decoder) { 03007 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 03008 true, 2, Inst, Decoder)) 03009 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 03010 return MCDisassembler::Success; 03011 } 03012 03013 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 03014 uint64_t Address, const void *Decoder) { 03015 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 03016 true, 4, Inst, Decoder)) 03017 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 03018 return MCDisassembler::Success; 03019 } 03020 03021 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 03022 uint64_t Address, const void *Decoder) { 03023 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 03024 true, 2, Inst, Decoder)) 03025 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 03026 return MCDisassembler::Success; 03027 } 03028 03029 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 03030 uint64_t Address, const void *Decoder) { 03031 DecodeStatus S = MCDisassembler::Success; 03032 03033 unsigned Rn = fieldFromInstruction(Val, 0, 3); 03034 unsigned Rm = fieldFromInstruction(Val, 3, 3); 03035 03036 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 03037 return MCDisassembler::Fail; 03038 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 03039 return MCDisassembler::Fail; 03040 03041 return S; 03042 } 03043 03044 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 03045 uint64_t Address, const void *Decoder) { 03046 DecodeStatus S = MCDisassembler::Success; 03047 03048 unsigned Rn = fieldFromInstruction(Val, 0, 3); 03049 unsigned imm = fieldFromInstruction(Val, 3, 5); 03050 03051 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 03052 return MCDisassembler::Fail; 03053 Inst.addOperand(MCOperand::CreateImm(imm)); 03054 03055 return S; 03056 } 03057 03058 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 03059 uint64_t Address, const void *Decoder) { 03060 unsigned imm = Val << 2; 03061 03062 Inst.addOperand(MCOperand::CreateImm(imm)); 03063 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 03064 03065 return MCDisassembler::Success; 03066 } 03067 03068 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 03069 uint64_t Address, const void *Decoder) { 03070 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03071 Inst.addOperand(MCOperand::CreateImm(Val)); 03072 03073 return MCDisassembler::Success; 03074 } 03075 03076 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 03077 uint64_t Address, const void *Decoder) { 03078 DecodeStatus S = MCDisassembler::Success; 03079 03080 unsigned Rn = fieldFromInstruction(Val, 6, 4); 03081 unsigned Rm = fieldFromInstruction(Val, 2, 4); 03082 unsigned imm = fieldFromInstruction(Val, 0, 2); 03083 03084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03085 return MCDisassembler::Fail; 03086 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 03087 return MCDisassembler::Fail; 03088 Inst.addOperand(MCOperand::CreateImm(imm)); 03089 03090 return S; 03091 } 03092 03093 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 03094 uint64_t Address, const void *Decoder) { 03095 DecodeStatus S = MCDisassembler::Success; 03096 03097 switch (Inst.getOpcode()) { 03098 case ARM::t2PLDs: 03099 case ARM::t2PLDWs: 03100 case ARM::t2PLIs: 03101 break; 03102 default: { 03103 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03104 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 03105 return MCDisassembler::Fail; 03106 } 03107 } 03108 03109 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03110 if (Rn == 0xF) { 03111 switch (Inst.getOpcode()) { 03112 case ARM::t2LDRBs: 03113 Inst.setOpcode(ARM::t2LDRBpci); 03114 break; 03115 case ARM::t2LDRHs: 03116 Inst.setOpcode(ARM::t2LDRHpci); 03117 break; 03118 case ARM::t2LDRSHs: 03119 Inst.setOpcode(ARM::t2LDRSHpci); 03120 break; 03121 case ARM::t2LDRSBs: 03122 Inst.setOpcode(ARM::t2LDRSBpci); 03123 break; 03124 case ARM::t2PLDs: 03125 Inst.setOpcode(ARM::t2PLDi12); 03126 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 03127 break; 03128 default: 03129 return MCDisassembler::Fail; 03130 } 03131 03132 int imm = fieldFromInstruction(Insn, 0, 12); 03133 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1; 03134 Inst.addOperand(MCOperand::CreateImm(imm)); 03135 03136 return S; 03137 } 03138 03139 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 03140 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 03141 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 03142 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 03143 return MCDisassembler::Fail; 03144 03145 return S; 03146 } 03147 03148 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 03149 uint64_t Address, const void *Decoder) { 03150 if (Val == 0) 03151 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 03152 else { 03153 int imm = Val & 0xFF; 03154 03155 if (!(Val & 0x100)) imm *= -1; 03156 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 03157 } 03158 03159 return MCDisassembler::Success; 03160 } 03161 03162 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 03163 uint64_t Address, const void *Decoder) { 03164 DecodeStatus S = MCDisassembler::Success; 03165 03166 unsigned Rn = fieldFromInstruction(Val, 9, 4); 03167 unsigned imm = fieldFromInstruction(Val, 0, 9); 03168 03169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03170 return MCDisassembler::Fail; 03171 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 03172 return MCDisassembler::Fail; 03173 03174 return S; 03175 } 03176 03177 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 03178 uint64_t Address, const void *Decoder) { 03179 DecodeStatus S = MCDisassembler::Success; 03180 03181 unsigned Rn = fieldFromInstruction(Val, 8, 4); 03182 unsigned imm = fieldFromInstruction(Val, 0, 8); 03183 03184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 03185 return MCDisassembler::Fail; 03186 03187 Inst.addOperand(MCOperand::CreateImm(imm)); 03188 03189 return S; 03190 } 03191 03192 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 03193 uint64_t Address, const void *Decoder) { 03194 int imm = Val & 0xFF; 03195 if (Val == 0) 03196 imm = INT32_MIN; 03197 else if (!(Val & 0x100)) 03198 imm *= -1; 03199 Inst.addOperand(MCOperand::CreateImm(imm)); 03200 03201 return MCDisassembler::Success; 03202 } 03203 03204 03205 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 03206 uint64_t Address, const void *Decoder) { 03207 DecodeStatus S = MCDisassembler::Success; 03208 03209 unsigned Rn = fieldFromInstruction(Val, 9, 4); 03210 unsigned imm = fieldFromInstruction(Val, 0, 9); 03211 03212 // Some instructions always use an additive offset. 03213 switch (Inst.getOpcode()) { 03214 case ARM::t2LDRT: 03215 case ARM::t2LDRBT: 03216 case ARM::t2LDRHT: 03217 case ARM::t2LDRSBT: 03218 case ARM::t2LDRSHT: 03219 case ARM::t2STRT: 03220 case ARM::t2STRBT: 03221 case ARM::t2STRHT: 03222 imm |= 0x100; 03223 break; 03224 default: 03225 break; 03226 } 03227 03228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03229 return MCDisassembler::Fail; 03230 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 03231 return MCDisassembler::Fail; 03232 03233 return S; 03234 } 03235 03236 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 03237 uint64_t Address, const void *Decoder) { 03238 DecodeStatus S = MCDisassembler::Success; 03239 03240 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03241 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03242 unsigned addr = fieldFromInstruction(Insn, 0, 8); 03243 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 03244 addr |= Rn << 9; 03245 unsigned load = fieldFromInstruction(Insn, 20, 1); 03246 03247 if (!load) { 03248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03249 return MCDisassembler::Fail; 03250 } 03251 03252 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 03253 return MCDisassembler::Fail; 03254 03255 if (load) { 03256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03257 return MCDisassembler::Fail; 03258 } 03259 03260 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 03261 return MCDisassembler::Fail; 03262 03263 return S; 03264 } 03265 03266 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 03267 uint64_t Address, const void *Decoder) { 03268 DecodeStatus S = MCDisassembler::Success; 03269 03270 unsigned Rn = fieldFromInstruction(Val, 13, 4); 03271 unsigned imm = fieldFromInstruction(Val, 0, 12); 03272 03273 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03274 return MCDisassembler::Fail; 03275 Inst.addOperand(MCOperand::CreateImm(imm)); 03276 03277 return S; 03278 } 03279 03280 03281 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 03282 uint64_t Address, const void *Decoder) { 03283 unsigned imm = fieldFromInstruction(Insn, 0, 7); 03284 03285 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03286 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03287 Inst.addOperand(MCOperand::CreateImm(imm)); 03288 03289 return MCDisassembler::Success; 03290 } 03291 03292 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 03293 uint64_t Address, const void *Decoder) { 03294 DecodeStatus S = MCDisassembler::Success; 03295 03296 if (Inst.getOpcode() == ARM::tADDrSP) { 03297 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 03298 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 03299 03300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 03301 return MCDisassembler::Fail; 03302 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 03304 return MCDisassembler::Fail; 03305 } else if (Inst.getOpcode() == ARM::tADDspr) { 03306 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 03307 03308 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03309 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 03311 return MCDisassembler::Fail; 03312 } 03313 03314 return S; 03315 } 03316 03317 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 03318 uint64_t Address, const void *Decoder) { 03319 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 03320 unsigned flags = fieldFromInstruction(Insn, 0, 3); 03321 03322 Inst.addOperand(MCOperand::CreateImm(imod)); 03323 Inst.addOperand(MCOperand::CreateImm(flags)); 03324 03325 return MCDisassembler::Success; 03326 } 03327 03328 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 03329 uint64_t Address, const void *Decoder) { 03330 DecodeStatus S = MCDisassembler::Success; 03331 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 03332 unsigned add = fieldFromInstruction(Insn, 4, 1); 03333 03334 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 03335 return MCDisassembler::Fail; 03336 Inst.addOperand(MCOperand::CreateImm(add)); 03337 03338 return S; 03339 } 03340 03341 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 03342 uint64_t Address, const void *Decoder) { 03343 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 03344 // Note only one trailing zero not two. Also the J1 and J2 values are from 03345 // the encoded instruction. So here change to I1 and I2 values via: 03346 // I1 = NOT(J1 EOR S); 03347 // I2 = NOT(J2 EOR S); 03348 // and build the imm32 with two trailing zeros as documented: 03349 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 03350 unsigned S = (Val >> 23) & 1; 03351 unsigned J1 = (Val >> 22) & 1; 03352 unsigned J2 = (Val >> 21) & 1; 03353 unsigned I1 = !(J1 ^ S); 03354 unsigned I2 = !(J2 ^ S); 03355 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 03356 int imm32 = SignExtend32<25>(tmp << 1); 03357 03358 if (!tryAddingSymbolicOperand(Address, 03359 (Address & ~2u) + imm32 + 4, 03360 true, 4, Inst, Decoder)) 03361 Inst.addOperand(MCOperand::CreateImm(imm32)); 03362 return MCDisassembler::Success; 03363 } 03364 03365 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 03366 uint64_t Address, const void *Decoder) { 03367 if (Val == 0xA || Val == 0xB) 03368 return MCDisassembler::Fail; 03369 03370 Inst.addOperand(MCOperand::CreateImm(Val)); 03371 return MCDisassembler::Success; 03372 } 03373 03374 static DecodeStatus 03375 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 03376 uint64_t Address, const void *Decoder) { 03377 DecodeStatus S = MCDisassembler::Success; 03378 03379 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03380 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 03381 03382 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 03383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03384 return MCDisassembler::Fail; 03385 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 03386 return MCDisassembler::Fail; 03387 return S; 03388 } 03389 03390 static DecodeStatus 03391 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 03392 uint64_t Address, const void *Decoder) { 03393 DecodeStatus S = MCDisassembler::Success; 03394 03395 unsigned pred = fieldFromInstruction(Insn, 22, 4); 03396 if (pred == 0xE || pred == 0xF) { 03397 unsigned opc = fieldFromInstruction(Insn, 4, 28); 03398 switch (opc) { 03399 default: 03400 return MCDisassembler::Fail; 03401 case 0xf3bf8f4: 03402 Inst.setOpcode(ARM::t2DSB); 03403 break; 03404 case 0xf3bf8f5: 03405 Inst.setOpcode(ARM::t2DMB); 03406 break; 03407 case 0xf3bf8f6: 03408 Inst.setOpcode(ARM::t2ISB); 03409 break; 03410 } 03411 03412 unsigned imm = fieldFromInstruction(Insn, 0, 4); 03413 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 03414 } 03415 03416 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 03417 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 03418 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 03419 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 03420 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 03421 03422 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 03423 return MCDisassembler::Fail; 03424 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 03425 return MCDisassembler::Fail; 03426 03427 return S; 03428 } 03429 03430 // Decode a shifted immediate operand. These basically consist 03431 // of an 8-bit value, and a 4-bit directive that specifies either 03432 // a splat operation or a rotation. 03433 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 03434 uint64_t Address, const void *Decoder) { 03435 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 03436 if (ctrl == 0) { 03437 unsigned byte = fieldFromInstruction(Val, 8, 2); 03438 unsigned imm = fieldFromInstruction(Val, 0, 8); 03439 switch (byte) { 03440 case 0: 03441 Inst.addOperand(MCOperand::CreateImm(imm)); 03442 break; 03443 case 1: 03444 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 03445 break; 03446 case 2: 03447 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 03448 break; 03449 case 3: 03450 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 03451 (imm << 8) | imm)); 03452 break; 03453 } 03454 } else { 03455 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 03456 unsigned rot = fieldFromInstruction(Val, 7, 5); 03457 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 03458 Inst.addOperand(MCOperand::CreateImm(imm)); 03459 } 03460 03461 return MCDisassembler::Success; 03462 } 03463 03464 static DecodeStatus 03465 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 03466 uint64_t Address, const void *Decoder){ 03467 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 03468 true, 2, Inst, Decoder)) 03469 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 03470 return MCDisassembler::Success; 03471 } 03472 03473 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 03474 uint64_t Address, const void *Decoder){ 03475 // Val is passed in as S:J1:J2:imm10:imm11 03476 // Note no trailing zero after imm11. Also the J1 and J2 values are from 03477 // the encoded instruction. So here change to I1 and I2 values via: 03478 // I1 = NOT(J1 EOR S); 03479 // I2 = NOT(J2 EOR S); 03480 // and build the imm32 with one trailing zero as documented: 03481 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 03482 unsigned S = (Val >> 23) & 1; 03483 unsigned J1 = (Val >> 22) & 1; 03484 unsigned J2 = (Val >> 21) & 1; 03485 unsigned I1 = !(J1 ^ S); 03486 unsigned I2 = !(J2 ^ S); 03487 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 03488 int imm32 = SignExtend32<25>(tmp << 1); 03489 03490 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 03491 true, 4, Inst, Decoder)) 03492 Inst.addOperand(MCOperand::CreateImm(imm32)); 03493 return MCDisassembler::Success; 03494 } 03495 03496 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 03497 uint64_t Address, const void *Decoder) { 03498 if (Val & ~0xf) 03499 return MCDisassembler::Fail; 03500 03501 Inst.addOperand(MCOperand::CreateImm(Val)); 03502 return MCDisassembler::Success; 03503 } 03504 03505 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 03506 uint64_t Address, const void *Decoder) { 03507 if (!Val) return MCDisassembler::Fail; 03508 Inst.addOperand(MCOperand::CreateImm(Val)); 03509 return MCDisassembler::Success; 03510 } 03511 03512 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 03513 uint64_t Address, const void *Decoder) { 03514 DecodeStatus S = MCDisassembler::Success; 03515 03516 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03517 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03518 unsigned pred = fieldFromInstruction(Insn, 28, 4); 03519 03520 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 03521 03522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 03523 return MCDisassembler::Fail; 03524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 03525 return MCDisassembler::Fail; 03526 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03527 return MCDisassembler::Fail; 03528 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 03529 return MCDisassembler::Fail; 03530 03531 return S; 03532 } 03533 03534 03535 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 03536 uint64_t Address, const void *Decoder){ 03537 DecodeStatus S = MCDisassembler::Success; 03538 03539 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 03540 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 03541 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03542 unsigned pred = fieldFromInstruction(Insn, 28, 4); 03543 03544 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 03545 return MCDisassembler::Fail; 03546 03547 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 03548 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 03549 03550 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 03551 return MCDisassembler::Fail; 03552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 03553 return MCDisassembler::Fail; 03554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03555 return MCDisassembler::Fail; 03556 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 03557 return MCDisassembler::Fail; 03558 03559 return S; 03560 } 03561 03562 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 03563 uint64_t Address, const void *Decoder) { 03564 DecodeStatus S = MCDisassembler::Success; 03565 03566 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03567 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03568 unsigned imm = fieldFromInstruction(Insn, 0, 12); 03569 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 03570 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 03571 unsigned pred = fieldFromInstruction(Insn, 28, 4); 03572 03573 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 03574 03575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 03576 return MCDisassembler::Fail; 03577 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03578 return MCDisassembler::Fail; 03579 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 03580 return MCDisassembler::Fail; 03581 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 03582 return MCDisassembler::Fail; 03583 03584 return S; 03585 } 03586 03587 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 03588 uint64_t Address, const void *Decoder) { 03589 DecodeStatus S = MCDisassembler::Success; 03590 03591 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03592 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03593 unsigned imm = fieldFromInstruction(Insn, 0, 12); 03594 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 03595 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 03596 unsigned pred = fieldFromInstruction(Insn, 28, 4); 03597 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 03598 03599 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 03600 if (Rm == 0xF) S = MCDisassembler::SoftFail; 03601 03602 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 03603 return MCDisassembler::Fail; 03604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03605 return MCDisassembler::Fail; 03606 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 03607 return MCDisassembler::Fail; 03608 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 03609 return MCDisassembler::Fail; 03610 03611 return S; 03612 } 03613 03614 03615 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 03616 uint64_t Address, const void *Decoder) { 03617 DecodeStatus S = MCDisassembler::Success; 03618 03619 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03620 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03621 unsigned imm = fieldFromInstruction(Insn, 0, 12); 03622 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 03623 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 03624 unsigned pred = fieldFromInstruction(Insn, 28, 4); 03625 03626 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 03627 03628 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03629 return MCDisassembler::Fail; 03630 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 03631 return MCDisassembler::Fail; 03632 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 03633 return MCDisassembler::Fail; 03634 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 03635 return MCDisassembler::Fail; 03636 03637 return S; 03638 } 03639 03640 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 03641 uint64_t Address, const void *Decoder) { 03642 DecodeStatus S = MCDisassembler::Success; 03643 03644 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03645 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03646 unsigned imm = fieldFromInstruction(Insn, 0, 12); 03647 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 03648 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 03649 unsigned pred = fieldFromInstruction(Insn, 28, 4); 03650 03651 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 03652 03653 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03654 return MCDisassembler::Fail; 03655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 03656 return MCDisassembler::Fail; 03657 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 03658 return MCDisassembler::Fail; 03659 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 03660 return MCDisassembler::Fail; 03661 03662 return S; 03663 } 03664 03665 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 03666 uint64_t Address, const void *Decoder) { 03667 DecodeStatus S = MCDisassembler::Success; 03668 03669 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03670 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 03671 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 03672 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 03673 unsigned size = fieldFromInstruction(Insn, 10, 2); 03674 03675 unsigned align = 0; 03676 unsigned index = 0; 03677 switch (size) { 03678 default: 03679 return MCDisassembler::Fail; 03680 case 0: 03681 if (fieldFromInstruction(Insn, 4, 1)) 03682 return MCDisassembler::Fail; // UNDEFINED 03683 index = fieldFromInstruction(Insn, 5, 3); 03684 break; 03685 case 1: 03686 if (fieldFromInstruction(Insn, 5, 1)) 03687 return MCDisassembler::Fail; // UNDEFINED 03688 index = fieldFromInstruction(Insn, 6, 2); 03689 if (fieldFromInstruction(Insn, 4, 1)) 03690 align = 2; 03691 break; 03692 case 2: 03693 if (fieldFromInstruction(Insn, 6, 1)) 03694 return MCDisassembler::Fail; // UNDEFINED 03695 index = fieldFromInstruction(Insn, 7, 1); 03696 03697 switch (fieldFromInstruction(Insn, 4, 2)) { 03698 case 0 : 03699 align = 0; break; 03700 case 3: 03701 align = 4; break; 03702 default: 03703 return MCDisassembler::Fail; 03704 } 03705 break; 03706 } 03707 03708 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 03709 return MCDisassembler::Fail; 03710 if (Rm != 0xF) { // Writeback 03711 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03712 return MCDisassembler::Fail; 03713 } 03714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03715 return MCDisassembler::Fail; 03716 Inst.addOperand(MCOperand::CreateImm(align)); 03717 if (Rm != 0xF) { 03718 if (Rm != 0xD) { 03719 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 03720 return MCDisassembler::Fail; 03721 } else 03722 Inst.addOperand(MCOperand::CreateReg(0)); 03723 } 03724 03725 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 03726 return MCDisassembler::Fail; 03727 Inst.addOperand(MCOperand::CreateImm(index)); 03728 03729 return S; 03730 } 03731 03732 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 03733 uint64_t Address, const void *Decoder) { 03734 DecodeStatus S = MCDisassembler::Success; 03735 03736 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03737 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 03738 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 03739 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 03740 unsigned size = fieldFromInstruction(Insn, 10, 2); 03741 03742 unsigned align = 0; 03743 unsigned index = 0; 03744 switch (size) { 03745 default: 03746 return MCDisassembler::Fail; 03747 case 0: 03748 if (fieldFromInstruction(Insn, 4, 1)) 03749 return MCDisassembler::Fail; // UNDEFINED 03750 index = fieldFromInstruction(Insn, 5, 3); 03751 break; 03752 case 1: 03753 if (fieldFromInstruction(Insn, 5, 1)) 03754 return MCDisassembler::Fail; // UNDEFINED 03755 index = fieldFromInstruction(Insn, 6, 2); 03756 if (fieldFromInstruction(Insn, 4, 1)) 03757 align = 2; 03758 break; 03759 case 2: 03760 if (fieldFromInstruction(Insn, 6, 1)) 03761 return MCDisassembler::Fail; // UNDEFINED 03762 index = fieldFromInstruction(Insn, 7, 1); 03763 03764 switch (fieldFromInstruction(Insn, 4, 2)) { 03765 case 0: 03766 align = 0; break; 03767 case 3: 03768 align = 4; break; 03769 default: 03770 return MCDisassembler::Fail; 03771 } 03772 break; 03773 } 03774 03775 if (Rm != 0xF) { // Writeback 03776 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03777 return MCDisassembler::Fail; 03778 } 03779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03780 return MCDisassembler::Fail; 03781 Inst.addOperand(MCOperand::CreateImm(align)); 03782 if (Rm != 0xF) { 03783 if (Rm != 0xD) { 03784 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 03785 return MCDisassembler::Fail; 03786 } else 03787 Inst.addOperand(MCOperand::CreateReg(0)); 03788 } 03789 03790 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 03791 return MCDisassembler::Fail; 03792 Inst.addOperand(MCOperand::CreateImm(index)); 03793 03794 return S; 03795 } 03796 03797 03798 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 03799 uint64_t Address, const void *Decoder) { 03800 DecodeStatus S = MCDisassembler::Success; 03801 03802 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03803 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 03804 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 03805 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 03806 unsigned size = fieldFromInstruction(Insn, 10, 2); 03807 03808 unsigned align = 0; 03809 unsigned index = 0; 03810 unsigned inc = 1; 03811 switch (size) { 03812 default: 03813 return MCDisassembler::Fail; 03814 case 0: 03815 index = fieldFromInstruction(Insn, 5, 3); 03816 if (fieldFromInstruction(Insn, 4, 1)) 03817 align = 2; 03818 break; 03819 case 1: 03820 index = fieldFromInstruction(Insn, 6, 2); 03821 if (fieldFromInstruction(Insn, 4, 1)) 03822 align = 4; 03823 if (fieldFromInstruction(Insn, 5, 1)) 03824 inc = 2; 03825 break; 03826 case 2: 03827 if (fieldFromInstruction(Insn, 5, 1)) 03828 return MCDisassembler::Fail; // UNDEFINED 03829 index = fieldFromInstruction(Insn, 7, 1); 03830 if (fieldFromInstruction(Insn, 4, 1) != 0) 03831 align = 8; 03832 if (fieldFromInstruction(Insn, 6, 1)) 03833 inc = 2; 03834 break; 03835 } 03836 03837 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 03838 return MCDisassembler::Fail; 03839 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 03840 return MCDisassembler::Fail; 03841 if (Rm != 0xF) { // Writeback 03842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03843 return MCDisassembler::Fail; 03844 } 03845 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03846 return MCDisassembler::Fail; 03847 Inst.addOperand(MCOperand::CreateImm(align)); 03848 if (Rm != 0xF) { 03849 if (Rm != 0xD) { 03850 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 03851 return MCDisassembler::Fail; 03852 } else 03853 Inst.addOperand(MCOperand::CreateReg(0)); 03854 } 03855 03856 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 03857 return MCDisassembler::Fail; 03858 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 03859 return MCDisassembler::Fail; 03860 Inst.addOperand(MCOperand::CreateImm(index)); 03861 03862 return S; 03863 } 03864 03865 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 03866 uint64_t Address, const void *Decoder) { 03867 DecodeStatus S = MCDisassembler::Success; 03868 03869 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03870 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 03871 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 03872 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 03873 unsigned size = fieldFromInstruction(Insn, 10, 2); 03874 03875 unsigned align = 0; 03876 unsigned index = 0; 03877 unsigned inc = 1; 03878 switch (size) { 03879 default: 03880 return MCDisassembler::Fail; 03881 case 0: 03882 index = fieldFromInstruction(Insn, 5, 3); 03883 if (fieldFromInstruction(Insn, 4, 1)) 03884 align = 2; 03885 break; 03886 case 1: 03887 index = fieldFromInstruction(Insn, 6, 2); 03888 if (fieldFromInstruction(Insn, 4, 1)) 03889 align = 4; 03890 if (fieldFromInstruction(Insn, 5, 1)) 03891 inc = 2; 03892 break; 03893 case 2: 03894 if (fieldFromInstruction(Insn, 5, 1)) 03895 return MCDisassembler::Fail; // UNDEFINED 03896 index = fieldFromInstruction(Insn, 7, 1); 03897 if (fieldFromInstruction(Insn, 4, 1) != 0) 03898 align = 8; 03899 if (fieldFromInstruction(Insn, 6, 1)) 03900 inc = 2; 03901 break; 03902 } 03903 03904 if (Rm != 0xF) { // Writeback 03905 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03906 return MCDisassembler::Fail; 03907 } 03908 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03909 return MCDisassembler::Fail; 03910 Inst.addOperand(MCOperand::CreateImm(align)); 03911 if (Rm != 0xF) { 03912 if (Rm != 0xD) { 03913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 03914 return MCDisassembler::Fail; 03915 } else 03916 Inst.addOperand(MCOperand::CreateReg(0)); 03917 } 03918 03919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 03920 return MCDisassembler::Fail; 03921 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 03922 return MCDisassembler::Fail; 03923 Inst.addOperand(MCOperand::CreateImm(index)); 03924 03925 return S; 03926 } 03927 03928 03929 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 03930 uint64_t Address, const void *Decoder) { 03931 DecodeStatus S = MCDisassembler::Success; 03932 03933 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03934 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 03935 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 03936 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 03937 unsigned size = fieldFromInstruction(Insn, 10, 2); 03938 03939 unsigned align = 0; 03940 unsigned index = 0; 03941 unsigned inc = 1; 03942 switch (size) { 03943 default: 03944 return MCDisassembler::Fail; 03945 case 0: 03946 if (fieldFromInstruction(Insn, 4, 1)) 03947 return MCDisassembler::Fail; // UNDEFINED 03948 index = fieldFromInstruction(Insn, 5, 3); 03949 break; 03950 case 1: 03951 if (fieldFromInstruction(Insn, 4, 1)) 03952 return MCDisassembler::Fail; // UNDEFINED 03953 index = fieldFromInstruction(Insn, 6, 2); 03954 if (fieldFromInstruction(Insn, 5, 1)) 03955 inc = 2; 03956 break; 03957 case 2: 03958 if (fieldFromInstruction(Insn, 4, 2)) 03959 return MCDisassembler::Fail; // UNDEFINED 03960 index = fieldFromInstruction(Insn, 7, 1); 03961 if (fieldFromInstruction(Insn, 6, 1)) 03962 inc = 2; 03963 break; 03964 } 03965 03966 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 03967 return MCDisassembler::Fail; 03968 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 03969 return MCDisassembler::Fail; 03970 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 03971 return MCDisassembler::Fail; 03972 03973 if (Rm != 0xF) { // Writeback 03974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03975 return MCDisassembler::Fail; 03976 } 03977 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03978 return MCDisassembler::Fail; 03979 Inst.addOperand(MCOperand::CreateImm(align)); 03980 if (Rm != 0xF) { 03981 if (Rm != 0xD) { 03982 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 03983 return MCDisassembler::Fail; 03984 } else 03985 Inst.addOperand(MCOperand::CreateReg(0)); 03986 } 03987 03988 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 03989 return MCDisassembler::Fail; 03990 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 03991 return MCDisassembler::Fail; 03992 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 03993 return MCDisassembler::Fail; 03994 Inst.addOperand(MCOperand::CreateImm(index)); 03995 03996 return S; 03997 } 03998 03999 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 04000 uint64_t Address, const void *Decoder) { 04001 DecodeStatus S = MCDisassembler::Success; 04002 04003 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04004 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 04005 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 04006 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 04007 unsigned size = fieldFromInstruction(Insn, 10, 2); 04008 04009 unsigned align = 0; 04010 unsigned index = 0; 04011 unsigned inc = 1; 04012 switch (size) { 04013 default: 04014 return MCDisassembler::Fail; 04015 case 0: 04016 if (fieldFromInstruction(Insn, 4, 1)) 04017 return MCDisassembler::Fail; // UNDEFINED 04018 index = fieldFromInstruction(Insn, 5, 3); 04019 break; 04020 case 1: 04021 if (fieldFromInstruction(Insn, 4, 1)) 04022 return MCDisassembler::Fail; // UNDEFINED 04023 index = fieldFromInstruction(Insn, 6, 2); 04024 if (fieldFromInstruction(Insn, 5, 1)) 04025 inc = 2; 04026 break; 04027 case 2: 04028 if (fieldFromInstruction(Insn, 4, 2)) 04029 return MCDisassembler::Fail; // UNDEFINED 04030 index = fieldFromInstruction(Insn, 7, 1); 04031 if (fieldFromInstruction(Insn, 6, 1)) 04032 inc = 2; 04033 break; 04034 } 04035 04036 if (Rm != 0xF) { // Writeback 04037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04038 return MCDisassembler::Fail; 04039 } 04040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04041 return MCDisassembler::Fail; 04042 Inst.addOperand(MCOperand::CreateImm(align)); 04043 if (Rm != 0xF) { 04044 if (Rm != 0xD) { 04045 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 04046 return MCDisassembler::Fail; 04047 } else 04048 Inst.addOperand(MCOperand::CreateReg(0)); 04049 } 04050 04051 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04052 return MCDisassembler::Fail; 04053 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04054 return MCDisassembler::Fail; 04055 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 04056 return MCDisassembler::Fail; 04057 Inst.addOperand(MCOperand::CreateImm(index)); 04058 04059 return S; 04060 } 04061 04062 04063 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 04064 uint64_t Address, const void *Decoder) { 04065 DecodeStatus S = MCDisassembler::Success; 04066 04067 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04068 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 04069 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 04070 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 04071 unsigned size = fieldFromInstruction(Insn, 10, 2); 04072 04073 unsigned align = 0; 04074 unsigned index = 0; 04075 unsigned inc = 1; 04076 switch (size) { 04077 default: 04078 return MCDisassembler::Fail; 04079 case 0: 04080 if (fieldFromInstruction(Insn, 4, 1)) 04081 align = 4; 04082 index = fieldFromInstruction(Insn, 5, 3); 04083 break; 04084 case 1: 04085 if (fieldFromInstruction(Insn, 4, 1)) 04086 align = 8; 04087 index = fieldFromInstruction(Insn, 6, 2); 04088 if (fieldFromInstruction(Insn, 5, 1)) 04089 inc = 2; 04090 break; 04091 case 2: 04092 switch (fieldFromInstruction(Insn, 4, 2)) { 04093 case 0: 04094 align = 0; break; 04095 case 3: 04096 return MCDisassembler::Fail; 04097 default: 04098 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 04099 } 04100 04101 index = fieldFromInstruction(Insn, 7, 1); 04102 if (fieldFromInstruction(Insn, 6, 1)) 04103 inc = 2; 04104 break; 04105 } 04106 04107 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04108 return MCDisassembler::Fail; 04109 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04110 return MCDisassembler::Fail; 04111 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 04112 return MCDisassembler::Fail; 04113 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 04114 return MCDisassembler::Fail; 04115 04116 if (Rm != 0xF) { // Writeback 04117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04118 return MCDisassembler::Fail; 04119 } 04120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04121 return MCDisassembler::Fail; 04122 Inst.addOperand(MCOperand::CreateImm(align)); 04123 if (Rm != 0xF) { 04124 if (Rm != 0xD) { 04125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 04126 return MCDisassembler::Fail; 04127 } else 04128 Inst.addOperand(MCOperand::CreateReg(0)); 04129 } 04130 04131 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04132 return MCDisassembler::Fail; 04133 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04134 return MCDisassembler::Fail; 04135 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 04136 return MCDisassembler::Fail; 04137 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 04138 return MCDisassembler::Fail; 04139 Inst.addOperand(MCOperand::CreateImm(index)); 04140 04141 return S; 04142 } 04143 04144 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 04145 uint64_t Address, const void *Decoder) { 04146 DecodeStatus S = MCDisassembler::Success; 04147 04148 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04149 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 04150 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 04151 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 04152 unsigned size = fieldFromInstruction(Insn, 10, 2); 04153 04154 unsigned align = 0; 04155 unsigned index = 0; 04156 unsigned inc = 1; 04157 switch (size) { 04158 default: 04159 return MCDisassembler::Fail; 04160 case 0: 04161 if (fieldFromInstruction(Insn, 4, 1)) 04162 align = 4; 04163 index = fieldFromInstruction(Insn, 5, 3); 04164 break; 04165 case 1: 04166 if (fieldFromInstruction(Insn, 4, 1)) 04167 align = 8; 04168 index = fieldFromInstruction(Insn, 6, 2); 04169 if (fieldFromInstruction(Insn, 5, 1)) 04170 inc = 2; 04171 break; 04172 case 2: 04173 switch (fieldFromInstruction(Insn, 4, 2)) { 04174 case 0: 04175 align = 0; break; 04176 case 3: 04177 return MCDisassembler::Fail; 04178 default: 04179 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 04180 } 04181 04182 index = fieldFromInstruction(Insn, 7, 1); 04183 if (fieldFromInstruction(Insn, 6, 1)) 04184 inc = 2; 04185 break; 04186 } 04187 04188 if (Rm != 0xF) { // Writeback 04189 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04190 return MCDisassembler::Fail; 04191 } 04192 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04193 return MCDisassembler::Fail; 04194 Inst.addOperand(MCOperand::CreateImm(align)); 04195 if (Rm != 0xF) { 04196 if (Rm != 0xD) { 04197 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 04198 return MCDisassembler::Fail; 04199 } else 04200 Inst.addOperand(MCOperand::CreateReg(0)); 04201 } 04202 04203 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04204 return MCDisassembler::Fail; 04205 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04206 return MCDisassembler::Fail; 04207 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 04208 return MCDisassembler::Fail; 04209 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 04210 return MCDisassembler::Fail; 04211 Inst.addOperand(MCOperand::CreateImm(index)); 04212 04213 return S; 04214 } 04215 04216 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 04217 uint64_t Address, const void *Decoder) { 04218 DecodeStatus S = MCDisassembler::Success; 04219 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04220 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 04221 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 04222 unsigned pred = fieldFromInstruction(Insn, 28, 4); 04223 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 04224 04225 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 04226 S = MCDisassembler::SoftFail; 04227 04228 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 04229 return MCDisassembler::Fail; 04230 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 04231 return MCDisassembler::Fail; 04232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 04233 return MCDisassembler::Fail; 04234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 04235 return MCDisassembler::Fail; 04236 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 04237 return MCDisassembler::Fail; 04238 04239 return S; 04240 } 04241 04242 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 04243 uint64_t Address, const void *Decoder) { 04244 DecodeStatus S = MCDisassembler::Success; 04245 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04246 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 04247 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 04248 unsigned pred = fieldFromInstruction(Insn, 28, 4); 04249 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 04250 04251 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 04252 S = MCDisassembler::SoftFail; 04253 04254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 04255 return MCDisassembler::Fail; 04256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 04257 return MCDisassembler::Fail; 04258 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 04259 return MCDisassembler::Fail; 04260 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 04261 return MCDisassembler::Fail; 04262 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 04263 return MCDisassembler::Fail; 04264 04265 return S; 04266 } 04267 04268 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 04269 uint64_t Address, const void *Decoder) { 04270 DecodeStatus S = MCDisassembler::Success; 04271 unsigned pred = fieldFromInstruction(Insn, 4, 4); 04272 unsigned mask = fieldFromInstruction(Insn, 0, 4); 04273 04274 if (pred == 0xF) { 04275 pred = 0xE; 04276 S = MCDisassembler::SoftFail; 04277 } 04278 04279 if (mask == 0x0) { 04280 mask |= 0x8; 04281 S = MCDisassembler::SoftFail; 04282 } 04283 04284 Inst.addOperand(MCOperand::CreateImm(pred)); 04285 Inst.addOperand(MCOperand::CreateImm(mask)); 04286 return S; 04287 } 04288 04289 static DecodeStatus 04290 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 04291 uint64_t Address, const void *Decoder) { 04292 DecodeStatus S = MCDisassembler::Success; 04293 04294 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04295 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 04296 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04297 unsigned addr = fieldFromInstruction(Insn, 0, 8); 04298 unsigned W = fieldFromInstruction(Insn, 21, 1); 04299 unsigned U = fieldFromInstruction(Insn, 23, 1); 04300 unsigned P = fieldFromInstruction(Insn, 24, 1); 04301 bool writeback = (W == 1) | (P == 0); 04302 04303 addr |= (U << 8) | (Rn << 9); 04304 04305 if (writeback && (Rn == Rt || Rn == Rt2)) 04306 Check(S, MCDisassembler::SoftFail); 04307 if (Rt == Rt2) 04308 Check(S, MCDisassembler::SoftFail); 04309 04310 // Rt 04311 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 04312 return MCDisassembler::Fail; 04313 // Rt2 04314 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 04315 return MCDisassembler::Fail; 04316 // Writeback operand 04317 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 04318 return MCDisassembler::Fail; 04319 // addr 04320 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 04321 return MCDisassembler::Fail; 04322 04323 return S; 04324 } 04325 04326 static DecodeStatus 04327 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 04328 uint64_t Address, const void *Decoder) { 04329 DecodeStatus S = MCDisassembler::Success; 04330 04331 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04332 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 04333 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04334 unsigned addr = fieldFromInstruction(Insn, 0, 8); 04335 unsigned W = fieldFromInstruction(Insn, 21, 1); 04336 unsigned U = fieldFromInstruction(Insn, 23, 1); 04337 unsigned P = fieldFromInstruction(Insn, 24, 1); 04338 bool writeback = (W == 1) | (P == 0); 04339 04340 addr |= (U << 8) | (Rn << 9); 04341 04342 if (writeback && (Rn == Rt || Rn == Rt2)) 04343 Check(S, MCDisassembler::SoftFail); 04344 04345 // Writeback operand 04346 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 04347 return MCDisassembler::Fail; 04348 // Rt 04349 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 04350 return MCDisassembler::Fail; 04351 // Rt2 04352 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 04353 return MCDisassembler::Fail; 04354 // addr 04355 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 04356 return MCDisassembler::Fail; 04357 04358 return S; 04359 } 04360 04361 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 04362 uint64_t Address, const void *Decoder) { 04363 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 04364 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 04365 if (sign1 != sign2) return MCDisassembler::Fail; 04366 04367 unsigned Val = fieldFromInstruction(Insn, 0, 8); 04368 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 04369 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 04370 Val |= sign1 << 12; 04371 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 04372 04373 return MCDisassembler::Success; 04374 } 04375 04376 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 04377 uint64_t Address, 04378 const void *Decoder) { 04379 DecodeStatus S = MCDisassembler::Success; 04380 04381 // Shift of "asr #32" is not allowed in Thumb2 mode. 04382 if (Val == 0x20) S = MCDisassembler::SoftFail; 04383 Inst.addOperand(MCOperand::CreateImm(Val)); 04384 return S; 04385 } 04386 04387 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 04388 uint64_t Address, const void *Decoder) { 04389 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04390 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 04391 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04392 unsigned pred = fieldFromInstruction(Insn, 28, 4); 04393 04394 if (pred == 0xF) 04395 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 04396 04397 DecodeStatus S = MCDisassembler::Success; 04398 04399 if (Rt == Rn || Rn == Rt2) 04400 S = MCDisassembler::SoftFail; 04401 04402 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 04403 return MCDisassembler::Fail; 04404 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 04405 return MCDisassembler::Fail; 04406 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 04407 return MCDisassembler::Fail; 04408 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 04409 return MCDisassembler::Fail; 04410 04411 return S; 04412 } 04413 04414 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 04415 uint64_t Address, const void *Decoder) { 04416 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 04417 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 04418 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 04419 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 04420 unsigned imm = fieldFromInstruction(Insn, 16, 6); 04421 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 04422 04423 DecodeStatus S = MCDisassembler::Success; 04424 04425 // VMOVv2f32 is ambiguous with these decodings. 04426 if (!(imm & 0x38) && cmode == 0xF) { 04427 Inst.setOpcode(ARM::VMOVv2f32); 04428 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 04429 } 04430 04431 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 04432 04433 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 04434 return MCDisassembler::Fail; 04435 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 04436 return MCDisassembler::Fail; 04437 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 04438 04439 return S; 04440 } 04441 04442 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 04443 uint64_t Address, const void *Decoder) { 04444 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 04445 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 04446 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 04447 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 04448 unsigned imm = fieldFromInstruction(Insn, 16, 6); 04449 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 04450 04451 DecodeStatus S = MCDisassembler::Success; 04452 04453 // VMOVv4f32 is ambiguous with these decodings. 04454 if (!(imm & 0x38) && cmode == 0xF) { 04455 Inst.setOpcode(ARM::VMOVv4f32); 04456 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 04457 } 04458 04459 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 04460 04461 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 04462 return MCDisassembler::Fail; 04463 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 04464 return MCDisassembler::Fail; 04465 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 04466 04467 return S; 04468 } 04469 04470 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 04471 const void *Decoder) 04472 { 04473 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 04474 if (Imm > 4) return MCDisassembler::Fail; 04475 Inst.addOperand(MCOperand::CreateImm(Imm)); 04476 return MCDisassembler::Success; 04477 } 04478 04479 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 04480 uint64_t Address, const void *Decoder) { 04481 DecodeStatus S = MCDisassembler::Success; 04482 04483 unsigned Rn = fieldFromInstruction(Val, 16, 4); 04484 unsigned Rt = fieldFromInstruction(Val, 12, 4); 04485 unsigned Rm = fieldFromInstruction(Val, 0, 4); 04486 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 04487 unsigned Cond = fieldFromInstruction(Val, 28, 4); 04488 04489 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 04490 S = MCDisassembler::SoftFail; 04491 04492 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 04493 return MCDisassembler::Fail; 04494 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 04495 return MCDisassembler::Fail; 04496 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 04497 return MCDisassembler::Fail; 04498 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 04499 return MCDisassembler::Fail; 04500 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 04501 return MCDisassembler::Fail; 04502 04503 return S; 04504 } 04505 04506 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 04507 uint64_t Address, const void *Decoder) { 04508 04509 DecodeStatus S = MCDisassembler::Success; 04510 04511 unsigned CRm = fieldFromInstruction(Val, 0, 4); 04512 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 04513 unsigned cop = fieldFromInstruction(Val, 8, 4); 04514 unsigned Rt = fieldFromInstruction(Val, 12, 4); 04515 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 04516 04517 if ((cop & ~0x1) == 0xa) 04518 return MCDisassembler::Fail; 04519 04520 if (Rt == Rt2) 04521 S = MCDisassembler::SoftFail; 04522 04523 Inst.addOperand(MCOperand::CreateImm(cop)); 04524 Inst.addOperand(MCOperand::CreateImm(opc1)); 04525 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 04526 return MCDisassembler::Fail; 04527 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 04528 return MCDisassembler::Fail; 04529 Inst.addOperand(MCOperand::CreateImm(CRm)); 04530 04531 return S; 04532 } 04533
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