37#define DEBUG_TYPE "arm-disassembler"
55 void advanceITState() { ITStates.pop_back(); }
58 bool instrInITBlock() {
return !ITStates.empty(); }
61 bool instrLastInITBlock() {
return ITStates.size() == 1; }
67 void setITState(
char Firstcond,
char Mask) {
70 unsigned char CCBits =
static_cast<unsigned char>(Firstcond & 0xf);
71 assert(NumTZ <= 3 &&
"Invalid IT mask!");
73 for (
unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
74 unsigned Else = (Mask >> Pos) & 1;
75 ITStates.push_back(CCBits ^ Else);
77 ITStates.push_back(CCBits);
81 std::vector<unsigned char> ITStates;
86 unsigned getVPTPred() {
88 if (instrInVPTBlock())
89 Pred = VPTStates.back();
93 void advanceVPTState() { VPTStates.pop_back(); }
95 bool instrInVPTBlock() {
return !VPTStates.empty(); }
97 bool instrLastInVPTBlock() {
return VPTStates.size() == 1; }
99 void setVPTState(
char Mask) {
102 assert(NumTZ <= 3 &&
"Invalid VPT mask!");
104 for (
unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
105 bool T = ((Mask >> Pos) & 1) == 0;
121 std::unique_ptr<const MCInstrInfo> MCII;
122 mutable ITStatus ITBlock;
123 mutable VPTStatus VPTBlock;
128 InstructionEndianness = STI.
hasFeature(ARM::ModeBigEndianInstructions)
133 ~ARMDisassembler()
override =
default;
203 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
204 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
205 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
206 ARM::R12, ARM::SP, ARM::LR, ARM::PC
210 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
211 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
212 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
213 ARM::R12, 0, ARM::LR, ARM::APSR
319 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
320 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
350 if ((RegNo & 1) || RegNo > 10)
405 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
413 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
414 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
415 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
416 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
417 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
418 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
419 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
420 ARM::S28, ARM::S29, ARM::S30, ARM::S31
441 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
442 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
443 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
444 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
445 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
446 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
447 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
448 ARM::D28, ARM::D29, ARM::D30, ARM::D31
457 return featureBits[ARM::FeatureD32];
463 if (RegNo > (
PermitsD32(Inst, Decoder) ? 31u : 15u))
496 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
497 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
498 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
499 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
505 if (RegNo > 31 || (RegNo & 1) != 0)
515 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
516 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
517 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
518 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
519 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
535 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
536 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
537 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
538 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
539 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
540 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
541 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
542 ARM::D28_D30, ARM::D29_D31
568 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
569 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
584 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
585 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
607 if (Inst.
getOpcode() == ARM::tBcc && Val == 0xE)
610 static_cast<const ARMDisassembler *
>(Decoder)->MCII.
get();
635 const auto *
D =
static_cast<const ARMDisassembler *
>(Decoder);
637 MCRegister CCR =
D->ITBlock.instrInITBlock() ? ARM::NoRegister : ARM::CPSR;
644 const auto *
D =
static_cast<const ARMDisassembler *
>(Decoder);
645 unsigned VCC =
D->VPTBlock.getVPTPred();
657 const auto *
D =
static_cast<const ARMDisassembler *
>(Decoder);
658 unsigned VCC =
D->VPTBlock.getVPTPred();
671 "Inactive register in vpred_r is not tied to an output!");
711 unsigned Op = Shift | (imm << 3);
758 bool NeedDisjointWriteback =
false;
768 case ARM::t2LDMIA_UPD:
769 case ARM::t2LDMDB_UPD:
770 case ARM::t2STMIA_UPD:
771 case ARM::t2STMDB_UPD:
772 NeedDisjointWriteback =
true;
782 for (
unsigned i = 0; i < 16; ++i) {
783 if (Val & (1 << i)) {
792 if (NeedDisjointWriteback && WritebackReg == Inst.
end()[-1].getReg())
810 if (regs == 0 || (Vd + regs) > 32) {
811 regs = Vd + regs > 32 ? 32 - Vd : regs;
812 regs = std::max( 1u, regs);
818 for (
unsigned i = 0; i < (regs - 1); ++i) {
835 unsigned MaxReg =
PermitsD32(Inst, Decoder) ? 32 : 16;
836 if (regs == 0 || (Vd + regs) > MaxReg) {
837 regs = Vd + regs > MaxReg ? MaxReg - Vd : regs;
838 regs = std::max( 1u, regs);
839 regs = std::min(MaxReg, regs);
845 for (
unsigned i = 0; i < (regs - 1); ++i) {
874 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
875 uint32_t lsb_mask = (1U << lsb) - 1;
896 case ARM::LDC_OFFSET:
899 case ARM::LDC_OPTION:
900 case ARM::LDCL_OFFSET:
903 case ARM::LDCL_OPTION:
904 case ARM::STC_OFFSET:
907 case ARM::STC_OPTION:
908 case ARM::STCL_OFFSET:
911 case ARM::STCL_OPTION:
912 case ARM::t2LDC_OFFSET:
914 case ARM::t2LDC_POST:
915 case ARM::t2LDC_OPTION:
916 case ARM::t2LDCL_OFFSET:
917 case ARM::t2LDCL_PRE:
918 case ARM::t2LDCL_POST:
919 case ARM::t2LDCL_OPTION:
920 case ARM::t2STC_OFFSET:
922 case ARM::t2STC_POST:
923 case ARM::t2STC_OPTION:
924 case ARM::t2STCL_OFFSET:
925 case ARM::t2STCL_PRE:
926 case ARM::t2STCL_POST:
927 case ARM::t2STCL_OPTION:
928 case ARM::t2LDC2_OFFSET:
929 case ARM::t2LDC2L_OFFSET:
930 case ARM::t2LDC2_PRE:
931 case ARM::t2LDC2L_PRE:
932 case ARM::t2STC2_OFFSET:
933 case ARM::t2STC2L_OFFSET:
934 case ARM::t2STC2_PRE:
935 case ARM::t2STC2L_PRE:
936 case ARM::LDC2_OFFSET:
937 case ARM::LDC2L_OFFSET:
940 case ARM::STC2_OFFSET:
941 case ARM::STC2L_OFFSET:
944 case ARM::t2LDC2_OPTION:
945 case ARM::t2STC2_OPTION:
946 case ARM::t2LDC2_POST:
947 case ARM::t2LDC2L_POST:
948 case ARM::t2STC2_POST:
949 case ARM::t2STC2L_POST:
951 case ARM::LDC2L_POST:
953 case ARM::STC2L_POST:
954 if (coproc == 0xA || coproc == 0xB ||
955 (featureBits[ARM::HasV8_1MMainlineOps] &&
956 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
957 coproc == 0xE || coproc == 0xF)))
964 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
973 case ARM::t2LDC2_OFFSET:
974 case ARM::t2LDC2L_OFFSET:
975 case ARM::t2LDC2_PRE:
976 case ARM::t2LDC2L_PRE:
977 case ARM::t2STC2_OFFSET:
978 case ARM::t2STC2L_OFFSET:
979 case ARM::t2STC2_PRE:
980 case ARM::t2STC2L_PRE:
981 case ARM::LDC2_OFFSET:
982 case ARM::LDC2L_OFFSET:
985 case ARM::STC2_OFFSET:
986 case ARM::STC2L_OFFSET:
989 case ARM::t2LDC_OFFSET:
990 case ARM::t2LDCL_OFFSET:
992 case ARM::t2LDCL_PRE:
993 case ARM::t2STC_OFFSET:
994 case ARM::t2STCL_OFFSET:
996 case ARM::t2STCL_PRE:
997 case ARM::LDC_OFFSET:
998 case ARM::LDCL_OFFSET:
1001 case ARM::STC_OFFSET:
1002 case ARM::STCL_OFFSET:
1008 case ARM::t2LDC2_POST:
1009 case ARM::t2LDC2L_POST:
1010 case ARM::t2STC2_POST:
1011 case ARM::t2STC2L_POST:
1012 case ARM::LDC2_POST:
1013 case ARM::LDC2L_POST:
1014 case ARM::STC2_POST:
1015 case ARM::STC2L_POST:
1016 case ARM::t2LDC_POST:
1017 case ARM::t2LDCL_POST:
1018 case ARM::t2STC_POST:
1019 case ARM::t2STCL_POST:
1021 case ARM::LDCL_POST:
1023 case ARM::STCL_POST:
1034 case ARM::LDC_OFFSET:
1037 case ARM::LDC_OPTION:
1038 case ARM::LDCL_OFFSET:
1040 case ARM::LDCL_POST:
1041 case ARM::LDCL_OPTION:
1042 case ARM::STC_OFFSET:
1045 case ARM::STC_OPTION:
1046 case ARM::STCL_OFFSET:
1048 case ARM::STCL_POST:
1049 case ARM::STCL_OPTION:
1076 case ARM::STR_POST_IMM:
1077 case ARM::STR_POST_REG:
1078 case ARM::STRB_POST_IMM:
1079 case ARM::STRB_POST_REG:
1080 case ARM::STRT_POST_REG:
1081 case ARM::STRT_POST_IMM:
1082 case ARM::STRBT_POST_REG:
1083 case ARM::STRBT_POST_IMM:
1096 case ARM::LDR_POST_IMM:
1097 case ARM::LDR_POST_REG:
1098 case ARM::LDRB_POST_IMM:
1099 case ARM::LDRB_POST_REG:
1100 case ARM::LDRBT_POST_REG:
1101 case ARM::LDRBT_POST_IMM:
1102 case ARM::LDRT_POST_REG:
1103 case ARM::LDRT_POST_IMM:
1118 bool writeback = (
P == 0) || (W == 1);
1119 unsigned idx_mode = 0;
1122 else if (!
P && writeback)
1125 if (writeback && (Rn == 15 || Rn == Rt))
1237 unsigned Rt2 = Rt + 1;
1239 bool writeback = (W == 1) | (
P == 0);
1245 case ARM::STRD_POST:
1248 case ARM::LDRD_POST:
1257 case ARM::STRD_POST:
1258 if (
P == 0 && W == 1)
1261 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1263 if (type && Rm == 15)
1272 case ARM::STRH_POST:
1275 if (writeback && (Rn == 15 || Rn == Rt))
1277 if (!type && Rm == 15)
1282 case ARM::LDRD_POST:
1283 if (type && Rn == 15) {
1288 if (
P == 0 && W == 1)
1290 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1292 if (!type && writeback && Rn == 15)
1294 if (writeback && (Rn == Rt || Rn == Rt2))
1299 case ARM::LDRH_POST:
1300 if (type && Rn == 15) {
1307 if (!type && Rm == 15)
1309 if (!type && writeback && (Rn == 15 || Rn == Rt))
1313 case ARM::LDRSH_PRE:
1314 case ARM::LDRSH_POST:
1316 case ARM::LDRSB_PRE:
1317 case ARM::LDRSB_POST:
1318 if (type && Rn == 15) {
1323 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1325 if (!type && (Rt == 15 || Rm == 15))
1327 if (!type && writeback && (Rn == 15 || Rn == Rt))
1344 case ARM::STRD_POST:
1347 case ARM::STRH_POST:
1361 case ARM::STRD_POST:
1364 case ARM::LDRD_POST:
1377 case ARM::LDRD_POST:
1380 case ARM::LDRH_POST:
1382 case ARM::LDRSH_PRE:
1383 case ARM::LDRSH_POST:
1385 case ARM::LDRSB_PRE:
1386 case ARM::LDRSB_POST:
1456 }
else if (imod && !M) {
1461 }
else if (!imod && M) {
1515 case ARM::LDMDA_UPD:
1521 case ARM::LDMDB_UPD:
1527 case ARM::LDMIA_UPD:
1533 case ARM::LDMIB_UPD:
1539 case ARM::STMDA_UPD:
1545 case ARM::STMDB_UPD:
1551 case ARM::STMIA_UPD:
1557 case ARM::STMIB_UPD:
1609 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1637 }
else if (imod && !M) {
1642 }
else if (!imod && M) {
1663 unsigned Opcode = ARM::t2HINT;
1666 Opcode = ARM::t2PACBTI;
1667 }
else if (imm == 0x1D) {
1668 Opcode = ARM::t2PAC;
1669 }
else if (imm == 0x2D) {
1670 Opcode = ARM::t2AUT;
1671 }
else if (imm == 0x0F) {
1672 Opcode = ARM::t2BTI;
1676 if (Opcode == ARM::t2HINT) {
1775 if (!FeatureBits[ARM::HasV8_1aOps] ||
1776 !FeatureBits[ARM::HasV8Ops])
1828 if (!add) imm *= -1;
1829 if (imm == 0 && !add) imm = INT32_MIN;
1899 unsigned I1 = !(J1 ^ S);
1900 unsigned I2 = !(J2 ^ S);
1903 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
1906 true, 4, Inst, Decoder))
1924 true, 4, Inst, Decoder))
1930 true, 4, Inst, Decoder))
1974 case ARM::VLD1q16:
case ARM::VLD1q32:
case ARM::VLD1q64:
case ARM::VLD1q8:
1975 case ARM::VLD1q16wb_fixed:
case ARM::VLD1q16wb_register:
1976 case ARM::VLD1q32wb_fixed:
case ARM::VLD1q32wb_register:
1977 case ARM::VLD1q64wb_fixed:
case ARM::VLD1q64wb_register:
1978 case ARM::VLD1q8wb_fixed:
case ARM::VLD1q8wb_register:
1979 case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d8:
1980 case ARM::VLD2d16wb_fixed:
case ARM::VLD2d16wb_register:
1981 case ARM::VLD2d32wb_fixed:
case ARM::VLD2d32wb_register:
1982 case ARM::VLD2d8wb_fixed:
case ARM::VLD2d8wb_register:
1989 case ARM::VLD2b16wb_fixed:
1990 case ARM::VLD2b16wb_register:
1991 case ARM::VLD2b32wb_fixed:
1992 case ARM::VLD2b32wb_register:
1993 case ARM::VLD2b8wb_fixed:
1994 case ARM::VLD2b8wb_register:
2008 case ARM::VLD3d8_UPD:
2009 case ARM::VLD3d16_UPD:
2010 case ARM::VLD3d32_UPD:
2014 case ARM::VLD4d8_UPD:
2015 case ARM::VLD4d16_UPD:
2016 case ARM::VLD4d32_UPD:
2023 case ARM::VLD3q8_UPD:
2024 case ARM::VLD3q16_UPD:
2025 case ARM::VLD3q32_UPD:
2029 case ARM::VLD4q8_UPD:
2030 case ARM::VLD4q16_UPD:
2031 case ARM::VLD4q32_UPD:
2044 case ARM::VLD3d8_UPD:
2045 case ARM::VLD3d16_UPD:
2046 case ARM::VLD3d32_UPD:
2050 case ARM::VLD4d8_UPD:
2051 case ARM::VLD4d16_UPD:
2052 case ARM::VLD4d32_UPD:
2059 case ARM::VLD3q8_UPD:
2060 case ARM::VLD3q16_UPD:
2061 case ARM::VLD3q32_UPD:
2065 case ARM::VLD4q8_UPD:
2066 case ARM::VLD4q16_UPD:
2067 case ARM::VLD4q32_UPD:
2080 case ARM::VLD4d8_UPD:
2081 case ARM::VLD4d16_UPD:
2082 case ARM::VLD4d32_UPD:
2089 case ARM::VLD4q8_UPD:
2090 case ARM::VLD4q16_UPD:
2091 case ARM::VLD4q32_UPD:
2101 case ARM::VLD1d8wb_fixed:
2102 case ARM::VLD1d16wb_fixed:
2103 case ARM::VLD1d32wb_fixed:
2104 case ARM::VLD1d64wb_fixed:
2105 case ARM::VLD1d8wb_register:
2106 case ARM::VLD1d16wb_register:
2107 case ARM::VLD1d32wb_register:
2108 case ARM::VLD1d64wb_register:
2109 case ARM::VLD1q8wb_fixed:
2110 case ARM::VLD1q16wb_fixed:
2111 case ARM::VLD1q32wb_fixed:
2112 case ARM::VLD1q64wb_fixed:
2113 case ARM::VLD1q8wb_register:
2114 case ARM::VLD1q16wb_register:
2115 case ARM::VLD1q32wb_register:
2116 case ARM::VLD1q64wb_register:
2117 case ARM::VLD1d8Twb_fixed:
2118 case ARM::VLD1d8Twb_register:
2119 case ARM::VLD1d16Twb_fixed:
2120 case ARM::VLD1d16Twb_register:
2121 case ARM::VLD1d32Twb_fixed:
2122 case ARM::VLD1d32Twb_register:
2123 case ARM::VLD1d64Twb_fixed:
2124 case ARM::VLD1d64Twb_register:
2125 case ARM::VLD1d8Qwb_fixed:
2126 case ARM::VLD1d8Qwb_register:
2127 case ARM::VLD1d16Qwb_fixed:
2128 case ARM::VLD1d16Qwb_register:
2129 case ARM::VLD1d32Qwb_fixed:
2130 case ARM::VLD1d32Qwb_register:
2131 case ARM::VLD1d64Qwb_fixed:
2132 case ARM::VLD1d64Qwb_register:
2133 case ARM::VLD2d8wb_fixed:
2134 case ARM::VLD2d16wb_fixed:
2135 case ARM::VLD2d32wb_fixed:
2136 case ARM::VLD2q8wb_fixed:
2137 case ARM::VLD2q16wb_fixed:
2138 case ARM::VLD2q32wb_fixed:
2139 case ARM::VLD2d8wb_register:
2140 case ARM::VLD2d16wb_register:
2141 case ARM::VLD2d32wb_register:
2142 case ARM::VLD2q8wb_register:
2143 case ARM::VLD2q16wb_register:
2144 case ARM::VLD2q32wb_register:
2145 case ARM::VLD2b8wb_fixed:
2146 case ARM::VLD2b16wb_fixed:
2147 case ARM::VLD2b32wb_fixed:
2148 case ARM::VLD2b8wb_register:
2149 case ARM::VLD2b16wb_register:
2150 case ARM::VLD2b32wb_register:
2153 case ARM::VLD3d8_UPD:
2154 case ARM::VLD3d16_UPD:
2155 case ARM::VLD3d32_UPD:
2156 case ARM::VLD3q8_UPD:
2157 case ARM::VLD3q16_UPD:
2158 case ARM::VLD3q32_UPD:
2159 case ARM::VLD4d8_UPD:
2160 case ARM::VLD4d16_UPD:
2161 case ARM::VLD4d32_UPD:
2162 case ARM::VLD4q8_UPD:
2163 case ARM::VLD4q16_UPD:
2164 case ARM::VLD4q32_UPD:
2191 case ARM::VLD1d8wb_fixed:
2192 case ARM::VLD1d16wb_fixed:
2193 case ARM::VLD1d32wb_fixed:
2194 case ARM::VLD1d64wb_fixed:
2195 case ARM::VLD1d8Twb_fixed:
2196 case ARM::VLD1d16Twb_fixed:
2197 case ARM::VLD1d32Twb_fixed:
2198 case ARM::VLD1d64Twb_fixed:
2199 case ARM::VLD1d8Qwb_fixed:
2200 case ARM::VLD1d16Qwb_fixed:
2201 case ARM::VLD1d32Qwb_fixed:
2202 case ARM::VLD1d64Qwb_fixed:
2203 case ARM::VLD1d8wb_register:
2204 case ARM::VLD1d16wb_register:
2205 case ARM::VLD1d32wb_register:
2206 case ARM::VLD1d64wb_register:
2207 case ARM::VLD1q8wb_fixed:
2208 case ARM::VLD1q16wb_fixed:
2209 case ARM::VLD1q32wb_fixed:
2210 case ARM::VLD1q64wb_fixed:
2211 case ARM::VLD1q8wb_register:
2212 case ARM::VLD1q16wb_register:
2213 case ARM::VLD1q32wb_register:
2214 case ARM::VLD1q64wb_register:
2218 if (Rm != 0xD && Rm != 0xF &&
2222 case ARM::VLD2d8wb_fixed:
2223 case ARM::VLD2d16wb_fixed:
2224 case ARM::VLD2d32wb_fixed:
2225 case ARM::VLD2b8wb_fixed:
2226 case ARM::VLD2b16wb_fixed:
2227 case ARM::VLD2b32wb_fixed:
2228 case ARM::VLD2q8wb_fixed:
2229 case ARM::VLD2q16wb_fixed:
2230 case ARM::VLD2q32wb_fixed:
2251 case ARM::VST1d8wb_fixed:
2252 case ARM::VST1d16wb_fixed:
2253 case ARM::VST1d32wb_fixed:
2254 case ARM::VST1d64wb_fixed:
2255 case ARM::VST1d8wb_register:
2256 case ARM::VST1d16wb_register:
2257 case ARM::VST1d32wb_register:
2258 case ARM::VST1d64wb_register:
2259 case ARM::VST1q8wb_fixed:
2260 case ARM::VST1q16wb_fixed:
2261 case ARM::VST1q32wb_fixed:
2262 case ARM::VST1q64wb_fixed:
2263 case ARM::VST1q8wb_register:
2264 case ARM::VST1q16wb_register:
2265 case ARM::VST1q32wb_register:
2266 case ARM::VST1q64wb_register:
2267 case ARM::VST1d8Twb_fixed:
2268 case ARM::VST1d16Twb_fixed:
2269 case ARM::VST1d32Twb_fixed:
2270 case ARM::VST1d64Twb_fixed:
2271 case ARM::VST1d8Twb_register:
2272 case ARM::VST1d16Twb_register:
2273 case ARM::VST1d32Twb_register:
2274 case ARM::VST1d64Twb_register:
2275 case ARM::VST1d8Qwb_fixed:
2276 case ARM::VST1d16Qwb_fixed:
2277 case ARM::VST1d32Qwb_fixed:
2278 case ARM::VST1d64Qwb_fixed:
2279 case ARM::VST1d8Qwb_register:
2280 case ARM::VST1d16Qwb_register:
2281 case ARM::VST1d32Qwb_register:
2282 case ARM::VST1d64Qwb_register:
2283 case ARM::VST2d8wb_fixed:
2284 case ARM::VST2d16wb_fixed:
2285 case ARM::VST2d32wb_fixed:
2286 case ARM::VST2d8wb_register:
2287 case ARM::VST2d16wb_register:
2288 case ARM::VST2d32wb_register:
2289 case ARM::VST2q8wb_fixed:
2290 case ARM::VST2q16wb_fixed:
2291 case ARM::VST2q32wb_fixed:
2292 case ARM::VST2q8wb_register:
2293 case ARM::VST2q16wb_register:
2294 case ARM::VST2q32wb_register:
2295 case ARM::VST2b8wb_fixed:
2296 case ARM::VST2b16wb_fixed:
2297 case ARM::VST2b32wb_fixed:
2298 case ARM::VST2b8wb_register:
2299 case ARM::VST2b16wb_register:
2300 case ARM::VST2b32wb_register:
2305 case ARM::VST3d8_UPD:
2306 case ARM::VST3d16_UPD:
2307 case ARM::VST3d32_UPD:
2308 case ARM::VST3q8_UPD:
2309 case ARM::VST3q16_UPD:
2310 case ARM::VST3q32_UPD:
2311 case ARM::VST4d8_UPD:
2312 case ARM::VST4d16_UPD:
2313 case ARM::VST4d32_UPD:
2314 case ARM::VST4q8_UPD:
2315 case ARM::VST4q16_UPD:
2316 case ARM::VST4q32_UPD:
2333 else if (Rm != 0xF) {
2338 case ARM::VST1d8wb_fixed:
2339 case ARM::VST1d16wb_fixed:
2340 case ARM::VST1d32wb_fixed:
2341 case ARM::VST1d64wb_fixed:
2342 case ARM::VST1q8wb_fixed:
2343 case ARM::VST1q16wb_fixed:
2344 case ARM::VST1q32wb_fixed:
2345 case ARM::VST1q64wb_fixed:
2346 case ARM::VST1d8Twb_fixed:
2347 case ARM::VST1d16Twb_fixed:
2348 case ARM::VST1d32Twb_fixed:
2349 case ARM::VST1d64Twb_fixed:
2350 case ARM::VST1d8Qwb_fixed:
2351 case ARM::VST1d16Qwb_fixed:
2352 case ARM::VST1d32Qwb_fixed:
2353 case ARM::VST1d64Qwb_fixed:
2354 case ARM::VST2d8wb_fixed:
2355 case ARM::VST2d16wb_fixed:
2356 case ARM::VST2d32wb_fixed:
2357 case ARM::VST2q8wb_fixed:
2358 case ARM::VST2q16wb_fixed:
2359 case ARM::VST2q32wb_fixed:
2360 case ARM::VST2b8wb_fixed:
2361 case ARM::VST2b16wb_fixed:
2362 case ARM::VST2b32wb_fixed:
2372 case ARM::VST1q16wb_fixed:
2373 case ARM::VST1q16wb_register:
2374 case ARM::VST1q32wb_fixed:
2375 case ARM::VST1q32wb_register:
2376 case ARM::VST1q64wb_fixed:
2377 case ARM::VST1q64wb_register:
2378 case ARM::VST1q8wb_fixed:
2379 case ARM::VST1q8wb_register:
2383 case ARM::VST2d16wb_fixed:
2384 case ARM::VST2d16wb_register:
2385 case ARM::VST2d32wb_fixed:
2386 case ARM::VST2d32wb_register:
2387 case ARM::VST2d8wb_fixed:
2388 case ARM::VST2d8wb_register:
2395 case ARM::VST2b16wb_fixed:
2396 case ARM::VST2b16wb_register:
2397 case ARM::VST2b32wb_fixed:
2398 case ARM::VST2b32wb_register:
2399 case ARM::VST2b8wb_fixed:
2400 case ARM::VST2b8wb_register:
2414 case ARM::VST3d8_UPD:
2415 case ARM::VST3d16_UPD:
2416 case ARM::VST3d32_UPD:
2420 case ARM::VST4d8_UPD:
2421 case ARM::VST4d16_UPD:
2422 case ARM::VST4d32_UPD:
2429 case ARM::VST3q8_UPD:
2430 case ARM::VST3q16_UPD:
2431 case ARM::VST3q32_UPD:
2435 case ARM::VST4q8_UPD:
2436 case ARM::VST4q16_UPD:
2437 case ARM::VST4q32_UPD:
2450 case ARM::VST3d8_UPD:
2451 case ARM::VST3d16_UPD:
2452 case ARM::VST3d32_UPD:
2456 case ARM::VST4d8_UPD:
2457 case ARM::VST4d16_UPD:
2458 case ARM::VST4d32_UPD:
2465 case ARM::VST3q8_UPD:
2466 case ARM::VST3q16_UPD:
2467 case ARM::VST3q32_UPD:
2471 case ARM::VST4q8_UPD:
2472 case ARM::VST4q16_UPD:
2473 case ARM::VST4q32_UPD:
2486 case ARM::VST4d8_UPD:
2487 case ARM::VST4d16_UPD:
2488 case ARM::VST4d32_UPD:
2495 case ARM::VST4q8_UPD:
2496 case ARM::VST4q16_UPD:
2497 case ARM::VST4q32_UPD:
2575 if (
size == 0 && align == 1)
2577 align *= (1 <<
size);
2580 case ARM::VLD1DUPq16:
case ARM::VLD1DUPq32:
case ARM::VLD1DUPq8:
2581 case ARM::VLD1DUPq16wb_fixed:
case ARM::VLD1DUPq16wb_register:
2582 case ARM::VLD1DUPq32wb_fixed:
case ARM::VLD1DUPq32wb_register:
2583 case ARM::VLD1DUPq8wb_fixed:
case ARM::VLD1DUPq8wb_register:
2604 if (Rm != 0xD && Rm != 0xF &&
2625 case ARM::VLD2DUPd16:
case ARM::VLD2DUPd32:
case ARM::VLD2DUPd8:
2626 case ARM::VLD2DUPd16wb_fixed:
case ARM::VLD2DUPd16wb_register:
2627 case ARM::VLD2DUPd32wb_fixed:
case ARM::VLD2DUPd32wb_register:
2628 case ARM::VLD2DUPd8wb_fixed:
case ARM::VLD2DUPd8wb_register:
2632 case ARM::VLD2DUPd16x2:
case ARM::VLD2DUPd32x2:
case ARM::VLD2DUPd8x2:
2633 case ARM::VLD2DUPd16x2wb_fixed:
case ARM::VLD2DUPd16x2wb_register:
2634 case ARM::VLD2DUPd32x2wb_fixed:
case ARM::VLD2DUPd32x2wb_register:
2635 case ARM::VLD2DUPd8x2wb_fixed:
case ARM::VLD2DUPd8x2wb_register:
2652 if (Rm != 0xD && Rm != 0xF) {
2688 else if (Rm != 0xF) {
2741 else if (Rm != 0xF) {
2774 case ARM::VORRiv4i16:
2775 case ARM::VORRiv2i32:
2776 case ARM::VBICiv4i16:
2777 case ARM::VBICiv2i32:
2781 case ARM::VORRiv8i16:
2782 case ARM::VORRiv4i32:
2783 case ARM::VBICiv8i16:
2784 case ARM::VBICiv4i32:
2809 if (cmode == 0xF && Inst.
getOpcode() == ARM::MVE_VMVNimmi32)
2961 true, 2, Inst, Decoder))
2970 true, 4, Inst, Decoder))
2979 true, 2, Inst, Decoder))
3018 unsigned imm = Val << 2;
3077 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3081 case ARM::t2LDRBpci:
3082 case ARM::t2LDRHpci:
3085 case ARM::t2LDRSBpci:
3088 case ARM::t2LDRSHpci:
3130 bool hasMP = featureBits[ARM::FeatureMP];
3131 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3186 if (!hasV7Ops || !hasMP)
3205 int imm = Val & 0xFF;
3208 else if (!(Val & 0x100))
3278 bool hasMP = featureBits[ARM::FeatureMP];
3279 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3289 case ARM::t2LDRSBi8:
3295 case ARM::t2LDRSHi8:
3312 case ARM::t2LDRSHi8:
3318 case ARM::t2LDRSBi8:
3334 if (!hasV7Ops || !hasMP)
3358 case ARM::t2STRBi12:
3359 case ARM::t2STRHi12:
3387 bool hasMP = featureBits[ARM::FeatureMP];
3388 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3395 case ARM::t2LDRHi12:
3398 case ARM::t2LDRSHi12:
3401 case ARM::t2LDRBi12:
3404 case ARM::t2LDRSBi12:
3421 case ARM::t2LDRSHi12:
3423 case ARM::t2LDRHi12:
3426 case ARM::t2LDRSBi12:
3441 case ARM::t2PLDWi12:
3442 if (!hasV7Ops || !hasMP)
3499 int imm = Val & 0xFF;
3501 if (!(Val & 0x100)) imm *= -1;
3513 int imm = Val & 0x7F;
3574 int imm = Val & 0x7F;
3577 else if (!(Val & 0x80))
3579 if (imm != INT32_MIN)
3580 imm *= (1U << shift);
3603template <
int shift,
int WriteBack>
3636 case ARM::t2LDR_PRE:
3637 case ARM::t2LDR_POST:
3640 case ARM::t2LDRB_PRE:
3641 case ARM::t2LDRB_POST:
3644 case ARM::t2LDRH_PRE:
3645 case ARM::t2LDRH_POST:
3648 case ARM::t2LDRSB_PRE:
3649 case ARM::t2LDRSB_POST:
3655 case ARM::t2LDRSH_PRE:
3656 case ARM::t2LDRSH_POST:
3710 }
else if (Inst.
getOpcode() == ARM::tADDspr) {
3780 if (imm != INT32_MIN)
3781 imm *= (1U << shift);
3797 unsigned S = (Val >> 23) & 1;
3798 unsigned J1 = (Val >> 22) & 1;
3799 unsigned J2 = (Val >> 21) & 1;
3800 unsigned I1 = !(J1 ^ S);
3801 unsigned I2 = !(J2 ^ S);
3802 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3806 (Address & ~2u) + imm32 + 4,
3807 true, 4, Inst, Decoder))
3815 if (Val == 0xA || Val == 0xB)
3862 if (pred == 0xE || pred == 0xF) {
3934 true, 2, Inst, Decoder))
3949 unsigned S = (Val >> 23) & 1;
3950 unsigned J1 = (Val >> 22) & 1;
3951 unsigned J2 = (Val >> 21) & 1;
3952 unsigned I1 = !(J1 ^ S);
3953 unsigned I2 = !(J2 ^ S);
3954 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3958 true, 4, Inst, Decoder))
3979 if (FeatureBits[ARM::FeatureMClass]) {
3980 unsigned ValLow = Val & 0xff;
3999 if (!(FeatureBits[ARM::HasV7Ops]))
4007 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4017 if (!(FeatureBits[ARM::Feature8MSecExt]))
4036 if (!(FeatureBits[ARM::FeaturePACBTI]))
4047 if (!(FeatureBits[ARM::HasV7Ops])) {
4060 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4061 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4083 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4125 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4801 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4827 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4863 unsigned LowBit = mask & -mask;
4864 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
4865 mask ^= BitsAboveLowBit;
4885 bool writeback = (W == 1) | (
P == 0);
4887 addr |= (U << 8) | (Rn << 9);
4889 if (writeback && (Rn == Rt || Rn == Rt2))
4922 bool writeback = (W == 1) | (
P == 0);
4924 addr |= (U << 8) | (Rn << 9);
4926 if (writeback && (Rn == Rt || Rn == Rt2))
4994 if (Rt == Rn || Rn == Rt2)
5013 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5026 if (!(imm & 0x38)) {
5072 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5085 if (!(imm & 0x38)) {
5144 if (!
Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5146 if (!
Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5148 if (!
Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
5198 if ((cop & ~0x1) == 0xa)
5243 case ARM::VMSR_FPSCR_NZCVQC:
5254 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5255 if (Rt == 13 || Rt == 15)
5264 case ARM::VMRS_FPSCR_NZCVQC:
5272 if (featureBits[ARM::ModeThumb]) {
5284template <
bool isSigned,
bool isNeg,
bool zeroPermitted,
int size>
5289 if (Val == 0 && !zeroPermitted)
5296 DecVal = (Val << 1);
5309 Val = LocImm + (2 << Val);
5335 case ARM::t2LEUpdate:
5342 Inst, Imm, Address, Decoder)))
5346 case ARM::MVE_WLSTP_8:
5347 case ARM::MVE_WLSTP_16:
5348 case ARM::MVE_WLSTP_32:
5349 case ARM::MVE_WLSTP_64:
5353 Address, Decoder)) ||
5355 Inst, Imm, Address, Decoder)))
5359 case ARM::MVE_DLSTP_8:
5360 case ARM::MVE_DLSTP_16:
5361 case ARM::MVE_DLSTP_32:
5362 case ARM::MVE_DLSTP_64:
5368 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
5369 if ((Insn & ~SBZMask) != CanonicalLCTP)
5371 if (Insn != CanonicalLCTP)
5403 if ((RegNo) + 1 > 11)
5449 }
else if (Inst.
getOpcode() == ARM::VSCCLRMD) {
5460 unsigned max_reg = Vd + regs;
5461 if (max_reg > 64 || (max_reg > 32 && (max_reg & 1)))
5463 unsigned max_sreg = std::min(32u, max_reg);
5464 unsigned max_dreg = std::min(32u, max_reg / 2);
5465 for (
unsigned i = Vd; i < max_sreg; ++i)
5468 for (
unsigned i = 16; i < max_dreg; ++i)
5487 unsigned CurBit = 0;
5488 for (
int i = 3; i >= 0; --i) {
5491 CurBit ^= (Val >> i) & 1U;
5494 Imm |= (CurBit << i);
5497 if ((Val & ~(~0U << i)) == 0) {
5519 switch (Val & 0x3) {
5580 unsigned DecodedVal = 64 - Val;
5583 case ARM::MVE_VCVTf16s16_fix:
5584 case ARM::MVE_VCVTs16f16_fix:
5585 case ARM::MVE_VCVTf16u16_fix:
5586 case ARM::MVE_VCVTu16f16_fix:
5587 if (DecodedVal > 16)
5590 case ARM::MVE_VCVTf32s32_fix:
5591 case ARM::MVE_VCVTs32f32_fix:
5592 case ARM::MVE_VCVTf32u32_fix:
5593 case ARM::MVE_VCVTu32f32_fix:
5594 if (DecodedVal > 32)
5606 case ARM::VSTR_P0_off:
5607 case ARM::VSTR_P0_pre:
5608 case ARM::VSTR_P0_post:
5609 case ARM::VLDR_P0_off:
5610 case ARM::VLDR_P0_pre:
5611 case ARM::VLDR_P0_post:
5613 case ARM::VSTR_FPSCR_NZCVQC_off:
5614 case ARM::VSTR_FPSCR_NZCVQC_pre:
5615 case ARM::VSTR_FPSCR_NZCVQC_post:
5616 case ARM::VLDR_FPSCR_NZCVQC_off:
5617 case ARM::VLDR_FPSCR_NZCVQC_pre:
5618 case ARM::VLDR_FPSCR_NZCVQC_post:
5625template <
bool Writeback>
5630 case ARM::VSTR_FPSCR_pre:
5631 case ARM::VSTR_FPSCR_NZCVQC_pre:
5632 case ARM::VLDR_FPSCR_pre:
5633 case ARM::VLDR_FPSCR_NZCVQC_pre:
5634 case ARM::VSTR_FPSCR_off:
5635 case ARM::VSTR_FPSCR_NZCVQC_off:
5636 case ARM::VLDR_FPSCR_off:
5637 case ARM::VLDR_FPSCR_NZCVQC_off:
5638 case ARM::VSTR_FPSCR_post:
5639 case ARM::VSTR_FPSCR_NZCVQC_post:
5640 case ARM::VLDR_FPSCR_post:
5641 case ARM::VLDR_FPSCR_NZCVQC_post:
5645 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
5679 if (!
Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
5683 if (!
Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
5720template <
unsigned MinLog,
unsigned MaxLog>
5726 if (Val < MinLog || Val > MaxLog)
5733template <
unsigned start>
5812 case ARM::MVE_ASRLr:
5813 case ARM::MVE_SQRSHRL:
5816 case ARM::MVE_LSLLr:
5817 case ARM::MVE_UQRSHLL:
5864 if (Inst.
getOpcode() == ARM::MVE_SQRSHRL ||
5894template <
bool scalar, OperandDecoder predicate_decoder>
5922 if (!
Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
5972 Inst.
setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
5975 Inst.
setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
6005#include "ARMGenDisassemblerTables.inc"
6012 switch (
MI.getOpcode()) {
6024 case ARM::t2ADDri12:
6028 case ARM::t2SUBri12:
6031 if (
MI.getOperand(0).getReg() == ARM::SP &&
6032 MI.getOperand(1).getReg() != ARM::SP)
6035 default:
return Result;
6044 if (!STI.hasFeature(ARM::ModeThumb))
6059 if (Bytes.
size() < 2)
6063 Bytes.
data(), InstructionEndianness);
6064 return Insn16 < 0xE800 ? 2 : 4;
6068 ArrayRef<uint8_t> Bytes,
6070 raw_ostream &CS)
const {
6072 if (STI.hasFeature(ARM::ModeThumb))
6076 if (S == DecodeStatus::Fail)
6080 const MCInstrDesc &MCID = MCII->get(
MI.getOpcode());
6084 Twine(
MI.getNumOperands()) +
"\n");
6091 ArrayRef<uint8_t> Bytes,
6093 raw_ostream &CS)
const {
6094 CommentStream = &CS;
6096 assert(!STI.hasFeature(ARM::ModeThumb) &&
6097 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
6101 if (Bytes.
size() < 4) {
6108 InstructionEndianness);
6112 decodeInstruction(DecoderTableARM32,
MI, Insn,
Address,
this, STI);
6118 struct DecodeTable {
6123 const DecodeTable Tables[] = {
6124 {DecoderTableVFP32,
false}, {DecoderTableVFPV832,
false},
6125 {DecoderTableNEONData32,
true}, {DecoderTableNEONLoadStore32,
true},
6126 {DecoderTableNEONDup32,
false}, {DecoderTablev8NEON32,
false},
6127 {DecoderTablev8Crypto32,
false},
6130 for (
auto Table : Tables) {
6136 if (Table.DecodePred && MCII->get(
MI.getOpcode()).isPredicable()) {
6145 decodeInstruction(DecoderTableCoProc32,
MI, Insn,
Address,
this, STI);
6155bool ARMDisassembler::isVectorPredicable(
const MCInst &
MI)
const {
6156 const MCInstrDesc &MCID = MCII->get(
MI.getOpcode());
6169ARMDisassembler::AddThumbPredicate(MCInst &
MI)
const {
6172 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
6176 switch (
MI.getOpcode()) {
6193 if (ITBlock.instrInITBlock())
6199 if (
MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
6208 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
6224 if (ITBlock.instrInITBlock()) {
6225 CC = ITBlock.getITCC();
6226 ITBlock.advanceITState();
6227 }
else if (VPTBlock.instrInVPTBlock()) {
6228 VPTBlock.advanceVPTState();
6231 const MCInstrDesc &MCID = MCII->get(
MI.getOpcode());
6234 for (
unsigned i = 0; i < MCID.
NumOperands; ++i, ++CCI) {
6235 if (MCID.
operands()[i].isPredicate() || CCI ==
MI.end())
6258void ARMDisassembler::UpdateThumbPredicate(
DecodeStatus &S, MCInst &
MI)
const {
6260 CC = ITBlock.getITCC();
6263 if (ITBlock.instrInITBlock())
6264 ITBlock.advanceITState();
6265 else if (VPTBlock.instrInVPTBlock()) {
6266 CC = VPTBlock.getVPTPred();
6267 VPTBlock.advanceVPTState();
6270 const MCInstrDesc &MCID = MCII->get(
MI.getOpcode());
6274 for (
unsigned i = 0; i <
NumOps; ++i, ++
I) {
6275 if (OpInfo[i].isPredicate() ) {
6281 I->setReg(ARM::NoRegister);
6283 I->setReg(ARM::CPSR);
6290 ArrayRef<uint8_t> Bytes,
6292 raw_ostream &CS)
const {
6293 CommentStream = &CS;
6295 assert(STI.hasFeature(ARM::ModeThumb) &&
6296 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
6299 if (Bytes.
size() < 2) {
6305 Bytes.
data(), InstructionEndianness);
6307 decodeInstruction(DecoderTableThumb16,
MI, Insn16,
Address,
this, STI);
6310 Check(Result, AddThumbPredicate(
MI));
6314 Result = decodeInstruction(DecoderTableThumbSBit16,
MI, Insn16,
Address,
this,
6318 Check(Result, AddThumbPredicate(
MI));
6323 decodeInstruction(DecoderTableThumb216,
MI, Insn16,
Address,
this, STI);
6329 if (
MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
6332 Check(Result, AddThumbPredicate(
MI));
6337 if (
MI.getOpcode() == ARM::t2IT) {
6338 unsigned Firstcond =
MI.getOperand(0).getImm();
6339 unsigned Mask =
MI.getOperand(1).getImm();
6340 ITBlock.setITState(Firstcond, Mask);
6344 CS <<
"unpredictable IT predicate sequence";
6351 if (Bytes.
size() < 4) {
6358 Bytes.
data() + 2, InstructionEndianness);
6361 decodeInstruction(DecoderTableMVE32,
MI, Insn32,
Address,
this, STI);
6367 if (
isVPTOpcode(
MI.getOpcode()) && VPTBlock.instrInVPTBlock())
6370 Check(Result, AddThumbPredicate(
MI));
6373 unsigned Mask =
MI.getOperand(0).getImm();
6374 VPTBlock.setVPTState(Mask);
6381 decodeInstruction(DecoderTableThumb32,
MI, Insn32,
Address,
this, STI);
6384 Check(Result, AddThumbPredicate(
MI));
6389 decodeInstruction(DecoderTableThumb232,
MI, Insn32,
Address,
this, STI);
6392 Check(Result, AddThumbPredicate(
MI));
6398 decodeInstruction(DecoderTableVFP32,
MI, Insn32,
Address,
this, STI);
6401 UpdateThumbPredicate(Result,
MI);
6407 decodeInstruction(DecoderTableVFPV832,
MI, Insn32,
Address,
this, STI);
6414 Result = decodeInstruction(DecoderTableNEONDup32,
MI, Insn32,
Address,
this,
6418 UpdateThumbPredicate(Result,
MI);
6424 uint32_t NEONLdStInsn = Insn32;
6425 NEONLdStInsn &= 0xF0FFFFFF;
6426 NEONLdStInsn |= 0x04000000;
6427 Result = decodeInstruction(DecoderTableNEONLoadStore32,
MI, NEONLdStInsn,
6431 Check(Result, AddThumbPredicate(
MI));
6437 uint32_t NEONDataInsn = Insn32;
6438 NEONDataInsn &= 0xF0FFFFFF;
6439 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4;
6440 NEONDataInsn |= 0x12000000;
6441 Result = decodeInstruction(DecoderTableNEONData32,
MI, NEONDataInsn,
6445 Check(Result, AddThumbPredicate(
MI));
6449 uint32_t NEONCryptoInsn = Insn32;
6450 NEONCryptoInsn &= 0xF0FFFFFF;
6451 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4;
6452 NEONCryptoInsn |= 0x12000000;
6453 Result = decodeInstruction(DecoderTablev8Crypto32,
MI, NEONCryptoInsn,
6460 uint32_t NEONv8Insn = Insn32;
6461 NEONv8Insn &= 0xF3FFFFFF;
6462 Result = decodeInstruction(DecoderTablev8NEON32,
MI, NEONv8Insn,
Address,
6472 ? DecoderTableThumb2CDE32
6473 : DecoderTableThumb2CoProc32;
6475 decodeInstruction(DecoderTable,
MI, Insn32,
Address,
this, STI);
6478 Check(Result, AddThumbPredicate(
MI));
6484 if (ITBlock.instrInITBlock())
6485 ITBlock.advanceITState();
6493 return new ARMDisassembler(STI, Ctx,
T.createMCInstrInfo());
MCDisassembler::DecodeStatus DecodeStatus
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
AMDGPU Mark last scratch load
static bool isVectorPredicable(const MCInstrDesc &MCID)
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t GPRPairDecoderTable[]
static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg QQPRDecoderTable[]
static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, const MCDisassembler *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler()
static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg DPairDecoderTable[]
static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg DPairSpacedDecoderTable[]
static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVpredNOperand(MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createARMDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode)
static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg QPRDecoderTable[]
static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg SPRDecoderTable[]
static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t CLRMGPRDecoderTable[]
static const MCPhysReg DPRDecoderTable[]
static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const MCDisassembler *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t GPRDecoderTable[]
static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVpredROperand(MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg QQQQPRDecoderTable[]
static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder, unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder)
static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, uint64_t Address, raw_ostream &CS, uint32_t Insn, DecodeStatus Result)
static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_EXTERNAL_VISIBILITY
static bool isNeg(Value *V)
Returns true if the operation is a negation of V, and it works for both integers and floats.
static bool isSigned(unsigned int Opcode)
amode Optimize addressing mode
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
static bool isBranch(unsigned Opcode)
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Container class for subtarget features.
Context object for machine code objects.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
const MCSubtargetInfo & getSubtargetInfo() const
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
SmallVectorImpl< MCOperand >::iterator iterator
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned short NumOperands
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(MCRegister Reg)
static MCOperand createImm(int64_t Val)
MCRegister getReg() const
Returns the register number.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
Wrapper class representing virtual and physical registers.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Target - Wrapper for Target specific information.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
getAM5Opc - This function encodes the addrmode5 opc field.
unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset)
getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
bool isVpred(OperandType op)
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
@ D16
Only 16 D registers.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)
value_type read(const void *memory, endianness endian)
Read a value of a particular endianness from memory.
This is an optimization pass for GlobalISel generic memory operations.
constexpr T rotr(T V, int R)
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Target & getTheThumbBETarget()
static bool isVPTOpcode(int Opc)
LLVM_ABI void reportFatalInternalError(Error Err)
Report a fatal error that indicates a bug in LLVM.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
Target & getTheARMLETarget()
Target & getTheARMBETarget()
Target & getTheThumbLETarget()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.