LLVM 20.0.0git
X86MCCodeEmitter.cpp
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1//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the X86MCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCFixup.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCSymbol.h"
29#include <cassert>
30#include <cstdint>
31#include <cstdlib>
32
33using namespace llvm;
34
35#define DEBUG_TYPE "mccodeemitter"
36
37namespace {
38
39enum PrefixKind { None, REX, REX2, XOP, VEX2, VEX3, EVEX };
40
41static void emitByte(uint8_t C, SmallVectorImpl<char> &CB) { CB.push_back(C); }
42
43class X86OpcodePrefixHelper {
44 // REX (1 byte)
45 // +-----+ +------+
46 // | 40H | | WRXB |
47 // +-----+ +------+
48
49 // REX2 (2 bytes)
50 // +-----+ +-------------------+
51 // | D5H | | M | R'X'B' | WRXB |
52 // +-----+ +-------------------+
53
54 // XOP (3-byte)
55 // +-----+ +--------------+ +-------------------+
56 // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
57 // +-----+ +--------------+ +-------------------+
58
59 // VEX2 (2 bytes)
60 // +-----+ +-------------------+
61 // | C5h | | R | vvvv | L | pp |
62 // +-----+ +-------------------+
63
64 // VEX3 (3 bytes)
65 // +-----+ +--------------+ +-------------------+
66 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
67 // +-----+ +--------------+ +-------------------+
68
69 // VEX_R: opcode externsion equivalent to REX.R in
70 // 1's complement (inverted) form
71 //
72 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
73 // 0: Same as REX_R=1 (64 bit mode only)
74
75 // VEX_X: equivalent to REX.X, only used when a
76 // register is used for index in SIB Byte.
77 //
78 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
79 // 0: Same as REX.X=1 (64-bit mode only)
80
81 // VEX_B:
82 // 1: Same as REX_B=0 (ignored in 32-bit mode)
83 // 0: Same as REX_B=1 (64 bit mode only)
84
85 // VEX_W: opcode specific (use like REX.W, or used for
86 // opcode extension, or ignored, depending on the opcode byte)
87
88 // VEX_5M (VEX m-mmmmm field):
89 //
90 // 0b00000: Reserved for future use
91 // 0b00001: implied 0F leading opcode
92 // 0b00010: implied 0F 38 leading opcode bytes
93 // 0b00011: implied 0F 3A leading opcode bytes
94 // 0b00100: Reserved for future use
95 // 0b00101: VEX MAP5
96 // 0b00110: VEX MAP6
97 // 0b00111: VEX MAP7
98 // 0b00111-0b11111: Reserved for future use
99 // 0b01000: XOP map select - 08h instructions with imm byte
100 // 0b01001: XOP map select - 09h instructions with no imm byte
101 // 0b01010: XOP map select - 0Ah instructions with imm dword
102
103 // VEX_4V (VEX vvvv field): a register specifier
104 // (in 1's complement form) or 1111 if unused.
105
106 // VEX_PP: opcode extension providing equivalent
107 // functionality of a SIMD prefix
108 // 0b00: None
109 // 0b01: 66
110 // 0b10: F3
111 // 0b11: F2
112
113 // EVEX (4 bytes)
114 // +-----+ +---------------+ +-------------------+ +------------------------+
115 // | 62h | | RXBR' | B'mmm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
116 // +-----+ +---------------+ +-------------------+ +------------------------+
117
118 // EVEX_L2/VEX_L (Vector Length):
119 // L2 L
120 // 0 0: scalar or 128-bit vector
121 // 0 1: 256-bit vector
122 // 1 0: 512-bit vector
123
124 // 32-Register Support in 64-bit Mode Using EVEX with Embedded REX/REX2 Bits:
125 //
126 // +----------+---------+--------+-----------+---------+--------------+
127 // | | 4 | 3 | [2:0] | Type | Common Usage |
128 // +----------+---------+--------+-----------+---------+--------------+
129 // | REG | EVEX_R' | EVEX_R | modrm.reg | GPR, VR | Dest or Src |
130 // | VVVV | EVEX_v' | EVEX.vvvv | GPR, VR | Dest or Src |
131 // | RM (VR) | EVEX_X | EVEX_B | modrm.r/m | VR | Dest or Src |
132 // | RM (GPR) | EVEX_B' | EVEX_B | modrm.r/m | GPR | Dest or Src |
133 // | BASE | EVEX_B' | EVEX_B | modrm.r/m | GPR | MA |
134 // | INDEX | EVEX_U | EVEX_X | sib.index | GPR | MA |
135 // | VIDX | EVEX_v' | EVEX_X | sib.index | VR | VSIB MA |
136 // +----------+---------+--------+-----------+---------+--------------+
137 //
138 // * GPR - General-purpose register
139 // * VR - Vector register
140 // * VIDX - Vector index
141 // * VSIB - Vector SIB
142 // * MA - Memory addressing
143
144private:
145 unsigned W : 1;
146 unsigned R : 1;
147 unsigned X : 1;
148 unsigned B : 1;
149 unsigned M : 1;
150 unsigned R2 : 1;
151 unsigned X2 : 1;
152 unsigned B2 : 1;
153 unsigned VEX_4V : 4;
154 unsigned VEX_L : 1;
155 unsigned VEX_PP : 2;
156 unsigned VEX_5M : 5;
157 unsigned EVEX_z : 1;
158 unsigned EVEX_L2 : 1;
159 unsigned EVEX_b : 1;
160 unsigned EVEX_V2 : 1;
161 unsigned EVEX_aaa : 3;
162 PrefixKind Kind = None;
163 const MCRegisterInfo &MRI;
164
165 unsigned getRegEncoding(const MCInst &MI, unsigned OpNum) const {
166 return MRI.getEncodingValue(MI.getOperand(OpNum).getReg());
167 }
168
169 void setR(unsigned Encoding) { R = Encoding >> 3 & 1; }
170 void setR2(unsigned Encoding) {
171 R2 = Encoding >> 4 & 1;
172 assert((!R2 || (Kind <= REX2 || Kind == EVEX)) && "invalid setting");
173 }
174 void setX(unsigned Encoding) { X = Encoding >> 3 & 1; }
175 void setX2(unsigned Encoding) {
176 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting");
177 X2 = Encoding >> 4 & 1;
178 }
179 void setB(unsigned Encoding) { B = Encoding >> 3 & 1; }
180 void setB2(unsigned Encoding) {
181 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting");
182 B2 = Encoding >> 4 & 1;
183 }
184 void set4V(unsigned Encoding) { VEX_4V = Encoding & 0xf; }
185 void setV2(unsigned Encoding) { EVEX_V2 = Encoding >> 4 & 1; }
186
187public:
188 void setW(bool V) { W = V; }
189 void setR(const MCInst &MI, unsigned OpNum) {
190 setR(getRegEncoding(MI, OpNum));
191 }
192 void setX(const MCInst &MI, unsigned OpNum, unsigned Shift = 3) {
193 unsigned Reg = MI.getOperand(OpNum).getReg();
194 // X is used to extend vector register only when shift is not 3.
195 if (Shift != 3 && X86II::isApxExtendedReg(Reg))
196 return;
197 unsigned Encoding = MRI.getEncodingValue(Reg);
198 X = Encoding >> Shift & 1;
199 }
200 void setB(const MCInst &MI, unsigned OpNum) {
201 B = getRegEncoding(MI, OpNum) >> 3 & 1;
202 }
203 void set4V(const MCInst &MI, unsigned OpNum, bool IsImm = false) {
204 // OF, SF, ZF and CF reuse VEX_4V bits but are not reversed
205 if (IsImm)
206 set4V(~(MI.getOperand(OpNum).getImm()));
207 else
208 set4V(getRegEncoding(MI, OpNum));
209 }
210 void setL(bool V) { VEX_L = V; }
211 void setPP(unsigned V) { VEX_PP = V; }
212 void set5M(unsigned V) { VEX_5M = V; }
213 void setR2(const MCInst &MI, unsigned OpNum) {
214 setR2(getRegEncoding(MI, OpNum));
215 }
216 void setRR2(const MCInst &MI, unsigned OpNum) {
217 unsigned Encoding = getRegEncoding(MI, OpNum);
218 setR(Encoding);
219 setR2(Encoding);
220 }
221 void setM(bool V) { M = V; }
222 void setXX2(const MCInst &MI, unsigned OpNum) {
223 unsigned Reg = MI.getOperand(OpNum).getReg();
224 unsigned Encoding = MRI.getEncodingValue(Reg);
225 setX(Encoding);
226 // Index can be a vector register while X2 is used to extend GPR only.
227 if (Kind <= REX2 || X86II::isApxExtendedReg(Reg))
228 setX2(Encoding);
229 }
230 void setBB2(const MCInst &MI, unsigned OpNum) {
231 unsigned Reg = MI.getOperand(OpNum).getReg();
232 unsigned Encoding = MRI.getEncodingValue(Reg);
233 setB(Encoding);
234 // Base can be a vector register while B2 is used to extend GPR only
235 if (Kind <= REX2 || X86II::isApxExtendedReg(Reg))
236 setB2(Encoding);
237 }
238 void setZ(bool V) { EVEX_z = V; }
239 void setL2(bool V) { EVEX_L2 = V; }
240 void setEVEX_b(bool V) { EVEX_b = V; }
241 void setEVEX_U(bool V) { X2 = V; }
242 void setV2(const MCInst &MI, unsigned OpNum, bool HasVEX_4V) {
243 // Only needed with VSIB which don't use VVVV.
244 if (HasVEX_4V)
245 return;
246 unsigned Reg = MI.getOperand(OpNum).getReg();
248 return;
249 setV2(MRI.getEncodingValue(Reg));
250 }
251 void set4VV2(const MCInst &MI, unsigned OpNum) {
252 unsigned Encoding = getRegEncoding(MI, OpNum);
253 set4V(Encoding);
254 setV2(Encoding);
255 }
256 void setAAA(const MCInst &MI, unsigned OpNum) {
257 EVEX_aaa = getRegEncoding(MI, OpNum);
258 }
259 void setNF(bool V) { EVEX_aaa |= V << 2; }
260 void setSC(const MCInst &MI, unsigned OpNum) {
261 unsigned Encoding = MI.getOperand(OpNum).getImm();
262 EVEX_V2 = ~(Encoding >> 3) & 0x1;
263 EVEX_aaa = Encoding & 0x7;
264 }
265
266 X86OpcodePrefixHelper(const MCRegisterInfo &MRI)
267 : W(0), R(0), X(0), B(0), M(0), R2(0), X2(0), B2(0), VEX_4V(0), VEX_L(0),
268 VEX_PP(0), VEX_5M(0), EVEX_z(0), EVEX_L2(0), EVEX_b(0), EVEX_V2(0),
269 EVEX_aaa(0), MRI(MRI) {}
270
271 void setLowerBound(PrefixKind K) { Kind = K; }
272
273 PrefixKind determineOptimalKind() {
274 switch (Kind) {
275 case None:
276 // Not M bit here by intention b/c
277 // 1. No guarantee that REX2 is supported by arch w/o explict EGPR
278 // 2. REX2 is longer than 0FH
279 Kind = (R2 | X2 | B2) ? REX2 : (W | R | X | B) ? REX : None;
280 break;
281 case REX:
282 Kind = (R2 | X2 | B2) ? REX2 : REX;
283 break;
284 case REX2:
285 case XOP:
286 case VEX3:
287 case EVEX:
288 break;
289 case VEX2:
290 Kind = (W | X | B | (VEX_5M != 1)) ? VEX3 : VEX2;
291 break;
292 }
293 return Kind;
294 }
295
296 void emit(SmallVectorImpl<char> &CB) const {
297 uint8_t FirstPayload =
298 ((~R) & 0x1) << 7 | ((~X) & 0x1) << 6 | ((~B) & 0x1) << 5;
299 uint8_t LastPayload = ((~VEX_4V) & 0xf) << 3 | VEX_L << 2 | VEX_PP;
300 switch (Kind) {
301 case None:
302 return;
303 case REX:
304 emitByte(0x40 | W << 3 | R << 2 | X << 1 | B, CB);
305 return;
306 case REX2:
307 emitByte(0xD5, CB);
308 emitByte(M << 7 | R2 << 6 | X2 << 5 | B2 << 4 | W << 3 | R << 2 | X << 1 |
309 B,
310 CB);
311 return;
312 case VEX2:
313 emitByte(0xC5, CB);
314 emitByte(((~R) & 1) << 7 | LastPayload, CB);
315 return;
316 case VEX3:
317 case XOP:
318 emitByte(Kind == VEX3 ? 0xC4 : 0x8F, CB);
319 emitByte(FirstPayload | VEX_5M, CB);
320 emitByte(W << 7 | LastPayload, CB);
321 return;
322 case EVEX:
323 assert(VEX_5M && !(VEX_5M & 0x8) && "invalid mmm fields for EVEX!");
324 emitByte(0x62, CB);
325 emitByte(FirstPayload | ((~R2) & 0x1) << 4 | B2 << 3 | VEX_5M, CB);
326 emitByte(W << 7 | ((~VEX_4V) & 0xf) << 3 | ((~X2) & 0x1) << 2 | VEX_PP,
327 CB);
328 emitByte(EVEX_z << 7 | EVEX_L2 << 6 | VEX_L << 5 | EVEX_b << 4 |
329 ((~EVEX_V2) & 0x1) << 3 | EVEX_aaa,
330 CB);
331 return;
332 }
333 }
334};
335
336class X86MCCodeEmitter : public MCCodeEmitter {
337 const MCInstrInfo &MCII;
338 MCContext &Ctx;
339
340public:
341 X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
342 : MCII(mcii), Ctx(ctx) {}
343 X86MCCodeEmitter(const X86MCCodeEmitter &) = delete;
344 X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete;
345 ~X86MCCodeEmitter() override = default;
346
347 void emitPrefix(const MCInst &MI, SmallVectorImpl<char> &CB,
348 const MCSubtargetInfo &STI) const;
349
352 const MCSubtargetInfo &STI) const override;
353
354private:
355 unsigned getX86RegNum(const MCOperand &MO) const;
356
357 unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const;
358
359 void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
360 MCFixupKind FixupKind, uint64_t StartByte,
362 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const;
363
364 void emitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
365 SmallVectorImpl<char> &CB) const;
366
367 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
368 SmallVectorImpl<char> &CB) const;
369
370 void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
371 uint64_t TSFlags, PrefixKind Kind, uint64_t StartByte,
374 const MCSubtargetInfo &STI,
375 bool ForceSIB = false) const;
376
377 PrefixKind emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
378 const MCSubtargetInfo &STI,
379 SmallVectorImpl<char> &CB) const;
380
381 PrefixKind emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
382 const MCSubtargetInfo &STI,
383 SmallVectorImpl<char> &CB) const;
384
385 void emitSegmentOverridePrefix(unsigned SegOperand, const MCInst &MI,
386 SmallVectorImpl<char> &CB) const;
387
388 PrefixKind emitOpcodePrefix(int MemOperand, const MCInst &MI,
389 const MCSubtargetInfo &STI,
390 SmallVectorImpl<char> &CB) const;
391
392 PrefixKind emitREXPrefix(int MemOperand, const MCInst &MI,
393 const MCSubtargetInfo &STI,
394 SmallVectorImpl<char> &CB) const;
395};
396
397} // end anonymous namespace
398
399static uint8_t modRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) {
400 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
401 return RM | (RegOpcode << 3) | (Mod << 6);
402}
403
404static void emitConstant(uint64_t Val, unsigned Size,
406 // Output the constant in little endian byte order.
407 for (unsigned i = 0; i != Size; ++i) {
408 emitByte(Val & 255, CB);
409 Val >>= 8;
410 }
411}
412
413/// Determine if this immediate can fit in a disp8 or a compressed disp8 for
414/// EVEX instructions. \p will be set to the value to pass to the ImmOffset
415/// parameter of emitImmediate.
416static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) {
417 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
418
419 unsigned CD8_Scale =
421 CD8_Scale = CD8_Scale ? 1U << (CD8_Scale - 1) : 0U;
422 if (!HasEVEX || !CD8_Scale)
423 return isInt<8>(Value);
424
425 assert(isPowerOf2_32(CD8_Scale) && "Unexpected CD8 scale!");
426 if (Value & (CD8_Scale - 1)) // Unaligned offset
427 return false;
428
429 int CDisp8 = Value / static_cast<int>(CD8_Scale);
430 if (!isInt<8>(CDisp8))
431 return false;
432
433 // ImmOffset will be added to Value in emitImmediate leaving just CDisp8.
434 ImmOffset = CDisp8 - Value;
435 return true;
436}
437
438/// \returns the appropriate fixup kind to use for an immediate in an
439/// instruction with the specified TSFlags.
441 unsigned Size = X86II::getSizeOfImm(TSFlags);
442 bool isPCRel = X86II::isImmPCRel(TSFlags);
443
444 if (X86II::isImmSigned(TSFlags)) {
445 switch (Size) {
446 default:
447 llvm_unreachable("Unsupported signed fixup size!");
448 case 4:
450 }
451 }
453}
454
456
457/// Check if this expression starts with _GLOBAL_OFFSET_TABLE_ and if it is
458/// of the form _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on
459/// ELF i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
460/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start of a
461/// binary expression.
464 const MCExpr *RHS = nullptr;
465 if (Expr->getKind() == MCExpr::Binary) {
466 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
467 Expr = BE->getLHS();
468 RHS = BE->getRHS();
469 }
470
471 if (Expr->getKind() != MCExpr::SymbolRef)
472 return GOT_None;
473
474 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
475 const MCSymbol &S = Ref->getSymbol();
476 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
477 return GOT_None;
478 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
479 return GOT_SymDiff;
480 return GOT_Normal;
481}
482
483static bool hasSecRelSymbolRef(const MCExpr *Expr) {
484 if (Expr->getKind() == MCExpr::SymbolRef) {
485 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
486 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
487 }
488 return false;
489}
490
491static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII) {
492 unsigned Opcode = MI.getOpcode();
493 const MCInstrDesc &Desc = MCII.get(Opcode);
494 if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4 &&
495 Opcode != X86::JCC_4) ||
496 getImmFixupKind(Desc.TSFlags) != FK_PCRel_4)
497 return false;
498
499 unsigned CurOp = X86II::getOperandBias(Desc);
500 const MCOperand &Op = MI.getOperand(CurOp);
501 if (!Op.isExpr())
502 return false;
503
504 const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(Op.getExpr());
505 return Ref && Ref->getKind() == MCSymbolRefExpr::VK_None;
506}
507
508unsigned X86MCCodeEmitter::getX86RegNum(const MCOperand &MO) const {
509 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
510}
511
512unsigned X86MCCodeEmitter::getX86RegEncoding(const MCInst &MI,
513 unsigned OpNum) const {
514 return Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(OpNum).getReg());
515}
516
517void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
518 unsigned Size, MCFixupKind FixupKind,
519 uint64_t StartByte,
522 int ImmOffset) const {
523 const MCExpr *Expr = nullptr;
524 if (DispOp.isImm()) {
525 // If this is a simple integer displacement that doesn't require a
526 // relocation, emit it now.
527 if (FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 &&
528 FixupKind != FK_PCRel_4) {
529 emitConstant(DispOp.getImm() + ImmOffset, Size, CB);
530 return;
531 }
532 Expr = MCConstantExpr::create(DispOp.getImm(), Ctx);
533 } else {
534 Expr = DispOp.getExpr();
535 }
536
537 // If we have an immoffset, add it to the expression.
538 if ((FixupKind == FK_Data_4 || FixupKind == FK_Data_8 ||
539 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
541 if (Kind != GOT_None) {
542 assert(ImmOffset == 0);
543
544 if (Size == 8) {
546 } else {
547 assert(Size == 4);
549 }
550
551 if (Kind == GOT_Normal)
552 ImmOffset = static_cast<int>(CB.size() - StartByte);
553 } else if (Expr->getKind() == MCExpr::SymbolRef) {
554 if (hasSecRelSymbolRef(Expr)) {
556 }
557 } else if (Expr->getKind() == MCExpr::Binary) {
558 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr *>(Expr);
559 if (hasSecRelSymbolRef(Bin->getLHS()) ||
560 hasSecRelSymbolRef(Bin->getRHS())) {
562 }
563 }
564 }
565
566 // If the fixup is pc-relative, we need to bias the value to be relative to
567 // the start of the field, not the end of the field.
568 if (FixupKind == FK_PCRel_4 ||
569 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
574 ImmOffset -= 4;
575 // If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
576 // leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
577 // this needs to be a GOTPC32 relocation.
580 }
581 if (FixupKind == FK_PCRel_2)
582 ImmOffset -= 2;
583 if (FixupKind == FK_PCRel_1)
584 ImmOffset -= 1;
585
586 if (ImmOffset)
587 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx),
588 Ctx);
589
590 // Emit a symbolic constant as a fixup and 4 zeros.
591 Fixups.push_back(MCFixup::create(static_cast<uint32_t>(CB.size() - StartByte),
592 Expr, FixupKind, Loc));
593 emitConstant(0, Size, CB);
594}
595
596void X86MCCodeEmitter::emitRegModRMByte(const MCOperand &ModRMReg,
597 unsigned RegOpcodeFld,
598 SmallVectorImpl<char> &CB) const {
599 emitByte(modRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)), CB);
600}
601
602void X86MCCodeEmitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
603 SmallVectorImpl<char> &CB) const {
604 // SIB byte is in the same format as the modRMByte.
605 emitByte(modRMByte(SS, Index, Base), CB);
606}
607
608void X86MCCodeEmitter::emitMemModRMByte(
609 const MCInst &MI, unsigned Op, unsigned RegOpcodeField, uint64_t TSFlags,
610 PrefixKind Kind, uint64_t StartByte, SmallVectorImpl<char> &CB,
611 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI,
612 bool ForceSIB) const {
613 const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
614 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
615 const MCOperand &Scale = MI.getOperand(Op + X86::AddrScaleAmt);
616 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg);
617 unsigned BaseReg = Base.getReg();
618
619 // Handle %rip relative addressing.
620 if (BaseReg == X86::RIP ||
621 BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
622 assert(STI.hasFeature(X86::Is64Bit) &&
623 "Rip-relative addressing requires 64-bit mode");
624 assert(IndexReg.getReg() == 0 && !ForceSIB &&
625 "Invalid rip-relative address");
626 emitByte(modRMByte(0, RegOpcodeField, 5), CB);
627
628 unsigned Opcode = MI.getOpcode();
629 unsigned FixupKind = [&]() {
630 // Enable relaxed relocation only for a MCSymbolRefExpr. We cannot use a
631 // relaxed relocation if an offset is present (e.g. x@GOTPCREL+4).
632 if (!(Disp.isExpr() && isa<MCSymbolRefExpr>(Disp.getExpr())))
634
635 // Certain loads for GOT references can be relocated against the symbol
636 // directly if the symbol ends up in the same linkage unit.
637 switch (Opcode) {
638 default:
640 case X86::MOV64rm:
641 // movq loads is a subset of reloc_riprel_4byte_relax_rex. It is a
642 // special case because COFF and Mach-O don't support ELF's more
643 // flexible R_X86_64_REX_GOTPCRELX relaxation.
644 // TODO: Support new relocation for REX2.
645 assert(Kind == REX || Kind == REX2);
647 case X86::ADC32rm:
648 case X86::ADD32rm:
649 case X86::AND32rm:
650 case X86::CMP32rm:
651 case X86::MOV32rm:
652 case X86::OR32rm:
653 case X86::SBB32rm:
654 case X86::SUB32rm:
655 case X86::TEST32mr:
656 case X86::XOR32rm:
657 case X86::CALL64m:
658 case X86::JMP64m:
659 case X86::TAILJMPm64:
660 case X86::TEST64mr:
661 case X86::ADC64rm:
662 case X86::ADD64rm:
663 case X86::AND64rm:
664 case X86::CMP64rm:
665 case X86::OR64rm:
666 case X86::SBB64rm:
667 case X86::SUB64rm:
668 case X86::XOR64rm:
669 // We haven't support relocation for REX2 prefix, so temporarily use REX
670 // relocation.
671 // TODO: Support new relocation for REX2.
672 return (Kind == REX || Kind == REX2) ? X86::reloc_riprel_4byte_relax_rex
674 }
675 }();
676
677 // rip-relative addressing is actually relative to the *next* instruction.
678 // Since an immediate can follow the mod/rm byte for an instruction, this
679 // means that we need to bias the displacement field of the instruction with
680 // the size of the immediate field. If we have this case, add it into the
681 // expression to emit.
682 // Note: rip-relative addressing using immediate displacement values should
683 // not be adjusted, assuming it was the user's intent.
684 int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags)
685 ? X86II::getSizeOfImm(TSFlags)
686 : 0;
687
688 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, CB,
689 Fixups, -ImmSize);
690 return;
691 }
692
693 unsigned BaseRegNo = BaseReg ? getX86RegNum(Base) : -1U;
694
695 bool IsAdSize16 = STI.hasFeature(X86::Is32Bit) &&
696 (TSFlags & X86II::AdSizeMask) == X86II::AdSize16;
697
698 // 16-bit addressing forms of the ModR/M byte have a different encoding for
699 // the R/M field and are far more limited in which registers can be used.
700 if (IsAdSize16 || X86_MC::is16BitMemOperand(MI, Op, STI)) {
701 if (BaseReg) {
702 // For 32-bit addressing, the row and column values in Table 2-2 are
703 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
704 // some special cases. And getX86RegNum reflects that numbering.
705 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
706 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
707 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
708 // while values 0-3 indicate the allowed combinations (base+index) of
709 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
710 //
711 // R16Table[] is a lookup from the normal RegNo, to the row values from
712 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
713 static const unsigned R16Table[] = {0, 0, 0, 7, 0, 6, 4, 5};
714 unsigned RMfield = R16Table[BaseRegNo];
715
716 assert(RMfield && "invalid 16-bit base register");
717
718 if (IndexReg.getReg()) {
719 unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)];
720
721 assert(IndexReg16 && "invalid 16-bit index register");
722 // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
723 assert(((IndexReg16 ^ RMfield) & 2) &&
724 "invalid 16-bit base/index register combination");
725 assert(Scale.getImm() == 1 &&
726 "invalid scale for 16-bit memory reference");
727
728 // Allow base/index to appear in either order (although GAS doesn't).
729 if (IndexReg16 & 2)
730 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
731 else
732 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
733 }
734
735 if (Disp.isImm() && isInt<8>(Disp.getImm())) {
736 if (Disp.getImm() == 0 && RMfield != 6) {
737 // There is no displacement; just the register.
738 emitByte(modRMByte(0, RegOpcodeField, RMfield), CB);
739 return;
740 }
741 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
742 emitByte(modRMByte(1, RegOpcodeField, RMfield), CB);
743 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups);
744 return;
745 }
746 // This is the [REG]+disp16 case.
747 emitByte(modRMByte(2, RegOpcodeField, RMfield), CB);
748 } else {
749 assert(IndexReg.getReg() == 0 && "Unexpected index register!");
750 // There is no BaseReg; this is the plain [disp16] case.
751 emitByte(modRMByte(0, RegOpcodeField, 6), CB);
752 }
753
754 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
755 emitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, StartByte, CB, Fixups);
756 return;
757 }
758
759 // Check for presence of {disp8} or {disp32} pseudo prefixes.
760 bool UseDisp8 = MI.getFlags() & X86::IP_USE_DISP8;
761 bool UseDisp32 = MI.getFlags() & X86::IP_USE_DISP32;
762
763 // We only allow no displacement if no pseudo prefix is present.
764 bool AllowNoDisp = !UseDisp8 && !UseDisp32;
765 // Disp8 is allowed unless the {disp32} prefix is present.
766 bool AllowDisp8 = !UseDisp32;
767
768 // Determine whether a SIB byte is needed.
769 if (!ForceSIB && !X86II::needSIB(BaseReg, IndexReg.getReg(),
770 STI.hasFeature(X86::Is64Bit))) {
771 if (BaseReg == 0) { // [disp32] in X86-32 mode
772 emitByte(modRMByte(0, RegOpcodeField, 5), CB);
773 emitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, StartByte, CB, Fixups);
774 return;
775 }
776
777 // If the base is not EBP/ESP/R12/R13/R20/R21/R28/R29 and there is no
778 // displacement, use simple indirect register encoding, this handles
779 // addresses like [EAX]. The encoding for [EBP], [R13], [R20], [R21], [R28]
780 // or [R29] with no displacement means [disp32] so we handle it by emitting
781 // a displacement of 0 later.
782 if (BaseRegNo != N86::EBP) {
783 if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp) {
784 emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CB);
785 return;
786 }
787
788 // If the displacement is @tlscall, treat it as a zero.
789 if (Disp.isExpr()) {
790 auto *Sym = dyn_cast<MCSymbolRefExpr>(Disp.getExpr());
791 if (Sym && Sym->getKind() == MCSymbolRefExpr::VK_TLSCALL) {
792 // This is exclusively used by call *a@tlscall(base). The relocation
793 // (R_386_TLSCALL or R_X86_64_TLSCALL) applies to the beginning.
794 Fixups.push_back(MCFixup::create(0, Sym, FK_NONE, MI.getLoc()));
795 emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CB);
796 return;
797 }
798 }
799 }
800
801 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
802 // Including a compressed disp8 for EVEX instructions that support it.
803 // This also handles the 0 displacement for [EBP], [R13], [R21] or [R29]. We
804 // can't use disp8 if the {disp32} pseudo prefix is present.
805 if (Disp.isImm() && AllowDisp8) {
806 int ImmOffset = 0;
807 if (isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
808 emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), CB);
809 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups,
810 ImmOffset);
811 return;
812 }
813 }
814
815 // Otherwise, emit the most general non-SIB encoding: [REG+disp32].
816 // Displacement may be 0 for [EBP], [R13], [R21], [R29] case if {disp32}
817 // pseudo prefix prevented using disp8 above.
818 emitByte(modRMByte(2, RegOpcodeField, BaseRegNo), CB);
819 unsigned Opcode = MI.getOpcode();
820 unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax
822 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, CB,
823 Fixups);
824 return;
825 }
826
827 // We need a SIB byte, so start by outputting the ModR/M byte first
828 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP &&
829 "Cannot use ESP as index reg!");
830
831 bool ForceDisp32 = false;
832 bool ForceDisp8 = false;
833 int ImmOffset = 0;
834 if (BaseReg == 0) {
835 // If there is no base register, we emit the special case SIB byte with
836 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
837 BaseRegNo = 5;
838 emitByte(modRMByte(0, RegOpcodeField, 4), CB);
839 ForceDisp32 = true;
840 } else if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp &&
841 // Base reg can't be EBP/RBP/R13/R21/R29 as that would end up with
842 // '5' as the base field, but that is the magic [*] nomenclature
843 // that indicates no base when mod=0. For these cases we'll emit a
844 // 0 displacement instead.
845 BaseRegNo != N86::EBP) {
846 // Emit no displacement ModR/M byte
847 emitByte(modRMByte(0, RegOpcodeField, 4), CB);
848 } else if (Disp.isImm() && AllowDisp8 &&
849 isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
850 // Displacement fits in a byte or matches an EVEX compressed disp8, use
851 // disp8 encoding. This also handles EBP/R13/R21/R29 base with 0
852 // displacement unless {disp32} pseudo prefix was used.
853 emitByte(modRMByte(1, RegOpcodeField, 4), CB);
854 ForceDisp8 = true;
855 } else {
856 // Otherwise, emit the normal disp32 encoding.
857 emitByte(modRMByte(2, RegOpcodeField, 4), CB);
858 ForceDisp32 = true;
859 }
860
861 // Calculate what the SS field value should be...
862 static const unsigned SSTable[] = {~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3};
863 unsigned SS = SSTable[Scale.getImm()];
864
865 unsigned IndexRegNo = IndexReg.getReg() ? getX86RegNum(IndexReg) : 4;
866
867 emitSIBByte(SS, IndexRegNo, BaseRegNo, CB);
868
869 // Do we need to output a displacement?
870 if (ForceDisp8)
871 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups,
872 ImmOffset);
873 else if (ForceDisp32)
874 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
875 StartByte, CB, Fixups);
876}
877
878/// Emit all instruction prefixes.
879///
880/// \returns one of the REX, XOP, VEX2, VEX3, EVEX if any of them is used,
881/// otherwise returns None.
882PrefixKind X86MCCodeEmitter::emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
883 const MCSubtargetInfo &STI,
884 SmallVectorImpl<char> &CB) const {
885 uint64_t TSFlags = MCII.get(MI.getOpcode()).TSFlags;
886 // Determine where the memory operand starts, if present.
887 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
888 // Emit segment override opcode prefix as needed.
889 if (MemoryOperand != -1) {
890 MemoryOperand += CurOp;
891 emitSegmentOverridePrefix(MemoryOperand + X86::AddrSegmentReg, MI, CB);
892 }
893
894 // Emit the repeat opcode prefix as needed.
895 unsigned Flags = MI.getFlags();
896 if (TSFlags & X86II::REP || Flags & X86::IP_HAS_REPEAT)
897 emitByte(0xF3, CB);
898 if (Flags & X86::IP_HAS_REPEAT_NE)
899 emitByte(0xF2, CB);
900
901 // Emit the address size opcode prefix as needed.
902 if (X86_MC::needsAddressSizeOverride(MI, STI, MemoryOperand, TSFlags) ||
903 Flags & X86::IP_HAS_AD_SIZE)
904 emitByte(0x67, CB);
905
906 uint64_t Form = TSFlags & X86II::FormMask;
907 switch (Form) {
908 default:
909 break;
910 case X86II::RawFrmDstSrc: {
911 // Emit segment override opcode prefix as needed (not for %ds).
912 if (MI.getOperand(2).getReg() != X86::DS)
913 emitSegmentOverridePrefix(2, MI, CB);
914 CurOp += 3; // Consume operands.
915 break;
916 }
917 case X86II::RawFrmSrc: {
918 // Emit segment override opcode prefix as needed (not for %ds).
919 if (MI.getOperand(1).getReg() != X86::DS)
920 emitSegmentOverridePrefix(1, MI, CB);
921 CurOp += 2; // Consume operands.
922 break;
923 }
924 case X86II::RawFrmDst: {
925 ++CurOp; // Consume operand.
926 break;
927 }
929 // Emit segment override opcode prefix as needed.
930 emitSegmentOverridePrefix(1, MI, CB);
931 break;
932 }
933 }
934
935 // REX prefix is optional, but if used must be immediately before the opcode
936 // Encoding type for this instruction.
937 return (TSFlags & X86II::EncodingMask)
938 ? emitVEXOpcodePrefix(MemoryOperand, MI, STI, CB)
939 : emitOpcodePrefix(MemoryOperand, MI, STI, CB);
940}
941
942// AVX instructions are encoded using an encoding scheme that combines
943// prefix bytes, opcode extension field, operand encoding fields, and vector
944// length encoding capability into a new prefix, referred to as VEX.
945
946// The majority of the AVX-512 family of instructions (operating on
947// 512/256/128-bit vector register operands) are encoded using a new prefix
948// (called EVEX).
949
950// XOP is a revised subset of what was originally intended as SSE5. It was
951// changed to be similar but not overlapping with AVX.
952
953/// Emit XOP, VEX2, VEX3 or EVEX prefix.
954/// \returns the used prefix.
955PrefixKind
956X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
957 const MCSubtargetInfo &STI,
958 SmallVectorImpl<char> &CB) const {
959 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
960 uint64_t TSFlags = Desc.TSFlags;
961
962 assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
963
964#ifndef NDEBUG
965 unsigned NumOps = MI.getNumOperands();
966 for (unsigned I = NumOps ? X86II::getOperandBias(Desc) : 0; I != NumOps;
967 ++I) {
968 const MCOperand &MO = MI.getOperand(I);
969 if (!MO.isReg())
970 continue;
971 unsigned Reg = MO.getReg();
972 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
974 "Cannot encode high byte register in VEX/EVEX-prefixed instruction");
975 }
976#endif
977
978 X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
979 switch (TSFlags & X86II::EncodingMask) {
980 default:
981 break;
982 case X86II::XOP:
983 Prefix.setLowerBound(XOP);
984 break;
985 case X86II::VEX:
986 // VEX can be 2 byte or 3 byte, not determined yet if not explicit
987 Prefix.setLowerBound((MI.getFlags() & X86::IP_USE_VEX3) ? VEX3 : VEX2);
988 break;
989 case X86II::EVEX:
990 Prefix.setLowerBound(EVEX);
991 break;
992 }
993
994 Prefix.setW(TSFlags & X86II::REX_W);
995 Prefix.setNF(TSFlags & X86II::EVEX_NF);
996
997 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
998 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
999 bool IsND = X86II::hasNewDataDest(TSFlags); // IsND implies HasVEX_4V
1000 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
1001
1002 switch (TSFlags & X86II::OpMapMask) {
1003 default:
1004 llvm_unreachable("Invalid prefix!");
1005 case X86II::TB:
1006 Prefix.set5M(0x1); // 0F
1007 break;
1008 case X86II::T8:
1009 Prefix.set5M(0x2); // 0F 38
1010 break;
1011 case X86II::TA:
1012 Prefix.set5M(0x3); // 0F 3A
1013 break;
1014 case X86II::XOP8:
1015 Prefix.set5M(0x8);
1016 break;
1017 case X86II::XOP9:
1018 Prefix.set5M(0x9);
1019 break;
1020 case X86II::XOPA:
1021 Prefix.set5M(0xA);
1022 break;
1023 case X86II::T_MAP4:
1024 Prefix.set5M(0x4);
1025 break;
1026 case X86II::T_MAP5:
1027 Prefix.set5M(0x5);
1028 break;
1029 case X86II::T_MAP6:
1030 Prefix.set5M(0x6);
1031 break;
1032 case X86II::T_MAP7:
1033 Prefix.set5M(0x7);
1034 break;
1035 }
1036
1037 Prefix.setL(TSFlags & X86II::VEX_L);
1038 Prefix.setL2(TSFlags & X86II::EVEX_L2);
1039 if ((TSFlags & X86II::EVEX_L2) && STI.hasFeature(X86::FeatureAVX512) &&
1040 !STI.hasFeature(X86::FeatureEVEX512))
1041 report_fatal_error("ZMM registers are not supported without EVEX512");
1042 switch (TSFlags & X86II::OpPrefixMask) {
1043 case X86II::PD:
1044 Prefix.setPP(0x1); // 66
1045 break;
1046 case X86II::XS:
1047 Prefix.setPP(0x2); // F3
1048 break;
1049 case X86II::XD:
1050 Prefix.setPP(0x3); // F2
1051 break;
1052 }
1053
1054 Prefix.setZ(HasEVEX_K && (TSFlags & X86II::EVEX_Z));
1055 Prefix.setEVEX_b(TSFlags & X86II::EVEX_B);
1056 Prefix.setEVEX_U(TSFlags & X86II::EVEX_U);
1057
1058 bool EncodeRC = false;
1059 uint8_t EVEX_rc = 0;
1060
1061 unsigned CurOp = X86II::getOperandBias(Desc);
1062 bool HasTwoConditionalOps = TSFlags & X86II::TwoConditionalOps;
1063
1064 switch (TSFlags & X86II::FormMask) {
1065 default:
1066 llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!");
1068 // src1(ModR/M), MemAddr, src2(VEX_4V)
1069 Prefix.setRR2(MI, CurOp++);
1070 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1071 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1072 CurOp += X86::AddrNumOperands;
1073 Prefix.set4VV2(MI, CurOp++);
1074 break;
1075 }
1076 case X86II::MRM_C0:
1077 case X86II::RawFrm:
1078 break;
1081 case X86II::MRMDestMem: {
1082 // MRMDestMem instructions forms:
1083 // MemAddr, src1(ModR/M)
1084 // MemAddr, src1(VEX_4V), src2(ModR/M)
1085 // MemAddr, src1(ModR/M), imm8
1086 //
1087 // NDD:
1088 // dst(VEX_4V), MemAddr, src1(ModR/M)
1089 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1090 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1091 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V);
1092
1093 if (IsND)
1094 Prefix.set4VV2(MI, CurOp++);
1095
1096 CurOp += X86::AddrNumOperands;
1097
1098 if (HasEVEX_K)
1099 Prefix.setAAA(MI, CurOp++);
1100
1101 if (!IsND && HasVEX_4V)
1102 Prefix.set4VV2(MI, CurOp++);
1103
1104 Prefix.setRR2(MI, CurOp++);
1105 if (HasTwoConditionalOps) {
1106 Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1107 Prefix.setSC(MI, CurOp++);
1108 }
1109 break;
1110 }
1111 case X86II::MRMSrcMemCC:
1113 case X86II::MRMSrcMem: {
1114 // MRMSrcMem instructions forms:
1115 // src1(ModR/M), MemAddr
1116 // src1(ModR/M), src2(VEX_4V), MemAddr
1117 // src1(ModR/M), MemAddr, imm8
1118 // src1(ModR/M), MemAddr, src2(Imm[7:4])
1119 //
1120 // FMA4:
1121 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
1122 //
1123 // NDD:
1124 // dst(VEX_4V), src1(ModR/M), MemAddr
1125 if (IsND)
1126 Prefix.set4VV2(MI, CurOp++);
1127
1128 Prefix.setRR2(MI, CurOp++);
1129
1130 if (HasEVEX_K)
1131 Prefix.setAAA(MI, CurOp++);
1132
1133 if (!IsND && HasVEX_4V)
1134 Prefix.set4VV2(MI, CurOp++);
1135
1136 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1137 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1138 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V);
1139 CurOp += X86::AddrNumOperands;
1140 if (HasTwoConditionalOps) {
1141 Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1142 Prefix.setSC(MI, CurOp++);
1143 }
1144 break;
1145 }
1146 case X86II::MRMSrcMem4VOp3: {
1147 // Instruction format for 4VOp3:
1148 // src1(ModR/M), MemAddr, src3(VEX_4V)
1149 Prefix.setRR2(MI, CurOp++);
1150 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1151 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1152 Prefix.set4VV2(MI, CurOp + X86::AddrNumOperands);
1153 break;
1154 }
1155 case X86II::MRMSrcMemOp4: {
1156 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
1157 Prefix.setR(MI, CurOp++);
1158 Prefix.set4V(MI, CurOp++);
1159 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1160 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1161 break;
1162 }
1163 case X86II::MRMXmCC:
1164 case X86II::MRM0m:
1165 case X86II::MRM1m:
1166 case X86II::MRM2m:
1167 case X86II::MRM3m:
1168 case X86II::MRM4m:
1169 case X86II::MRM5m:
1170 case X86II::MRM6m:
1171 case X86II::MRM7m: {
1172 // MRM[0-9]m instructions forms:
1173 // MemAddr
1174 // src1(VEX_4V), MemAddr
1175 if (HasVEX_4V)
1176 Prefix.set4VV2(MI, CurOp++);
1177
1178 if (HasEVEX_K)
1179 Prefix.setAAA(MI, CurOp++);
1180
1181 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1182 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1183 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V);
1184 CurOp += X86::AddrNumOperands + 1; // Skip first imm.
1185 if (HasTwoConditionalOps) {
1186 Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1187 Prefix.setSC(MI, CurOp++);
1188 }
1189 break;
1190 }
1191 case X86II::MRMSrcRegCC:
1192 case X86II::MRMSrcReg: {
1193 // MRMSrcReg instructions forms:
1194 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
1195 // dst(ModR/M), src1(ModR/M)
1196 // dst(ModR/M), src1(ModR/M), imm8
1197 //
1198 // FMA4:
1199 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
1200 //
1201 // NDD:
1202 // dst(VEX_4V), src1(ModR/M.reg), src2(ModR/M)
1203 if (IsND)
1204 Prefix.set4VV2(MI, CurOp++);
1205 Prefix.setRR2(MI, CurOp++);
1206
1207 if (HasEVEX_K)
1208 Prefix.setAAA(MI, CurOp++);
1209
1210 if (!IsND && HasVEX_4V)
1211 Prefix.set4VV2(MI, CurOp++);
1212
1213 Prefix.setBB2(MI, CurOp);
1214 Prefix.setX(MI, CurOp, 4);
1215 ++CurOp;
1216
1217 if (HasTwoConditionalOps) {
1218 Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1219 Prefix.setSC(MI, CurOp++);
1220 }
1221
1222 if (TSFlags & X86II::EVEX_B) {
1223 if (HasEVEX_RC) {
1224 unsigned NumOps = Desc.getNumOperands();
1225 unsigned RcOperand = NumOps - 1;
1226 assert(RcOperand >= CurOp);
1227 EVEX_rc = MI.getOperand(RcOperand).getImm();
1228 assert(EVEX_rc <= 3 && "Invalid rounding control!");
1229 }
1230 EncodeRC = true;
1231 }
1232 break;
1233 }
1234 case X86II::MRMSrcReg4VOp3: {
1235 // Instruction format for 4VOp3:
1236 // src1(ModR/M), src2(ModR/M), src3(VEX_4V)
1237 Prefix.setRR2(MI, CurOp++);
1238 Prefix.setBB2(MI, CurOp++);
1239 Prefix.set4VV2(MI, CurOp++);
1240 break;
1241 }
1242 case X86II::MRMSrcRegOp4: {
1243 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
1244 Prefix.setR(MI, CurOp++);
1245 Prefix.set4V(MI, CurOp++);
1246 // Skip second register source (encoded in Imm[7:4])
1247 ++CurOp;
1248
1249 Prefix.setB(MI, CurOp);
1250 Prefix.setX(MI, CurOp, 4);
1251 ++CurOp;
1252 break;
1253 }
1255 case X86II::MRMDestReg: {
1256 // MRMDestReg instructions forms:
1257 // dst(ModR/M), src(ModR/M)
1258 // dst(ModR/M), src(ModR/M), imm8
1259 // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
1260 //
1261 // NDD:
1262 // dst(VEX_4V), src1(ModR/M), src2(ModR/M)
1263 if (IsND)
1264 Prefix.set4VV2(MI, CurOp++);
1265 Prefix.setBB2(MI, CurOp);
1266 Prefix.setX(MI, CurOp, 4);
1267 ++CurOp;
1268
1269 if (HasEVEX_K)
1270 Prefix.setAAA(MI, CurOp++);
1271
1272 if (!IsND && HasVEX_4V)
1273 Prefix.set4VV2(MI, CurOp++);
1274
1275 Prefix.setRR2(MI, CurOp++);
1276 if (HasTwoConditionalOps) {
1277 Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1278 Prefix.setSC(MI, CurOp++);
1279 }
1280 if (TSFlags & X86II::EVEX_B)
1281 EncodeRC = true;
1282 break;
1283 }
1284 case X86II::MRMr0: {
1285 // MRMr0 instructions forms:
1286 // 11:rrr:000
1287 // dst(ModR/M)
1288 Prefix.setRR2(MI, CurOp++);
1289 break;
1290 }
1291 case X86II::MRMXrCC:
1292 case X86II::MRM0r:
1293 case X86II::MRM1r:
1294 case X86II::MRM2r:
1295 case X86II::MRM3r:
1296 case X86II::MRM4r:
1297 case X86II::MRM5r:
1298 case X86II::MRM6r:
1299 case X86II::MRM7r: {
1300 // MRM0r-MRM7r instructions forms:
1301 // dst(VEX_4V), src(ModR/M), imm8
1302 if (HasVEX_4V)
1303 Prefix.set4VV2(MI, CurOp++);
1304
1305 if (HasEVEX_K)
1306 Prefix.setAAA(MI, CurOp++);
1307
1308 Prefix.setBB2(MI, CurOp);
1309 Prefix.setX(MI, CurOp, 4);
1310 ++CurOp;
1311 if (HasTwoConditionalOps) {
1312 Prefix.set4V(MI, ++CurOp, /*IsImm=*/true);
1313 Prefix.setSC(MI, ++CurOp);
1314 }
1315 break;
1316 }
1317 }
1318 if (EncodeRC) {
1319 Prefix.setL(EVEX_rc & 0x1);
1320 Prefix.setL2(EVEX_rc & 0x2);
1321 }
1322 PrefixKind Kind = Prefix.determineOptimalKind();
1323 Prefix.emit(CB);
1324 return Kind;
1325}
1326
1327/// Emit REX prefix which specifies
1328/// 1) 64-bit instructions,
1329/// 2) non-default operand size, and
1330/// 3) use of X86-64 extended registers.
1331///
1332/// \returns the used prefix (REX or None).
1333PrefixKind X86MCCodeEmitter::emitREXPrefix(int MemOperand, const MCInst &MI,
1334 const MCSubtargetInfo &STI,
1335 SmallVectorImpl<char> &CB) const {
1336 if (!STI.hasFeature(X86::Is64Bit))
1337 return None;
1338 X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
1339 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1340 uint64_t TSFlags = Desc.TSFlags;
1341 Prefix.setW(TSFlags & X86II::REX_W);
1342 unsigned NumOps = MI.getNumOperands();
1343 bool UsesHighByteReg = false;
1344#ifndef NDEBUG
1345 bool HasRegOp = false;
1346#endif
1347 unsigned CurOp = NumOps ? X86II::getOperandBias(Desc) : 0;
1348 for (unsigned i = CurOp; i != NumOps; ++i) {
1349 const MCOperand &MO = MI.getOperand(i);
1350 if (MO.isReg()) {
1351#ifndef NDEBUG
1352 HasRegOp = true;
1353#endif
1354 unsigned Reg = MO.getReg();
1355 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
1356 UsesHighByteReg = true;
1357 // If it accesses SPL, BPL, SIL, or DIL, then it requires a REX prefix.
1359 Prefix.setLowerBound(REX);
1360 } else if (MO.isExpr() && STI.getTargetTriple().isX32()) {
1361 // GOTTPOFF and TLSDESC relocations require a REX prefix to allow
1362 // linker optimizations: even if the instructions we see may not require
1363 // any prefix, they may be replaced by instructions that do. This is
1364 // handled as a special case here so that it also works for hand-written
1365 // assembly without the user needing to write REX, as with GNU as.
1366 const auto *Ref = dyn_cast<MCSymbolRefExpr>(MO.getExpr());
1367 if (Ref && (Ref->getKind() == MCSymbolRefExpr::VK_GOTTPOFF ||
1368 Ref->getKind() == MCSymbolRefExpr::VK_TLSDESC)) {
1369 Prefix.setLowerBound(REX);
1370 }
1371 }
1372 }
1373 if (MI.getFlags() & X86::IP_USE_REX)
1374 Prefix.setLowerBound(REX);
1376 MI.getFlags() & X86::IP_USE_REX2)
1377 Prefix.setLowerBound(REX2);
1378 switch (TSFlags & X86II::FormMask) {
1379 default:
1380 assert(!HasRegOp && "Unexpected form in emitREXPrefix!");
1381 break;
1382 case X86II::RawFrm:
1384 case X86II::RawFrmSrc:
1385 case X86II::RawFrmDst:
1387 break;
1388 case X86II::AddRegFrm:
1389 Prefix.setBB2(MI, CurOp++);
1390 break;
1391 case X86II::MRMSrcReg:
1392 case X86II::MRMSrcRegCC:
1393 Prefix.setRR2(MI, CurOp++);
1394 Prefix.setBB2(MI, CurOp++);
1395 break;
1396 case X86II::MRMSrcMem:
1397 case X86II::MRMSrcMemCC:
1398 Prefix.setRR2(MI, CurOp++);
1399 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1400 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1401 CurOp += X86::AddrNumOperands;
1402 break;
1403 case X86II::MRMDestReg:
1404 Prefix.setBB2(MI, CurOp++);
1405 Prefix.setRR2(MI, CurOp++);
1406 break;
1407 case X86II::MRMDestMem:
1408 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1409 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1410 CurOp += X86::AddrNumOperands;
1411 Prefix.setRR2(MI, CurOp++);
1412 break;
1413 case X86II::MRMXmCC:
1414 case X86II::MRMXm:
1415 case X86II::MRM0m:
1416 case X86II::MRM1m:
1417 case X86II::MRM2m:
1418 case X86II::MRM3m:
1419 case X86II::MRM4m:
1420 case X86II::MRM5m:
1421 case X86II::MRM6m:
1422 case X86II::MRM7m:
1423 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1424 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1425 break;
1426 case X86II::MRMXrCC:
1427 case X86II::MRMXr:
1428 case X86II::MRM0r:
1429 case X86II::MRM1r:
1430 case X86II::MRM2r:
1431 case X86II::MRM3r:
1432 case X86II::MRM4r:
1433 case X86II::MRM5r:
1434 case X86II::MRM6r:
1435 case X86II::MRM7r:
1436 Prefix.setBB2(MI, CurOp++);
1437 break;
1438 }
1439 Prefix.setM((TSFlags & X86II::OpMapMask) == X86II::TB);
1440 PrefixKind Kind = Prefix.determineOptimalKind();
1441 if (Kind && UsesHighByteReg)
1443 "Cannot encode high byte register in REX-prefixed instruction");
1444 Prefix.emit(CB);
1445 return Kind;
1446}
1447
1448/// Emit segment override opcode prefix as needed.
1449void X86MCCodeEmitter::emitSegmentOverridePrefix(
1450 unsigned SegOperand, const MCInst &MI, SmallVectorImpl<char> &CB) const {
1451 // Check for explicit segment override on memory operand.
1452 if (unsigned Reg = MI.getOperand(SegOperand).getReg())
1453 emitByte(X86::getSegmentOverridePrefixForReg(Reg), CB);
1454}
1455
1456/// Emit all instruction prefixes prior to the opcode.
1457///
1458/// \param MemOperand the operand # of the start of a memory operand if present.
1459/// If not present, it is -1.
1460///
1461/// \returns the used prefix (REX or None).
1462PrefixKind X86MCCodeEmitter::emitOpcodePrefix(int MemOperand, const MCInst &MI,
1463 const MCSubtargetInfo &STI,
1464 SmallVectorImpl<char> &CB) const {
1465 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1466 uint64_t TSFlags = Desc.TSFlags;
1467
1468 // Emit the operand size opcode prefix as needed.
1469 if ((TSFlags & X86II::OpSizeMask) ==
1470 (STI.hasFeature(X86::Is16Bit) ? X86II::OpSize32 : X86II::OpSize16))
1471 emitByte(0x66, CB);
1472
1473 // Emit the LOCK opcode prefix.
1474 if (TSFlags & X86II::LOCK || MI.getFlags() & X86::IP_HAS_LOCK)
1475 emitByte(0xF0, CB);
1476
1477 // Emit the NOTRACK opcode prefix.
1478 if (TSFlags & X86II::NOTRACK || MI.getFlags() & X86::IP_HAS_NOTRACK)
1479 emitByte(0x3E, CB);
1480
1481 switch (TSFlags & X86II::OpPrefixMask) {
1482 case X86II::PD: // 66
1483 emitByte(0x66, CB);
1484 break;
1485 case X86II::XS: // F3
1486 emitByte(0xF3, CB);
1487 break;
1488 case X86II::XD: // F2
1489 emitByte(0xF2, CB);
1490 break;
1491 }
1492
1493 // Handle REX prefix.
1494 assert((STI.hasFeature(X86::Is64Bit) || !(TSFlags & X86II::REX_W)) &&
1495 "REX.W requires 64bit mode.");
1496 PrefixKind Kind = emitREXPrefix(MemOperand, MI, STI, CB);
1497
1498 // 0x0F escape code must be emitted just before the opcode.
1499 switch (TSFlags & X86II::OpMapMask) {
1500 case X86II::TB: // Two-byte opcode map
1501 // Encoded by M bit in REX2
1502 if (Kind == REX2)
1503 break;
1504 [[fallthrough]];
1505 case X86II::T8: // 0F 38
1506 case X86II::TA: // 0F 3A
1507 case X86II::ThreeDNow: // 0F 0F, second 0F emitted by caller.
1508 emitByte(0x0F, CB);
1509 break;
1510 }
1511
1512 switch (TSFlags & X86II::OpMapMask) {
1513 case X86II::T8: // 0F 38
1514 emitByte(0x38, CB);
1515 break;
1516 case X86II::TA: // 0F 3A
1517 emitByte(0x3A, CB);
1518 break;
1519 }
1520
1521 return Kind;
1522}
1523
1524void X86MCCodeEmitter::emitPrefix(const MCInst &MI, SmallVectorImpl<char> &CB,
1525 const MCSubtargetInfo &STI) const {
1526 unsigned Opcode = MI.getOpcode();
1527 const MCInstrDesc &Desc = MCII.get(Opcode);
1528 uint64_t TSFlags = Desc.TSFlags;
1529
1530 // Pseudo instructions don't get encoded.
1531 if (X86II::isPseudo(TSFlags))
1532 return;
1533
1534 unsigned CurOp = X86II::getOperandBias(Desc);
1535
1536 emitPrefixImpl(CurOp, MI, STI, CB);
1537}
1538
1540 SmallVectorImpl<char> &CB, const MCSubtargetInfo &STI) {
1541 static_cast<X86MCCodeEmitter &>(MCE).emitPrefix(MI, CB, STI);
1542}
1543
1544void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
1547 const MCSubtargetInfo &STI) const {
1548 unsigned Opcode = MI.getOpcode();
1549 const MCInstrDesc &Desc = MCII.get(Opcode);
1550 uint64_t TSFlags = Desc.TSFlags;
1551
1552 // Pseudo instructions don't get encoded.
1553 if (X86II::isPseudo(TSFlags))
1554 return;
1555
1556 unsigned NumOps = Desc.getNumOperands();
1557 unsigned CurOp = X86II::getOperandBias(Desc);
1558
1559 uint64_t StartByte = CB.size();
1560
1561 PrefixKind Kind = emitPrefixImpl(CurOp, MI, STI, CB);
1562
1563 // It uses the VEX.VVVV field?
1564 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1565 bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg;
1566
1567 // It uses the EVEX.aaa field?
1568 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1569 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
1570
1571 // Used if a register is encoded in 7:4 of immediate.
1572 unsigned I8RegNum = 0;
1573
1574 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1575
1576 if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
1577 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1578
1579 unsigned OpcodeOffset = 0;
1580
1581 bool IsND = X86II::hasNewDataDest(TSFlags);
1582 bool HasTwoConditionalOps = TSFlags & X86II::TwoConditionalOps;
1583
1584 uint64_t Form = TSFlags & X86II::FormMask;
1585 switch (Form) {
1586 default:
1587 errs() << "FORM: " << Form << "\n";
1588 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1589 case X86II::Pseudo:
1590 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1592 case X86II::RawFrmSrc:
1593 case X86II::RawFrmDst:
1594 case X86II::PrefixByte:
1595 emitByte(BaseOpcode, CB);
1596 break;
1597 case X86II::AddCCFrm: {
1598 // This will be added to the opcode in the fallthrough.
1599 OpcodeOffset = MI.getOperand(NumOps - 1).getImm();
1600 assert(OpcodeOffset < 16 && "Unexpected opcode offset!");
1601 --NumOps; // Drop the operand from the end.
1602 [[fallthrough]];
1603 case X86II::RawFrm:
1604 emitByte(BaseOpcode + OpcodeOffset, CB);
1605
1606 if (!STI.hasFeature(X86::Is64Bit) || !isPCRel32Branch(MI, MCII))
1607 break;
1608
1609 const MCOperand &Op = MI.getOperand(CurOp++);
1610 emitImmediate(Op, MI.getLoc(), X86II::getSizeOfImm(TSFlags),
1612 Fixups);
1613 break;
1614 }
1616 emitByte(BaseOpcode, CB);
1617 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1618 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1619 StartByte, CB, Fixups);
1620 ++CurOp; // skip segment operand
1621 break;
1622 case X86II::RawFrmImm8:
1623 emitByte(BaseOpcode, CB);
1624 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1625 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1626 StartByte, CB, Fixups);
1627 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, StartByte,
1628 CB, Fixups);
1629 break;
1630 case X86II::RawFrmImm16:
1631 emitByte(BaseOpcode, CB);
1632 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1633 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1634 StartByte, CB, Fixups);
1635 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, StartByte,
1636 CB, Fixups);
1637 break;
1638
1639 case X86II::AddRegFrm:
1640 emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), CB);
1641 break;
1642
1643 case X86II::MRMDestReg: {
1644 emitByte(BaseOpcode, CB);
1645 unsigned SrcRegNum = CurOp + 1;
1646
1647 if (HasEVEX_K) // Skip writemask
1648 ++SrcRegNum;
1649
1650 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1651 ++SrcRegNum;
1652 if (IsND) // Skip the NDD operand encoded in EVEX_VVVV
1653 ++CurOp;
1654
1655 emitRegModRMByte(MI.getOperand(CurOp),
1656 getX86RegNum(MI.getOperand(SrcRegNum)), CB);
1657 CurOp = SrcRegNum + 1;
1658 break;
1659 }
1660 case X86II::MRMDestRegCC: {
1661 unsigned FirstOp = CurOp++;
1662 unsigned SecondOp = CurOp++;
1663 unsigned CC = MI.getOperand(CurOp++).getImm();
1664 emitByte(BaseOpcode + CC, CB);
1665 emitRegModRMByte(MI.getOperand(FirstOp),
1666 getX86RegNum(MI.getOperand(SecondOp)), CB);
1667 break;
1668 }
1670 unsigned CC = MI.getOperand(8).getImm();
1671 emitByte(BaseOpcode + CC, CB);
1672 unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1673 emitMemModRMByte(MI, CurOp + 1, getX86RegNum(MI.getOperand(0)), TSFlags,
1674 Kind, StartByte, CB, Fixups, STI, false);
1675 CurOp = SrcRegNum + 3; // skip reg, VEX_V4 and CC
1676 break;
1677 }
1679 case X86II::MRMDestMem: {
1680 emitByte(BaseOpcode, CB);
1681 unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1682
1683 if (HasEVEX_K) // Skip writemask
1684 ++SrcRegNum;
1685
1686 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1687 ++SrcRegNum;
1688
1689 if (IsND) // Skip new data destination
1690 ++CurOp;
1691
1692 bool ForceSIB = (Form == X86II::MRMDestMemFSIB);
1693 emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,
1694 Kind, StartByte, CB, Fixups, STI, ForceSIB);
1695 CurOp = SrcRegNum + 1;
1696 break;
1697 }
1698 case X86II::MRMDestMemCC: {
1699 unsigned MemOp = CurOp;
1700 CurOp = MemOp + X86::AddrNumOperands;
1701 unsigned RegOp = CurOp++;
1702 unsigned CC = MI.getOperand(CurOp++).getImm();
1703 emitByte(BaseOpcode + CC, CB);
1704 emitMemModRMByte(MI, MemOp, getX86RegNum(MI.getOperand(RegOp)), TSFlags,
1705 Kind, StartByte, CB, Fixups, STI);
1706 break;
1707 }
1708 case X86II::MRMSrcReg: {
1709 emitByte(BaseOpcode, CB);
1710 unsigned SrcRegNum = CurOp + 1;
1711
1712 if (HasEVEX_K) // Skip writemask
1713 ++SrcRegNum;
1714
1715 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1716 ++SrcRegNum;
1717
1718 if (IsND) // Skip new data destination
1719 ++CurOp;
1720
1721 emitRegModRMByte(MI.getOperand(SrcRegNum),
1722 getX86RegNum(MI.getOperand(CurOp)), CB);
1723 CurOp = SrcRegNum + 1;
1724 if (HasVEX_I8Reg)
1725 I8RegNum = getX86RegEncoding(MI, CurOp++);
1726 // do not count the rounding control operand
1727 if (HasEVEX_RC)
1728 --NumOps;
1729 break;
1730 }
1731 case X86II::MRMSrcReg4VOp3: {
1732 emitByte(BaseOpcode, CB);
1733 unsigned SrcRegNum = CurOp + 1;
1734
1735 emitRegModRMByte(MI.getOperand(SrcRegNum),
1736 getX86RegNum(MI.getOperand(CurOp)), CB);
1737 CurOp = SrcRegNum + 1;
1738 ++CurOp; // Encoded in VEX.VVVV
1739 break;
1740 }
1741 case X86II::MRMSrcRegOp4: {
1742 emitByte(BaseOpcode, CB);
1743 unsigned SrcRegNum = CurOp + 1;
1744
1745 // Skip 1st src (which is encoded in VEX_VVVV)
1746 ++SrcRegNum;
1747
1748 // Capture 2nd src (which is encoded in Imm[7:4])
1749 assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1750 I8RegNum = getX86RegEncoding(MI, SrcRegNum++);
1751
1752 emitRegModRMByte(MI.getOperand(SrcRegNum),
1753 getX86RegNum(MI.getOperand(CurOp)), CB);
1754 CurOp = SrcRegNum + 1;
1755 break;
1756 }
1757 case X86II::MRMSrcRegCC: {
1758 if (IsND) // Skip new data destination
1759 ++CurOp;
1760 unsigned FirstOp = CurOp++;
1761 unsigned SecondOp = CurOp++;
1762
1763 unsigned CC = MI.getOperand(CurOp++).getImm();
1764 emitByte(BaseOpcode + CC, CB);
1765
1766 emitRegModRMByte(MI.getOperand(SecondOp),
1767 getX86RegNum(MI.getOperand(FirstOp)), CB);
1768 break;
1769 }
1771 case X86II::MRMSrcMem: {
1772 unsigned FirstMemOp = CurOp + 1;
1773
1774 if (IsND) // Skip new data destination
1775 CurOp++;
1776
1777 if (HasEVEX_K) // Skip writemask
1778 ++FirstMemOp;
1779
1780 if (HasVEX_4V)
1781 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1782
1783 emitByte(BaseOpcode, CB);
1784
1785 bool ForceSIB = (Form == X86II::MRMSrcMemFSIB);
1786 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
1787 TSFlags, Kind, StartByte, CB, Fixups, STI, ForceSIB);
1788 CurOp = FirstMemOp + X86::AddrNumOperands;
1789 if (HasVEX_I8Reg)
1790 I8RegNum = getX86RegEncoding(MI, CurOp++);
1791 break;
1792 }
1793 case X86II::MRMSrcMem4VOp3: {
1794 unsigned FirstMemOp = CurOp + 1;
1795
1796 emitByte(BaseOpcode, CB);
1797
1798 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
1799 TSFlags, Kind, StartByte, CB, Fixups, STI);
1800 CurOp = FirstMemOp + X86::AddrNumOperands;
1801 ++CurOp; // Encoded in VEX.VVVV.
1802 break;
1803 }
1804 case X86II::MRMSrcMemOp4: {
1805 unsigned FirstMemOp = CurOp + 1;
1806
1807 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1808
1809 // Capture second register source (encoded in Imm[7:4])
1810 assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1811 I8RegNum = getX86RegEncoding(MI, FirstMemOp++);
1812
1813 emitByte(BaseOpcode, CB);
1814
1815 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
1816 TSFlags, Kind, StartByte, CB, Fixups, STI);
1817 CurOp = FirstMemOp + X86::AddrNumOperands;
1818 break;
1819 }
1820 case X86II::MRMSrcMemCC: {
1821 if (IsND) // Skip new data destination
1822 ++CurOp;
1823 unsigned RegOp = CurOp++;
1824 unsigned FirstMemOp = CurOp;
1825 CurOp = FirstMemOp + X86::AddrNumOperands;
1826
1827 unsigned CC = MI.getOperand(CurOp++).getImm();
1828 emitByte(BaseOpcode + CC, CB);
1829
1830 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)),
1831 TSFlags, Kind, StartByte, CB, Fixups, STI);
1832 break;
1833 }
1834
1835 case X86II::MRMXrCC: {
1836 unsigned RegOp = CurOp++;
1837
1838 unsigned CC = MI.getOperand(CurOp++).getImm();
1839 emitByte(BaseOpcode + CC, CB);
1840 emitRegModRMByte(MI.getOperand(RegOp), 0, CB);
1841 break;
1842 }
1843
1844 case X86II::MRMXr:
1845 case X86II::MRM0r:
1846 case X86II::MRM1r:
1847 case X86II::MRM2r:
1848 case X86II::MRM3r:
1849 case X86II::MRM4r:
1850 case X86II::MRM5r:
1851 case X86II::MRM6r:
1852 case X86II::MRM7r:
1853 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1854 ++CurOp;
1855 if (HasEVEX_K) // Skip writemask
1856 ++CurOp;
1857 emitByte(BaseOpcode, CB);
1858 emitRegModRMByte(MI.getOperand(CurOp++),
1859 (Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, CB);
1860 break;
1861 case X86II::MRMr0:
1862 emitByte(BaseOpcode, CB);
1863 emitByte(modRMByte(3, getX86RegNum(MI.getOperand(CurOp++)), 0), CB);
1864 break;
1865
1866 case X86II::MRMXmCC: {
1867 unsigned FirstMemOp = CurOp;
1868 CurOp = FirstMemOp + X86::AddrNumOperands;
1869
1870 unsigned CC = MI.getOperand(CurOp++).getImm();
1871 emitByte(BaseOpcode + CC, CB);
1872
1873 emitMemModRMByte(MI, FirstMemOp, 0, TSFlags, Kind, StartByte, CB, Fixups,
1874 STI);
1875 break;
1876 }
1877
1878 case X86II::MRMXm:
1879 case X86II::MRM0m:
1880 case X86II::MRM1m:
1881 case X86II::MRM2m:
1882 case X86II::MRM3m:
1883 case X86II::MRM4m:
1884 case X86II::MRM5m:
1885 case X86II::MRM6m:
1886 case X86II::MRM7m:
1887 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1888 ++CurOp;
1889 if (HasEVEX_K) // Skip writemask
1890 ++CurOp;
1891 emitByte(BaseOpcode, CB);
1892 emitMemModRMByte(MI, CurOp,
1893 (Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags,
1894 Kind, StartByte, CB, Fixups, STI);
1895 CurOp += X86::AddrNumOperands;
1896 break;
1897
1898 case X86II::MRM0X:
1899 case X86II::MRM1X:
1900 case X86II::MRM2X:
1901 case X86II::MRM3X:
1902 case X86II::MRM4X:
1903 case X86II::MRM5X:
1904 case X86II::MRM6X:
1905 case X86II::MRM7X:
1906 emitByte(BaseOpcode, CB);
1907 emitByte(0xC0 + ((Form - X86II::MRM0X) << 3), CB);
1908 break;
1909
1910 case X86II::MRM_C0:
1911 case X86II::MRM_C1:
1912 case X86II::MRM_C2:
1913 case X86II::MRM_C3:
1914 case X86II::MRM_C4:
1915 case X86II::MRM_C5:
1916 case X86II::MRM_C6:
1917 case X86II::MRM_C7:
1918 case X86II::MRM_C8:
1919 case X86II::MRM_C9:
1920 case X86II::MRM_CA:
1921 case X86II::MRM_CB:
1922 case X86II::MRM_CC:
1923 case X86II::MRM_CD:
1924 case X86II::MRM_CE:
1925 case X86II::MRM_CF:
1926 case X86II::MRM_D0:
1927 case X86II::MRM_D1:
1928 case X86II::MRM_D2:
1929 case X86II::MRM_D3:
1930 case X86II::MRM_D4:
1931 case X86II::MRM_D5:
1932 case X86II::MRM_D6:
1933 case X86II::MRM_D7:
1934 case X86II::MRM_D8:
1935 case X86II::MRM_D9:
1936 case X86II::MRM_DA:
1937 case X86II::MRM_DB:
1938 case X86II::MRM_DC:
1939 case X86II::MRM_DD:
1940 case X86II::MRM_DE:
1941 case X86II::MRM_DF:
1942 case X86II::MRM_E0:
1943 case X86II::MRM_E1:
1944 case X86II::MRM_E2:
1945 case X86II::MRM_E3:
1946 case X86II::MRM_E4:
1947 case X86II::MRM_E5:
1948 case X86II::MRM_E6:
1949 case X86II::MRM_E7:
1950 case X86II::MRM_E8:
1951 case X86II::MRM_E9:
1952 case X86II::MRM_EA:
1953 case X86II::MRM_EB:
1954 case X86II::MRM_EC:
1955 case X86II::MRM_ED:
1956 case X86II::MRM_EE:
1957 case X86II::MRM_EF:
1958 case X86II::MRM_F0:
1959 case X86II::MRM_F1:
1960 case X86II::MRM_F2:
1961 case X86II::MRM_F3:
1962 case X86II::MRM_F4:
1963 case X86II::MRM_F5:
1964 case X86II::MRM_F6:
1965 case X86II::MRM_F7:
1966 case X86II::MRM_F8:
1967 case X86II::MRM_F9:
1968 case X86II::MRM_FA:
1969 case X86II::MRM_FB:
1970 case X86II::MRM_FC:
1971 case X86II::MRM_FD:
1972 case X86II::MRM_FE:
1973 case X86II::MRM_FF:
1974 emitByte(BaseOpcode, CB);
1975 emitByte(0xC0 + Form - X86II::MRM_C0, CB);
1976 break;
1977 }
1978
1979 if (HasVEX_I8Reg) {
1980 // The last source register of a 4 operand instruction in AVX is encoded
1981 // in bits[7:4] of a immediate byte.
1982 assert(I8RegNum < 16 && "Register encoding out of range");
1983 I8RegNum <<= 4;
1984 if (CurOp != NumOps) {
1985 unsigned Val = MI.getOperand(CurOp++).getImm();
1986 assert(Val < 16 && "Immediate operand value out of range");
1987 I8RegNum |= Val;
1988 }
1989 emitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1,
1990 StartByte, CB, Fixups);
1991 } else {
1992 // If there is a remaining operand, it must be a trailing immediate. Emit it
1993 // according to the right size for the instruction. Some instructions
1994 // (SSE4a extrq and insertq) have two trailing immediates.
1995
1996 // Skip two trainling conditional operands encoded in EVEX prefix
1997 unsigned RemaningOps = NumOps - CurOp - 2 * HasTwoConditionalOps;
1998 while (RemaningOps) {
1999 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
2000 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
2001 StartByte, CB, Fixups);
2002 --RemaningOps;
2003 }
2004 CurOp += 2 * HasTwoConditionalOps;
2005 }
2006
2007 if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
2008 emitByte(X86II::getBaseOpcodeFor(TSFlags), CB);
2009
2010 if (CB.size() - StartByte > 15)
2011 Ctx.reportError(MI.getLoc(), "instruction length exceeds the limit of 15");
2012#ifndef NDEBUG
2013 // FIXME: Verify.
2014 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
2015 errs() << "Cannot encode all operands of: ";
2016 MI.dump();
2017 errs() << '\n';
2018 abort();
2019 }
2020#endif
2021}
2022
2024 MCContext &Ctx) {
2025 return new X86MCCodeEmitter(MCII, Ctx);
2026}
unsigned const MachineRegisterInfo * MRI
uint64_t Size
Symbol * Sym
Definition: ELF_riscv.cpp:479
static bool isPCRel(unsigned Kind)
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
#define R2(n)
if(auto Err=PB.parsePassPipeline(MPM, Passes)) return wrap(std MPM run * Mod
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static MCFixupKind getImmFixupKind(uint64_t TSFlags)
static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII)
static GlobalOffsetTableExprKind startsWithGlobalOffsetTable(const MCExpr *Expr)
Check if this expression starts with GLOBAL_OFFSET_TABLE and if it is of the form GLOBAL_OFFSET_TABLE...
static uint8_t modRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM)
static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset)
Determine if this immediate can fit in a disp8 or a compressed disp8 for EVEX instructions.
GlobalOffsetTableExprKind
@ GOT_Normal
@ GOT_None
@ GOT_SymDiff
static void emitConstant(uint64_t Val, unsigned Size, SmallVectorImpl< char > &CB)
static bool hasSecRelSymbolRef(const MCExpr *Expr)
Value * RHS
This class represents an Operation in the Expression.
Binary assembler expressions.
Definition: MCExpr.h:488
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:635
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:638
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:532
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:193
Context object for machine code objects.
Definition: MCContext.h:83
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:39
@ Binary
Binary expressions.
Definition: MCExpr.h:37
ExprKind getKind() const
Definition: MCExpr.h:78
static MCFixupKind getKindForSize(unsigned Size, bool IsPCRel)
Return the generic fixup kind for a value with the given size.
Definition: MCFixup.h:109
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
int64_t getImm() const
Definition: MCInst.h:80
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
bool isImm() const
Definition: MCInst.h:62
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
const MCExpr * getExpr() const
Definition: MCInst.h:114
bool isExpr() const
Definition: MCInst.h:65
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:188
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:205
void dump() const
Definition: Pass.cpp:136
Represents a location in source code.
Definition: SMLoc.h:23
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
bool isX32() const
Tests whether the target is X32.
Definition: Triple.h:1037
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ SS
Definition: X86.h:211
Reg
All possible values of the reg field in the ModR/M byte.
bool hasImm(uint64_t TSFlags)
Definition: X86BaseInfo.h:897
bool hasNewDataDest(uint64_t TSFlags)
Definition: X86BaseInfo.h:1001
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:1308
bool needSIB(unsigned BaseReg, unsigned IndexReg, bool In64BitMode)
Definition: X86BaseInfo.h:1324
bool isPseudo(uint64_t TSFlags)
Definition: X86BaseInfo.h:887
bool isImmPCRel(uint64_t TSFlags)
Definition: X86BaseInfo.h:923
unsigned getSizeOfImm(uint64_t TSFlags)
Decode the "size of immediate" field from the TSFlags field of the specified instruction.
Definition: X86BaseInfo.h:901
uint8_t getBaseOpcodeFor(uint64_t TSFlags)
Definition: X86BaseInfo.h:893
bool isApxExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1186
int getMemoryOperandNo(uint64_t TSFlags)
Definition: X86BaseInfo.h:1011
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
Definition: X86BaseInfo.h:968
@ MRM0X
MRM0X-MRM7X - Instructions that operate that have mod=11 and an opcode but ignore r/m.
Definition: X86BaseInfo.h:618
@ RawFrm
Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode val...
Definition: X86BaseInfo.h:502
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
Definition: X86BaseInfo.h:518
@ EVEX
EVEX - Specifies that this instruction use EVEX form which provides syntax support up to 32 512-bit r...
Definition: X86BaseInfo.h:825
@ ExplicitREX2Prefix
For instructions that require REX2 prefix even if EGPR is not used.
Definition: X86BaseInfo.h:863
@ MRMSrcMemCC
MRMSrcMemCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
Definition: X86BaseInfo.h:566
@ MRM_C0
MRM_XX (XX: C0-FF)- A mod/rm byte of exactly 0xXX.
Definition: X86BaseInfo.h:627
@ RawFrmDst
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI.
Definition: X86BaseInfo.h:514
@ MRMDestMem4VOp3CC
MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM byte to specify a destinat...
Definition: X86BaseInfo.h:545
@ AddCCFrm
AddCCFrm - This form is used for Jcc that encode the condition code in the lower 4 bits of the opcode...
Definition: X86BaseInfo.h:530
@ T_MAP4
MAP4, MAP5, MAP6, MAP7 - Prefix after the 0x0F prefix.
Definition: X86BaseInfo.h:753
@ PrefixByte
PrefixByte - This form is used for instructions that represent a prefix byte like data16 or rep.
Definition: X86BaseInfo.h:533
@ MRMr0
Instructions operate on a register Reg/Opcode operand not the r/m field.
Definition: X86BaseInfo.h:547
@ MRMXm
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
Definition: X86BaseInfo.h:573
@ MRM0r
MRM0r-MRM7r - Instructions that operate on a register r/m operand and use reg field to hold extended ...
Definition: X86BaseInfo.h:608
@ MRMDestMemFSIB
MRMDestMem - But force to use the SIB field.
Definition: X86BaseInfo.h:551
@ AddRegFrm
AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand a...
Definition: X86BaseInfo.h:505
@ VEX
VEX - encoding using 0xC4/0xC5.
Definition: X86BaseInfo.h:818
@ RawFrmImm8
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition: X86BaseInfo.h:522
@ TB
TB - TwoByte - Set if this instruction has a two byte opcode, which starts with a 0x0F byte before th...
Definition: X86BaseInfo.h:735
@ XOP
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:820
@ MRMXr
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
Definition: X86BaseInfo.h:605
@ MRMSrcMem4VOp3
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX....
Definition: X86BaseInfo.h:560
@ XOP8
XOP8 - Prefix to include use of imm byte.
Definition: X86BaseInfo.h:740
@ MRMDestRegCC
MRMDestRegCC - This form is used for the cfcmov instructions, which use the Mod/RM byte to specify th...
Definition: X86BaseInfo.h:537
@ PD
PD - Prefix code for packed double precision vector floating point operations performed in the SSE re...
Definition: X86BaseInfo.h:721
@ MRMDestMem
MRMDestMem - This form is used for instructions that use the Mod/RM byte to specify a destination,...
Definition: X86BaseInfo.h:554
@ MRMSrcMemFSIB
MRMSrcMem - But force to use the SIB field.
Definition: X86BaseInfo.h:549
@ MRMSrcRegOp4
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:595
@ MRMXrCC
MRMXCCr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
Definition: X86BaseInfo.h:602
@ T8
T8, TA - Prefix after the 0x0F prefix.
Definition: X86BaseInfo.h:737
@ MRMDestMemCC
MRMDestMemCC - This form is used for the cfcmov instructions, which use the Mod/RM byte to specify th...
Definition: X86BaseInfo.h:541
@ XOP9
XOP9 - Prefix to exclude use of imm byte.
Definition: X86BaseInfo.h:742
@ MRMXmCC
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
Definition: X86BaseInfo.h:570
@ RawFrmImm16
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition: X86BaseInfo.h:527
@ MRMSrcReg
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition: X86BaseInfo.h:589
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:511
@ MRMDestReg
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination,...
Definition: X86BaseInfo.h:586
@ MRMSrcMem
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition: X86BaseInfo.h:557
@ MRMSrcMemOp4
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:563
@ Pseudo
PseudoFrm - This represents an instruction that is a pseudo instruction or one that has not been impl...
Definition: X86BaseInfo.h:499
@ CD8_Scale_Shift
The scaling factor for the AVX512's 8-bit compressed displacement.
Definition: X86BaseInfo.h:852
@ MRMSrcRegCC
MRMSrcRegCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
Definition: X86BaseInfo.h:598
@ MRM0m
MRM0m-MRM7m - Instructions that operate on a memory r/m operand and use reg field to hold extended op...
Definition: X86BaseInfo.h:576
@ ThreeDNow
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow!...
Definition: X86BaseInfo.h:751
@ XS
XS, XD - These prefix codes are for single and double precision scalar floating point operations perf...
Definition: X86BaseInfo.h:724
@ ExplicitOpPrefixMask
Definition: X86BaseInfo.h:869
@ XOPA
XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
Definition: X86BaseInfo.h:744
@ MRMSrcReg4VOp3
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX....
Definition: X86BaseInfo.h:592
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition: X86BaseInfo.h:508
bool isImmSigned(uint64_t TSFlags)
Definition: X86BaseInfo.h:943
bool is16BitMemOperand(const MCInst &MI, unsigned Op, const MCSubtargetInfo &STI)
bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, int MemoryOperand, uint64_t TSFlags)
Returns true if this instruction needs an Address-Size override prefix.
void emitPrefix(MCCodeEmitter &MCE, const MCInst &MI, SmallVectorImpl< char > &CB, const MCSubtargetInfo &STI)
@ AddrScaleAmt
Definition: X86BaseInfo.h:30
@ AddrSegmentReg
Definition: X86BaseInfo.h:34
@ AddrIndexReg
Definition: X86BaseInfo.h:31
@ AddrNumOperands
Definition: X86BaseInfo.h:36
@ IP_HAS_NOTRACK
Definition: X86BaseInfo.h:58
@ IP_USE_DISP8
Definition: X86BaseInfo.h:65
@ IP_HAS_AD_SIZE
Definition: X86BaseInfo.h:54
@ IP_HAS_REPEAT
Definition: X86BaseInfo.h:56
@ IP_USE_DISP32
Definition: X86BaseInfo.h:66
@ IP_HAS_REPEAT_NE
Definition: X86BaseInfo.h:55
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)
Given a segment register, return the encoding of the segment override prefix for it.
Definition: X86BaseInfo.h:332
@ reloc_global_offset_table8
Definition: X86FixupKinds.h:31
@ reloc_signed_4byte_relax
Definition: X86FixupKinds.h:26
@ reloc_branch_4byte_pcrel
Definition: X86FixupKinds.h:32
@ reloc_riprel_4byte_relax
Definition: X86FixupKinds.h:19
@ reloc_signed_4byte
Definition: X86FixupKinds.h:23
@ reloc_riprel_4byte_relax_rex
Definition: X86FixupKinds.h:21
@ reloc_global_offset_table
Definition: X86FixupKinds.h:28
@ reloc_riprel_4byte_movq_load
Definition: X86FixupKinds.h:18
@ reloc_riprel_4byte
Definition: X86FixupKinds.h:17
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:291
@ None
Definition: CodeGenData.h:101
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
@ FK_PCRel_2
A two-byte pc relative fixup.
Definition: MCFixup.h:29
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:42
@ FK_PCRel_1
A one-byte pc relative fixup.
Definition: MCFixup.h:28
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
@ Ref
The access may reference the value stored in memory.
Description of the encoding of one expression Op.