LLVM  8.0.0svn
Host.cpp
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1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the operating system Host concept.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/Support/Host.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/Config/llvm-config.h"
22 #include "llvm/Support/Debug.h"
26 #include <assert.h>
27 #include <string.h>
28 
29 // Include the platform-specific parts of this class.
30 #ifdef LLVM_ON_UNIX
31 #include "Unix/Host.inc"
32 #endif
33 #ifdef _WIN32
34 #include "Windows/Host.inc"
35 #endif
36 #ifdef _MSC_VER
37 #include <intrin.h>
38 #endif
39 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
40 #include <mach/host_info.h>
41 #include <mach/mach.h>
42 #include <mach/mach_host.h>
43 #include <mach/machine.h>
44 #endif
45 
46 #define DEBUG_TYPE "host-detection"
47 
48 //===----------------------------------------------------------------------===//
49 //
50 // Implementations of the CPU detection routines
51 //
52 //===----------------------------------------------------------------------===//
53 
54 using namespace llvm;
55 
56 static std::unique_ptr<llvm::MemoryBuffer>
59  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
60  if (std::error_code EC = Text.getError()) {
61  llvm::errs() << "Can't read "
62  << "/proc/cpuinfo: " << EC.message() << "\n";
63  return nullptr;
64  }
65  return std::move(*Text);
66 }
67 
69  // Access to the Processor Version Register (PVR) on PowerPC is privileged,
70  // and so we must use an operating-system interface to determine the current
71  // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
72  const char *generic = "generic";
73 
74  // The cpu line is second (after the 'processor: 0' line), so if this
75  // buffer is too small then something has changed (or is wrong).
76  StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
77  StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
78 
79  StringRef::const_iterator CIP = CPUInfoStart;
80 
81  StringRef::const_iterator CPUStart = 0;
82  size_t CPULen = 0;
83 
84  // We need to find the first line which starts with cpu, spaces, and a colon.
85  // After the colon, there may be some additional spaces and then the cpu type.
86  while (CIP < CPUInfoEnd && CPUStart == 0) {
87  if (CIP < CPUInfoEnd && *CIP == '\n')
88  ++CIP;
89 
90  if (CIP < CPUInfoEnd && *CIP == 'c') {
91  ++CIP;
92  if (CIP < CPUInfoEnd && *CIP == 'p') {
93  ++CIP;
94  if (CIP < CPUInfoEnd && *CIP == 'u') {
95  ++CIP;
96  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
97  ++CIP;
98 
99  if (CIP < CPUInfoEnd && *CIP == ':') {
100  ++CIP;
101  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
102  ++CIP;
103 
104  if (CIP < CPUInfoEnd) {
105  CPUStart = CIP;
106  while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
107  *CIP != ',' && *CIP != '\n'))
108  ++CIP;
109  CPULen = CIP - CPUStart;
110  }
111  }
112  }
113  }
114  }
115 
116  if (CPUStart == 0)
117  while (CIP < CPUInfoEnd && *CIP != '\n')
118  ++CIP;
119  }
120 
121  if (CPUStart == 0)
122  return generic;
123 
124  return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
125  .Case("604e", "604e")
126  .Case("604", "604")
127  .Case("7400", "7400")
128  .Case("7410", "7400")
129  .Case("7447", "7400")
130  .Case("7455", "7450")
131  .Case("G4", "g4")
132  .Case("POWER4", "970")
133  .Case("PPC970FX", "970")
134  .Case("PPC970MP", "970")
135  .Case("G5", "g5")
136  .Case("POWER5", "g5")
137  .Case("A2", "a2")
138  .Case("POWER6", "pwr6")
139  .Case("POWER7", "pwr7")
140  .Case("POWER8", "pwr8")
141  .Case("POWER8E", "pwr8")
142  .Case("POWER8NVL", "pwr8")
143  .Case("POWER9", "pwr9")
144  .Default(generic);
145 }
146 
148  // The cpuid register on arm is not accessible from user space. On Linux,
149  // it is exposed through the /proc/cpuinfo file.
150 
151  // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
152  // in all cases.
154  ProcCpuinfoContent.split(Lines, "\n");
155 
156  // Look for the CPU implementer line.
157  StringRef Implementer;
158  StringRef Hardware;
159  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
160  if (Lines[I].startswith("CPU implementer"))
161  Implementer = Lines[I].substr(15).ltrim("\t :");
162  if (Lines[I].startswith("Hardware"))
163  Hardware = Lines[I].substr(8).ltrim("\t :");
164  }
165 
166  if (Implementer == "0x41") { // ARM Ltd.
167  // MSM8992/8994 may give cpu part for the core that the kernel is running on,
168  // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
169  if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
170  return "cortex-a53";
171 
172 
173  // Look for the CPU part line.
174  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
175  if (Lines[I].startswith("CPU part"))
176  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
177  // values correspond to the "Part number" in the CP15/c0 register. The
178  // contents are specified in the various processor manuals.
179  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
180  .Case("0x926", "arm926ej-s")
181  .Case("0xb02", "mpcore")
182  .Case("0xb36", "arm1136j-s")
183  .Case("0xb56", "arm1156t2-s")
184  .Case("0xb76", "arm1176jz-s")
185  .Case("0xc08", "cortex-a8")
186  .Case("0xc09", "cortex-a9")
187  .Case("0xc0f", "cortex-a15")
188  .Case("0xc20", "cortex-m0")
189  .Case("0xc23", "cortex-m3")
190  .Case("0xc24", "cortex-m4")
191  .Case("0xd04", "cortex-a35")
192  .Case("0xd03", "cortex-a53")
193  .Case("0xd07", "cortex-a57")
194  .Case("0xd08", "cortex-a72")
195  .Case("0xd09", "cortex-a73")
196  .Default("generic");
197  }
198 
199  if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
200  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
201  if (Lines[I].startswith("CPU part")) {
202  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
203  .Case("0x516", "thunderx2t99")
204  .Case("0x0516", "thunderx2t99")
205  .Case("0xaf", "thunderx2t99")
206  .Case("0x0af", "thunderx2t99")
207  .Case("0xa1", "thunderxt88")
208  .Case("0x0a1", "thunderxt88")
209  .Default("generic");
210  }
211  }
212  }
213 
214  if (Implementer == "0x48") // HiSilicon Technologies, Inc.
215  // Look for the CPU part line.
216  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
217  if (Lines[I].startswith("CPU part"))
218  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
219  // values correspond to the "Part number" in the CP15/c0 register. The
220  // contents are specified in the various processor manuals.
221  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
222  .Case("0xd01", "tsv110")
223  .Default("generic");
224 
225  if (Implementer == "0x51") // Qualcomm Technologies, Inc.
226  // Look for the CPU part line.
227  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
228  if (Lines[I].startswith("CPU part"))
229  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
230  // values correspond to the "Part number" in the CP15/c0 register. The
231  // contents are specified in the various processor manuals.
232  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
233  .Case("0x06f", "krait") // APQ8064
234  .Case("0x201", "kryo")
235  .Case("0x205", "kryo")
236  .Case("0x211", "kryo")
237  .Case("0x800", "cortex-a73")
238  .Case("0x801", "cortex-a73")
239  .Case("0xc00", "falkor")
240  .Case("0xc01", "saphira")
241  .Default("generic");
242 
243  if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
244  // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
245  // any predictive pattern across variants and parts.
246  unsigned Variant = 0, Part = 0;
247 
248  // Look for the CPU variant line, whose value is a 1 digit hexadecimal
249  // number, corresponding to the Variant bits in the CP15/C0 register.
250  for (auto I : Lines)
251  if (I.consume_front("CPU variant"))
252  I.ltrim("\t :").getAsInteger(0, Variant);
253 
254  // Look for the CPU part line, whose value is a 3 digit hexadecimal
255  // number, corresponding to the PartNum bits in the CP15/C0 register.
256  for (auto I : Lines)
257  if (I.consume_front("CPU part"))
258  I.ltrim("\t :").getAsInteger(0, Part);
259 
260  unsigned Exynos = (Variant << 12) | Part;
261  switch (Exynos) {
262  default:
263  // Default by falling through to Exynos M1.
265 
266  case 0x1001:
267  return "exynos-m1";
268 
269  case 0x4001:
270  return "exynos-m2";
271  }
272  }
273 
274  return "generic";
275 }
276 
278  // STIDP is a privileged operation, so use /proc/cpuinfo instead.
279 
280  // The "processor 0:" line comes after a fair amount of other information,
281  // including a cache breakdown, but this should be plenty.
283  ProcCpuinfoContent.split(Lines, "\n");
284 
285  // Look for the CPU features.
286  SmallVector<StringRef, 32> CPUFeatures;
287  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
288  if (Lines[I].startswith("features")) {
289  size_t Pos = Lines[I].find(":");
290  if (Pos != StringRef::npos) {
291  Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
292  break;
293  }
294  }
295 
296  // We need to check for the presence of vector support independently of
297  // the machine type, since we may only use the vector register set when
298  // supported by the kernel (and hypervisor).
299  bool HaveVectorSupport = false;
300  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
301  if (CPUFeatures[I] == "vx")
302  HaveVectorSupport = true;
303  }
304 
305  // Now check the processor machine type.
306  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
307  if (Lines[I].startswith("processor ")) {
308  size_t Pos = Lines[I].find("machine = ");
309  if (Pos != StringRef::npos) {
310  Pos += sizeof("machine = ") - 1;
311  unsigned int Id;
312  if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
313  if (Id >= 3906 && HaveVectorSupport)
314  return "z14";
315  if (Id >= 2964 && HaveVectorSupport)
316  return "z13";
317  if (Id >= 2827)
318  return "zEC12";
319  if (Id >= 2817)
320  return "z196";
321  }
322  }
323  break;
324  }
325  }
326 
327  return "generic";
328 }
329 
331 #if !defined(__linux__) || !defined(__x86_64__)
332  return "generic";
333 #else
334  uint8_t insns[40] __attribute__ ((aligned (8))) =
335  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
336  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
337  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
338  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
339  /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
340  0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
341  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
342  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
343  /* BPF_EXIT_INSN() */
344  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
345 
346  struct bpf_prog_load_attr {
347  uint32_t prog_type;
348  uint32_t insn_cnt;
349  uint64_t insns;
350  uint64_t license;
351  uint32_t log_level;
352  uint32_t log_size;
353  uint64_t log_buf;
354  uint32_t kern_version;
355  uint32_t prog_flags;
356  } attr = {};
357  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
358  attr.insn_cnt = 5;
359  attr.insns = (uint64_t)insns;
360  attr.license = (uint64_t)"DUMMY";
361 
362  int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
363  if (fd >= 0) {
364  close(fd);
365  return "v2";
366  }
367  return "v1";
368 #endif
369 }
370 
371 #if defined(__i386__) || defined(_M_IX86) || \
372  defined(__x86_64__) || defined(_M_X64)
373 
374 enum VendorSignatures {
375  SIG_INTEL = 0x756e6547 /* Genu */,
376  SIG_AMD = 0x68747541 /* Auth */
377 };
378 
379 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
380 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
381 // support. Consequently, for i386, the presence of CPUID is checked first
382 // via the corresponding eflags bit.
383 // Removal of cpuid.h header motivated by PR30384
384 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
385 // or test-suite, but are used in external projects e.g. libstdcxx
386 static bool isCpuIdSupported() {
387 #if defined(__GNUC__) || defined(__clang__)
388 #if defined(__i386__)
389  int __cpuid_supported;
390  __asm__(" pushfl\n"
391  " popl %%eax\n"
392  " movl %%eax,%%ecx\n"
393  " xorl $0x00200000,%%eax\n"
394  " pushl %%eax\n"
395  " popfl\n"
396  " pushfl\n"
397  " popl %%eax\n"
398  " movl $0,%0\n"
399  " cmpl %%eax,%%ecx\n"
400  " je 1f\n"
401  " movl $1,%0\n"
402  "1:"
403  : "=r"(__cpuid_supported)
404  :
405  : "eax", "ecx");
406  if (!__cpuid_supported)
407  return false;
408 #endif
409  return true;
410 #endif
411  return true;
412 }
413 
414 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
415 /// the specified arguments. If we can't run cpuid on the host, return true.
416 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
417  unsigned *rECX, unsigned *rEDX) {
418 #if defined(__GNUC__) || defined(__clang__)
419 #if defined(__x86_64__)
420  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
421  // FIXME: should we save this for Clang?
422  __asm__("movq\t%%rbx, %%rsi\n\t"
423  "cpuid\n\t"
424  "xchgq\t%%rbx, %%rsi\n\t"
425  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
426  : "a"(value));
427  return false;
428 #elif defined(__i386__)
429  __asm__("movl\t%%ebx, %%esi\n\t"
430  "cpuid\n\t"
431  "xchgl\t%%ebx, %%esi\n\t"
432  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
433  : "a"(value));
434  return false;
435 #else
436  return true;
437 #endif
438 #elif defined(_MSC_VER)
439  // The MSVC intrinsic is portable across x86 and x64.
440  int registers[4];
441  __cpuid(registers, value);
442  *rEAX = registers[0];
443  *rEBX = registers[1];
444  *rECX = registers[2];
445  *rEDX = registers[3];
446  return false;
447 #else
448  return true;
449 #endif
450 }
451 
452 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
453 /// the 4 values in the specified arguments. If we can't run cpuid on the host,
454 /// return true.
455 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
456  unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
457  unsigned *rEDX) {
458 #if defined(__GNUC__) || defined(__clang__)
459 #if defined(__x86_64__)
460  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
461  // FIXME: should we save this for Clang?
462  __asm__("movq\t%%rbx, %%rsi\n\t"
463  "cpuid\n\t"
464  "xchgq\t%%rbx, %%rsi\n\t"
465  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
466  : "a"(value), "c"(subleaf));
467  return false;
468 #elif defined(__i386__)
469  __asm__("movl\t%%ebx, %%esi\n\t"
470  "cpuid\n\t"
471  "xchgl\t%%ebx, %%esi\n\t"
472  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
473  : "a"(value), "c"(subleaf));
474  return false;
475 #else
476  return true;
477 #endif
478 #elif defined(_MSC_VER)
479  int registers[4];
480  __cpuidex(registers, value, subleaf);
481  *rEAX = registers[0];
482  *rEBX = registers[1];
483  *rECX = registers[2];
484  *rEDX = registers[3];
485  return false;
486 #else
487  return true;
488 #endif
489 }
490 
491 // Read control register 0 (XCR0). Used to detect features such as AVX.
492 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
493 #if defined(__GNUC__) || defined(__clang__)
494  // Check xgetbv; this uses a .byte sequence instead of the instruction
495  // directly because older assemblers do not include support for xgetbv and
496  // there is no easy way to conditionally compile based on the assembler used.
497  __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
498  return false;
499 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
500  unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
501  *rEAX = Result;
502  *rEDX = Result >> 32;
503  return false;
504 #else
505  return true;
506 #endif
507 }
508 
509 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
510  unsigned *Model) {
511  *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
512  *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
513  if (*Family == 6 || *Family == 0xf) {
514  if (*Family == 0xf)
515  // Examine extended family ID if family ID is F.
516  *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
517  // Examine extended model ID if family ID is 6 or F.
518  *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
519  }
520 }
521 
522 static void
523 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
524  unsigned Brand_id, unsigned Features,
525  unsigned Features2, unsigned Features3,
526  unsigned *Type, unsigned *Subtype) {
527  if (Brand_id != 0)
528  return;
529  switch (Family) {
530  case 3:
531  *Type = X86::INTEL_i386;
532  break;
533  case 4:
534  *Type = X86::INTEL_i486;
535  break;
536  case 5:
537  if (Features & (1 << X86::FEATURE_MMX)) {
538  *Type = X86::INTEL_PENTIUM_MMX;
539  break;
540  }
541  *Type = X86::INTEL_PENTIUM;
542  break;
543  case 6:
544  switch (Model) {
545  case 0x01: // Pentium Pro processor
546  *Type = X86::INTEL_PENTIUM_PRO;
547  break;
548  case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
549  // model 03
550  case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
551  // model 05, and Intel Celeron processor, model 05
552  case 0x06: // Celeron processor, model 06
553  *Type = X86::INTEL_PENTIUM_II;
554  break;
555  case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
556  // processor, model 07
557  case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
558  // model 08, and Celeron processor, model 08
559  case 0x0a: // Pentium III Xeon processor, model 0Ah
560  case 0x0b: // Pentium III processor, model 0Bh
561  *Type = X86::INTEL_PENTIUM_III;
562  break;
563  case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
564  case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
565  // 0Dh. All processors are manufactured using the 90 nm process.
566  case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
567  // Integrated Processor with Intel QuickAssist Technology
568  *Type = X86::INTEL_PENTIUM_M;
569  break;
570  case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
571  // 0Eh. All processors are manufactured using the 65 nm process.
572  *Type = X86::INTEL_CORE_DUO;
573  break; // yonah
574  case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
575  // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
576  // mobile processor, Intel Core 2 Extreme processor, Intel
577  // Pentium Dual-Core processor, Intel Xeon processor, model
578  // 0Fh. All processors are manufactured using the 65 nm process.
579  case 0x16: // Intel Celeron processor model 16h. All processors are
580  // manufactured using the 65 nm process
581  *Type = X86::INTEL_CORE2; // "core2"
582  *Subtype = X86::INTEL_CORE2_65;
583  break;
584  case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
585  // 17h. All processors are manufactured using the 45 nm process.
586  //
587  // 45nm: Penryn , Wolfdale, Yorkfield (XE)
588  case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
589  // the 45 nm process.
590  *Type = X86::INTEL_CORE2; // "penryn"
591  *Subtype = X86::INTEL_CORE2_45;
592  break;
593  case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
594  // processors are manufactured using the 45 nm process.
595  case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
596  // As found in a Summer 2010 model iMac.
597  case 0x1f:
598  case 0x2e: // Nehalem EX
599  *Type = X86::INTEL_COREI7; // "nehalem"
600  *Subtype = X86::INTEL_COREI7_NEHALEM;
601  break;
602  case 0x25: // Intel Core i7, laptop version.
603  case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
604  // processors are manufactured using the 32 nm process.
605  case 0x2f: // Westmere EX
606  *Type = X86::INTEL_COREI7; // "westmere"
607  *Subtype = X86::INTEL_COREI7_WESTMERE;
608  break;
609  case 0x2a: // Intel Core i7 processor. All processors are manufactured
610  // using the 32 nm process.
611  case 0x2d:
612  *Type = X86::INTEL_COREI7; //"sandybridge"
613  *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
614  break;
615  case 0x3a:
616  case 0x3e: // Ivy Bridge EP
617  *Type = X86::INTEL_COREI7; // "ivybridge"
618  *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
619  break;
620 
621  // Haswell:
622  case 0x3c:
623  case 0x3f:
624  case 0x45:
625  case 0x46:
626  *Type = X86::INTEL_COREI7; // "haswell"
627  *Subtype = X86::INTEL_COREI7_HASWELL;
628  break;
629 
630  // Broadwell:
631  case 0x3d:
632  case 0x47:
633  case 0x4f:
634  case 0x56:
635  *Type = X86::INTEL_COREI7; // "broadwell"
636  *Subtype = X86::INTEL_COREI7_BROADWELL;
637  break;
638 
639  // Skylake:
640  case 0x4e: // Skylake mobile
641  case 0x5e: // Skylake desktop
642  case 0x8e: // Kaby Lake mobile
643  case 0x9e: // Kaby Lake desktop
644  *Type = X86::INTEL_COREI7; // "skylake"
645  *Subtype = X86::INTEL_COREI7_SKYLAKE;
646  break;
647 
648  // Skylake Xeon:
649  case 0x55:
650  *Type = X86::INTEL_COREI7;
651  *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
652  break;
653 
654  // Cannonlake:
655  case 0x66:
656  *Type = X86::INTEL_COREI7;
657  *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake"
658  break;
659 
660  case 0x1c: // Most 45 nm Intel Atom processors
661  case 0x26: // 45 nm Atom Lincroft
662  case 0x27: // 32 nm Atom Medfield
663  case 0x35: // 32 nm Atom Midview
664  case 0x36: // 32 nm Atom Midview
665  *Type = X86::INTEL_BONNELL;
666  break; // "bonnell"
667 
668  // Atom Silvermont codes from the Intel software optimization guide.
669  case 0x37:
670  case 0x4a:
671  case 0x4d:
672  case 0x5a:
673  case 0x5d:
674  case 0x4c: // really airmont
675  *Type = X86::INTEL_SILVERMONT;
676  break; // "silvermont"
677  // Goldmont:
678  case 0x5c: // Apollo Lake
679  case 0x5f: // Denverton
680  *Type = X86::INTEL_GOLDMONT;
681  break; // "goldmont"
682  case 0x7a:
683  *Type = X86::INTEL_GOLDMONT_PLUS;
684  break;
685  case 0x57:
686  *Type = X86::INTEL_KNL; // knl
687  break;
688  case 0x85:
689  *Type = X86::INTEL_KNM; // knm
690  break;
691 
692  default: // Unknown family 6 CPU, try to guess.
693  if (Features & (1 << X86::FEATURE_AVX512VBMI2)) {
694  *Type = X86::INTEL_COREI7;
695  *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
696  break;
697  }
698 
699  if (Features & (1 << X86::FEATURE_AVX512VBMI)) {
700  *Type = X86::INTEL_COREI7;
701  *Subtype = X86::INTEL_COREI7_CANNONLAKE;
702  break;
703  }
704 
705  if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) {
706  *Type = X86::INTEL_COREI7;
707  *Subtype = X86::INTEL_COREI7_CASCADELAKE;
708  break;
709  }
710 
711  if (Features & (1 << X86::FEATURE_AVX512VL)) {
712  *Type = X86::INTEL_COREI7;
713  *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
714  break;
715  }
716 
717  if (Features & (1 << X86::FEATURE_AVX512ER)) {
718  *Type = X86::INTEL_KNL; // knl
719  break;
720  }
721 
722  if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) {
723  if (Features3 & (1 << (X86::FEATURE_SHA - 64))) {
724  *Type = X86::INTEL_GOLDMONT;
725  } else {
726  *Type = X86::INTEL_COREI7;
727  *Subtype = X86::INTEL_COREI7_SKYLAKE;
728  }
729  break;
730  }
731  if (Features3 & (1 << (X86::FEATURE_ADX - 64))) {
732  *Type = X86::INTEL_COREI7;
733  *Subtype = X86::INTEL_COREI7_BROADWELL;
734  break;
735  }
736  if (Features & (1 << X86::FEATURE_AVX2)) {
737  *Type = X86::INTEL_COREI7;
738  *Subtype = X86::INTEL_COREI7_HASWELL;
739  break;
740  }
741  if (Features & (1 << X86::FEATURE_AVX)) {
742  *Type = X86::INTEL_COREI7;
743  *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
744  break;
745  }
746  if (Features & (1 << X86::FEATURE_SSE4_2)) {
747  if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) {
748  *Type = X86::INTEL_SILVERMONT;
749  } else {
750  *Type = X86::INTEL_COREI7;
751  *Subtype = X86::INTEL_COREI7_NEHALEM;
752  }
753  break;
754  }
755  if (Features & (1 << X86::FEATURE_SSE4_1)) {
756  *Type = X86::INTEL_CORE2; // "penryn"
757  *Subtype = X86::INTEL_CORE2_45;
758  break;
759  }
760  if (Features & (1 << X86::FEATURE_SSSE3)) {
761  if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) {
762  *Type = X86::INTEL_BONNELL; // "bonnell"
763  } else {
764  *Type = X86::INTEL_CORE2; // "core2"
765  *Subtype = X86::INTEL_CORE2_65;
766  }
767  break;
768  }
769  if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) {
770  *Type = X86::INTEL_CORE2; // "core2"
771  *Subtype = X86::INTEL_CORE2_65;
772  break;
773  }
774  if (Features & (1 << X86::FEATURE_SSE3)) {
775  *Type = X86::INTEL_CORE_DUO;
776  break;
777  }
778  if (Features & (1 << X86::FEATURE_SSE2)) {
779  *Type = X86::INTEL_PENTIUM_M;
780  break;
781  }
782  if (Features & (1 << X86::FEATURE_SSE)) {
783  *Type = X86::INTEL_PENTIUM_III;
784  break;
785  }
786  if (Features & (1 << X86::FEATURE_MMX)) {
787  *Type = X86::INTEL_PENTIUM_II;
788  break;
789  }
790  *Type = X86::INTEL_PENTIUM_PRO;
791  break;
792  }
793  break;
794  case 15: {
795  if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) {
796  *Type = X86::INTEL_NOCONA;
797  break;
798  }
799  if (Features & (1 << X86::FEATURE_SSE3)) {
800  *Type = X86::INTEL_PRESCOTT;
801  break;
802  }
803  *Type = X86::INTEL_PENTIUM_IV;
804  break;
805  }
806  default:
807  break; /*"generic"*/
808  }
809 }
810 
811 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
812  unsigned Features, unsigned *Type,
813  unsigned *Subtype) {
814  // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
815  // appears to be no way to generate the wide variety of AMD-specific targets
816  // from the information returned from CPUID.
817  switch (Family) {
818  case 4:
819  *Type = X86::AMD_i486;
820  break;
821  case 5:
822  *Type = X86::AMDPENTIUM;
823  switch (Model) {
824  case 6:
825  case 7:
826  *Subtype = X86::AMDPENTIUM_K6;
827  break; // "k6"
828  case 8:
829  *Subtype = X86::AMDPENTIUM_K62;
830  break; // "k6-2"
831  case 9:
832  case 13:
833  *Subtype = X86::AMDPENTIUM_K63;
834  break; // "k6-3"
835  case 10:
836  *Subtype = X86::AMDPENTIUM_GEODE;
837  break; // "geode"
838  }
839  break;
840  case 6:
841  if (Features & (1 << X86::FEATURE_SSE)) {
842  *Type = X86::AMD_ATHLON_XP;
843  break; // "athlon-xp"
844  }
845  *Type = X86::AMD_ATHLON;
846  break; // "athlon"
847  case 15:
848  if (Features & (1 << X86::FEATURE_SSE3)) {
849  *Type = X86::AMD_K8SSE3;
850  break; // "k8-sse3"
851  }
852  *Type = X86::AMD_K8;
853  break; // "k8"
854  case 16:
855  *Type = X86::AMDFAM10H; // "amdfam10"
856  switch (Model) {
857  case 2:
858  *Subtype = X86::AMDFAM10H_BARCELONA;
859  break;
860  case 4:
861  *Subtype = X86::AMDFAM10H_SHANGHAI;
862  break;
863  case 8:
864  *Subtype = X86::AMDFAM10H_ISTANBUL;
865  break;
866  }
867  break;
868  case 20:
869  *Type = X86::AMD_BTVER1;
870  break; // "btver1";
871  case 21:
872  *Type = X86::AMDFAM15H;
873  if (Model >= 0x60 && Model <= 0x7f) {
874  *Subtype = X86::AMDFAM15H_BDVER4;
875  break; // "bdver4"; 60h-7Fh: Excavator
876  }
877  if (Model >= 0x30 && Model <= 0x3f) {
878  *Subtype = X86::AMDFAM15H_BDVER3;
879  break; // "bdver3"; 30h-3Fh: Steamroller
880  }
881  if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
882  *Subtype = X86::AMDFAM15H_BDVER2;
883  break; // "bdver2"; 02h, 10h-1Fh: Piledriver
884  }
885  if (Model <= 0x0f) {
886  *Subtype = X86::AMDFAM15H_BDVER1;
887  break; // "bdver1"; 00h-0Fh: Bulldozer
888  }
889  break;
890  case 22:
891  *Type = X86::AMD_BTVER2;
892  break; // "btver2"
893  case 23:
894  *Type = X86::AMDFAM17H;
895  *Subtype = X86::AMDFAM17H_ZNVER1;
896  break;
897  default:
898  break; // "generic"
899  }
900 }
901 
902 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
903  unsigned *FeaturesOut, unsigned *Features2Out,
904  unsigned *Features3Out) {
905  unsigned Features = 0;
906  unsigned Features2 = 0;
907  unsigned Features3 = 0;
908  unsigned EAX, EBX;
909 
910  auto setFeature = [&](unsigned F) {
911  if (F < 32)
912  Features |= 1U << (F & 0x1f);
913  else if (F < 64)
914  Features2 |= 1U << ((F - 32) & 0x1f);
915  else if (F < 96)
916  Features3 |= 1U << ((F - 64) & 0x1f);
917  else
918  llvm_unreachable("Unexpected FeatureBit");
919  };
920 
921  if ((EDX >> 15) & 1)
922  setFeature(X86::FEATURE_CMOV);
923  if ((EDX >> 23) & 1)
924  setFeature(X86::FEATURE_MMX);
925  if ((EDX >> 25) & 1)
926  setFeature(X86::FEATURE_SSE);
927  if ((EDX >> 26) & 1)
928  setFeature(X86::FEATURE_SSE2);
929 
930  if ((ECX >> 0) & 1)
931  setFeature(X86::FEATURE_SSE3);
932  if ((ECX >> 1) & 1)
933  setFeature(X86::FEATURE_PCLMUL);
934  if ((ECX >> 9) & 1)
935  setFeature(X86::FEATURE_SSSE3);
936  if ((ECX >> 12) & 1)
937  setFeature(X86::FEATURE_FMA);
938  if ((ECX >> 19) & 1)
939  setFeature(X86::FEATURE_SSE4_1);
940  if ((ECX >> 20) & 1)
941  setFeature(X86::FEATURE_SSE4_2);
942  if ((ECX >> 23) & 1)
943  setFeature(X86::FEATURE_POPCNT);
944  if ((ECX >> 25) & 1)
945  setFeature(X86::FEATURE_AES);
946 
947  if ((ECX >> 22) & 1)
948  setFeature(X86::FEATURE_MOVBE);
949 
950  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
951  // indicates that the AVX registers will be saved and restored on context
952  // switch, then we have full AVX support.
953  const unsigned AVXBits = (1 << 27) | (1 << 28);
954  bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
955  ((EAX & 0x6) == 0x6);
956  bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
957 
958  if (HasAVX)
959  setFeature(X86::FEATURE_AVX);
960 
961  bool HasLeaf7 =
962  MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
963 
964  if (HasLeaf7 && ((EBX >> 3) & 1))
965  setFeature(X86::FEATURE_BMI);
966  if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
967  setFeature(X86::FEATURE_AVX2);
968  if (HasLeaf7 && ((EBX >> 9) & 1))
969  setFeature(X86::FEATURE_BMI2);
970  if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
971  setFeature(X86::FEATURE_AVX512F);
972  if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
973  setFeature(X86::FEATURE_AVX512DQ);
974  if (HasLeaf7 && ((EBX >> 19) & 1))
975  setFeature(X86::FEATURE_ADX);
976  if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
977  setFeature(X86::FEATURE_AVX512IFMA);
978  if (HasLeaf7 && ((EBX >> 23) & 1))
979  setFeature(X86::FEATURE_CLFLUSHOPT);
980  if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
981  setFeature(X86::FEATURE_AVX512PF);
982  if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
983  setFeature(X86::FEATURE_AVX512ER);
984  if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
985  setFeature(X86::FEATURE_AVX512CD);
986  if (HasLeaf7 && ((EBX >> 29) & 1))
987  setFeature(X86::FEATURE_SHA);
988  if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
989  setFeature(X86::FEATURE_AVX512BW);
990  if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
991  setFeature(X86::FEATURE_AVX512VL);
992 
993  if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
994  setFeature(X86::FEATURE_AVX512VBMI);
995  if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
996  setFeature(X86::FEATURE_AVX512VBMI2);
997  if (HasLeaf7 && ((ECX >> 8) & 1))
998  setFeature(X86::FEATURE_GFNI);
999  if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1000  setFeature(X86::FEATURE_VPCLMULQDQ);
1001  if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1002  setFeature(X86::FEATURE_AVX512VNNI);
1003  if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1004  setFeature(X86::FEATURE_AVX512BITALG);
1005  if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1006  setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1007 
1008  if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1009  setFeature(X86::FEATURE_AVX5124VNNIW);
1010  if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1011  setFeature(X86::FEATURE_AVX5124FMAPS);
1012 
1013  unsigned MaxExtLevel;
1014  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1015 
1016  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1017  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1018  if (HasExtLeaf1 && ((ECX >> 6) & 1))
1019  setFeature(X86::FEATURE_SSE4_A);
1020  if (HasExtLeaf1 && ((ECX >> 11) & 1))
1021  setFeature(X86::FEATURE_XOP);
1022  if (HasExtLeaf1 && ((ECX >> 16) & 1))
1023  setFeature(X86::FEATURE_FMA4);
1024 
1025  if (HasExtLeaf1 && ((EDX >> 29) & 1))
1026  setFeature(X86::FEATURE_EM64T);
1027 
1028  *FeaturesOut = Features;
1029  *Features2Out = Features2;
1030  *Features3Out = Features3;
1031 }
1032 
1034  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1035  unsigned MaxLeaf, Vendor;
1036 
1037 #if defined(__GNUC__) || defined(__clang__)
1038  //FIXME: include cpuid.h from clang or copy __get_cpuid_max here
1039  // and simplify it to not invoke __cpuid (like cpu_model.c in
1040  // compiler-rt/lib/builtins/cpu_model.c?
1041  // Opting for the second option.
1042  if(!isCpuIdSupported())
1043  return "generic";
1044 #endif
1045  if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1)
1046  return "generic";
1047  getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1048 
1049  unsigned Brand_id = EBX & 0xff;
1050  unsigned Family = 0, Model = 0;
1051  unsigned Features = 0, Features2 = 0, Features3 = 0;
1052  detectX86FamilyModel(EAX, &Family, &Model);
1053  getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3);
1054 
1055  unsigned Type = 0;
1056  unsigned Subtype = 0;
1057 
1058  if (Vendor == SIG_INTEL) {
1059  getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
1060  Features2, Features3, &Type, &Subtype);
1061  } else if (Vendor == SIG_AMD) {
1062  getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
1063  }
1064 
1065  // Check subtypes first since those are more specific.
1066 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
1067  if (Subtype == X86::ENUM) \
1068  return ARCHNAME;
1069 #include "llvm/Support/X86TargetParser.def"
1070 
1071  // Now check types.
1072 #define X86_CPU_TYPE(ARCHNAME, ENUM) \
1073  if (Type == X86::ENUM) \
1074  return ARCHNAME;
1075 #include "llvm/Support/X86TargetParser.def"
1076 
1077  return "generic";
1078 }
1079 
1080 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
1082  host_basic_info_data_t hostInfo;
1083  mach_msg_type_number_t infoCount;
1084 
1085  infoCount = HOST_BASIC_INFO_COUNT;
1086  mach_port_t hostPort = mach_host_self();
1087  host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1088  &infoCount);
1089  mach_port_deallocate(mach_task_self(), hostPort);
1090 
1091  if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1092  return "generic";
1093 
1094  switch (hostInfo.cpu_subtype) {
1096  return "601";
1098  return "602";
1100  return "603";
1102  return "603e";
1104  return "603ev";
1106  return "604";
1108  return "604e";
1110  return "620";
1112  return "750";
1114  return "7400";
1116  return "7450";
1118  return "970";
1119  default:;
1120  }
1121 
1122  return "generic";
1123 }
1124 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
1126  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1127  StringRef Content = P ? P->getBuffer() : "";
1128  return detail::getHostCPUNameForPowerPC(Content);
1129 }
1130 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1132  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1133  StringRef Content = P ? P->getBuffer() : "";
1134  return detail::getHostCPUNameForARM(Content);
1135 }
1136 #elif defined(__linux__) && defined(__s390x__)
1138  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1139  StringRef Content = P ? P->getBuffer() : "";
1140  return detail::getHostCPUNameForS390x(Content);
1141 }
1142 #else
1143 StringRef sys::getHostCPUName() { return "generic"; }
1144 #endif
1145 
1146 #if defined(__linux__) && defined(__x86_64__)
1147 // On Linux, the number of physical cores can be computed from /proc/cpuinfo,
1148 // using the number of unique physical/core id pairs. The following
1149 // implementation reads the /proc/cpuinfo format on an x86_64 system.
1150 static int computeHostNumPhysicalCores() {
1151  // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
1152  // mmapped because it appears to have 0 size.
1154  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
1155  if (std::error_code EC = Text.getError()) {
1156  llvm::errs() << "Can't read "
1157  << "/proc/cpuinfo: " << EC.message() << "\n";
1158  return -1;
1159  }
1161  (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
1162  /*KeepEmpty=*/false);
1163  int CurPhysicalId = -1;
1164  int CurCoreId = -1;
1165  SmallSet<std::pair<int, int>, 32> UniqueItems;
1166  for (auto &Line : strs) {
1167  Line = Line.trim();
1168  if (!Line.startswith("physical id") && !Line.startswith("core id"))
1169  continue;
1170  std::pair<StringRef, StringRef> Data = Line.split(':');
1171  auto Name = Data.first.trim();
1172  auto Val = Data.second.trim();
1173  if (Name == "physical id") {
1174  assert(CurPhysicalId == -1 &&
1175  "Expected a core id before seeing another physical id");
1176  Val.getAsInteger(10, CurPhysicalId);
1177  }
1178  if (Name == "core id") {
1179  assert(CurCoreId == -1 &&
1180  "Expected a physical id before seeing another core id");
1181  Val.getAsInteger(10, CurCoreId);
1182  }
1183  if (CurPhysicalId != -1 && CurCoreId != -1) {
1184  UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId));
1185  CurPhysicalId = -1;
1186  CurCoreId = -1;
1187  }
1188  }
1189  return UniqueItems.size();
1190 }
1191 #elif defined(__APPLE__) && defined(__x86_64__)
1192 #include <sys/param.h>
1193 #include <sys/sysctl.h>
1194 
1195 // Gets the number of *physical cores* on the machine.
1196 static int computeHostNumPhysicalCores() {
1197  uint32_t count;
1198  size_t len = sizeof(count);
1199  sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
1200  if (count < 1) {
1201  int nm[2];
1202  nm[0] = CTL_HW;
1203  nm[1] = HW_AVAILCPU;
1204  sysctl(nm, 2, &count, &len, NULL, 0);
1205  if (count < 1)
1206  return -1;
1207  }
1208  return count;
1209 }
1210 #else
1211 // On other systems, return -1 to indicate unknown.
1212 static int computeHostNumPhysicalCores() { return -1; }
1213 #endif
1214 
1216  static int NumCores = computeHostNumPhysicalCores();
1217  return NumCores;
1218 }
1219 
1220 #if defined(__i386__) || defined(_M_IX86) || \
1221  defined(__x86_64__) || defined(_M_X64)
1222 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1223  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1224  unsigned MaxLevel;
1225  union {
1226  unsigned u[3];
1227  char c[12];
1228  } text;
1229 
1230  if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
1231  MaxLevel < 1)
1232  return false;
1233 
1234  getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1235 
1236  Features["cmov"] = (EDX >> 15) & 1;
1237  Features["mmx"] = (EDX >> 23) & 1;
1238  Features["sse"] = (EDX >> 25) & 1;
1239  Features["sse2"] = (EDX >> 26) & 1;
1240 
1241  Features["sse3"] = (ECX >> 0) & 1;
1242  Features["pclmul"] = (ECX >> 1) & 1;
1243  Features["ssse3"] = (ECX >> 9) & 1;
1244  Features["cx16"] = (ECX >> 13) & 1;
1245  Features["sse4.1"] = (ECX >> 19) & 1;
1246  Features["sse4.2"] = (ECX >> 20) & 1;
1247  Features["movbe"] = (ECX >> 22) & 1;
1248  Features["popcnt"] = (ECX >> 23) & 1;
1249  Features["aes"] = (ECX >> 25) & 1;
1250  Features["rdrnd"] = (ECX >> 30) & 1;
1251 
1252  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1253  // indicates that the AVX registers will be saved and restored on context
1254  // switch, then we have full AVX support.
1255  bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
1256  !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
1257  // AVX512 requires additional context to be saved by the OS.
1258  bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1259 
1260  Features["avx"] = HasAVXSave;
1261  Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
1262  // Only enable XSAVE if OS has enabled support for saving YMM state.
1263  Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1264  Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
1265 
1266  unsigned MaxExtLevel;
1267  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1268 
1269  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1270  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1271  Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
1272  Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1273  Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1274  Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1275  Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1276  Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1277  Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1278  Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1279  Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1280 
1281  Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
1282 
1283  // Miscellaneous memory related features, detected by
1284  // using the 0x80000008 leaf of the CPUID instruction
1285  bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1286  !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1287  Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1288  Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1289 
1290  bool HasLeaf7 =
1291  MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1292 
1293  Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1294  Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1295  Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1296  // AVX2 is only supported if we have the OS save support from AVX.
1297  Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
1298  Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1299  Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1300  Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1301  // AVX512 is only supported if the OS supports the context save for it.
1302  Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1303  Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1304  Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1305  Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1306  Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1307  Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1308  Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1309  Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1310  Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1311  Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1312  Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1313  Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1314  Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1315 
1316  Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1);
1317  Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1318  Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1319  Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
1320  Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
1321  Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
1322  Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
1323  Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
1324  Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1325  Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1326  Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1327  Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1328  Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
1329  Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
1330  Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
1331  Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
1332 
1333  // There are two CPUID leafs which information associated with the pconfig
1334  // instruction:
1335  // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1336  // bit of EDX), while the EAX=0x1b leaf returns information on the
1337  // availability of specific pconfig leafs.
1338  // The target feature here only refers to the the first of these two.
1339  // Users might need to check for the availability of specific pconfig
1340  // leaves using cpuid, since that information is ignored while
1341  // detecting features using the "-march=native" flag.
1342  // For more info, see X86 ISA docs.
1343  Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1344 
1345  bool HasLeafD = MaxLevel >= 0xd &&
1346  !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1347 
1348  // Only enable XSAVE if OS has enabled support for saving YMM state.
1349  Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1350  Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1351  Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1352 
1353  bool HasLeaf14 = MaxLevel >= 0x14 &&
1354  !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1355 
1356  Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1357 
1358  return true;
1359 }
1360 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1361 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1362  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1363  if (!P)
1364  return false;
1365 
1367  P->getBuffer().split(Lines, "\n");
1368 
1369  SmallVector<StringRef, 32> CPUFeatures;
1370 
1371  // Look for the CPU features.
1372  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1373  if (Lines[I].startswith("Features")) {
1374  Lines[I].split(CPUFeatures, ' ');
1375  break;
1376  }
1377 
1378 #if defined(__aarch64__)
1379  // Keep track of which crypto features we have seen
1380  enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1381  uint32_t crypto = 0;
1382 #endif
1383 
1384  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1385  StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1386 #if defined(__aarch64__)
1387  .Case("asimd", "neon")
1388  .Case("fp", "fp-armv8")
1389  .Case("crc32", "crc")
1390 #else
1391  .Case("half", "fp16")
1392  .Case("neon", "neon")
1393  .Case("vfpv3", "vfp3")
1394  .Case("vfpv3d16", "d16")
1395  .Case("vfpv4", "vfp4")
1396  .Case("idiva", "hwdiv-arm")
1397  .Case("idivt", "hwdiv")
1398 #endif
1399  .Default("");
1400 
1401 #if defined(__aarch64__)
1402  // We need to check crypto separately since we need all of the crypto
1403  // extensions to enable the subtarget feature
1404  if (CPUFeatures[I] == "aes")
1405  crypto |= CAP_AES;
1406  else if (CPUFeatures[I] == "pmull")
1407  crypto |= CAP_PMULL;
1408  else if (CPUFeatures[I] == "sha1")
1409  crypto |= CAP_SHA1;
1410  else if (CPUFeatures[I] == "sha2")
1411  crypto |= CAP_SHA2;
1412 #endif
1413 
1414  if (LLVMFeatureStr != "")
1415  Features[LLVMFeatureStr] = true;
1416  }
1417 
1418 #if defined(__aarch64__)
1419  // If we have all crypto bits we can add the feature
1420  if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1421  Features["crypto"] = true;
1422 #endif
1423 
1424  return true;
1425 }
1426 #else
1427 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1428 #endif
1429 
1430 std::string sys::getProcessTriple() {
1431  std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1432  Triple PT(Triple::normalize(TargetTripleString));
1433 
1434  if (sizeof(void *) == 8 && PT.isArch32Bit())
1435  PT = PT.get64BitArchVariant();
1436  if (sizeof(void *) == 4 && PT.isArch64Bit())
1437  PT = PT.get32BitArchVariant();
1438 
1439  return PT.str();
1440 }
Represents either an error or a value T.
Definition: ErrorOr.h:57
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
Definition: Host.cpp:57
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
This class represents lattice values for constants.
Definition: AllocatorList.h:24
#define LLVM_FALLTHROUGH
Definition: Compiler.h:86
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
Definition: Host.cpp:68
const FeatureBitset Features
F(f)
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
Definition: Host.cpp:277
int getHostNumPhysicalCores()
Get the number of physical cores (as opposed to logical cores returned from thread::hardware_concurre...
Definition: Host.cpp:1215
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:279
amdgpu Simplify well known AMD library false Value Value const Twine & Name
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(T Value)
Definition: StringSwitch.h:203
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:30
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1278
const std::string & str() const
Definition: Triple.h:359
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
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A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
Definition: Triple.cpp:1286
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Definition: Host.cpp:330
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Definition: Type.h:46
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
std::error_code getError() const
Definition: ErrorOr.h:160
size_type size() const
Definition: SmallSet.h:160
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:181
size_t size() const
Definition: SmallVector.h:53
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
Definition: Host.cpp:1430
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:727
std::string normalize() const
Return the normalized form of this triple&#39;s string.
Definition: Triple.h:283
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:70
iterator begin() const
Definition: StringRef.h:106
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
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static const size_t npos
Definition: StringRef.h:51
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1274
#define I(x, y, z)
Definition: MD5.cpp:58
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
Definition: Host.cpp:147
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
Definition: Triple.cpp:1350
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool getHostCPUFeatures(StringMap< bool > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
Definition: Host.cpp:1427
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:160
iterator end() const
Definition: StringRef.h:108
static int computeHostNumPhysicalCores()
Definition: Host.cpp:1212