LLVM  9.0.0svn
Host.cpp
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1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the operating system Host concept.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Config/llvm-config.h"
21 #include "llvm/Support/Debug.h"
25 #include <assert.h>
26 #include <string.h>
27 
28 // Include the platform-specific parts of this class.
29 #ifdef LLVM_ON_UNIX
30 #include "Unix/Host.inc"
31 #endif
32 #ifdef _WIN32
33 #include "Windows/Host.inc"
34 #endif
35 #ifdef _MSC_VER
36 #include <intrin.h>
37 #endif
38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
39 #include <mach/host_info.h>
40 #include <mach/mach.h>
41 #include <mach/mach_host.h>
42 #include <mach/machine.h>
43 #endif
44 
45 #define DEBUG_TYPE "host-detection"
46 
47 //===----------------------------------------------------------------------===//
48 //
49 // Implementations of the CPU detection routines
50 //
51 //===----------------------------------------------------------------------===//
52 
53 using namespace llvm;
54 
55 static std::unique_ptr<llvm::MemoryBuffer>
58  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
59  if (std::error_code EC = Text.getError()) {
60  llvm::errs() << "Can't read "
61  << "/proc/cpuinfo: " << EC.message() << "\n";
62  return nullptr;
63  }
64  return std::move(*Text);
65 }
66 
68  // Access to the Processor Version Register (PVR) on PowerPC is privileged,
69  // and so we must use an operating-system interface to determine the current
70  // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
71  const char *generic = "generic";
72 
73  // The cpu line is second (after the 'processor: 0' line), so if this
74  // buffer is too small then something has changed (or is wrong).
75  StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
76  StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
77 
78  StringRef::const_iterator CIP = CPUInfoStart;
79 
80  StringRef::const_iterator CPUStart = 0;
81  size_t CPULen = 0;
82 
83  // We need to find the first line which starts with cpu, spaces, and a colon.
84  // After the colon, there may be some additional spaces and then the cpu type.
85  while (CIP < CPUInfoEnd && CPUStart == 0) {
86  if (CIP < CPUInfoEnd && *CIP == '\n')
87  ++CIP;
88 
89  if (CIP < CPUInfoEnd && *CIP == 'c') {
90  ++CIP;
91  if (CIP < CPUInfoEnd && *CIP == 'p') {
92  ++CIP;
93  if (CIP < CPUInfoEnd && *CIP == 'u') {
94  ++CIP;
95  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
96  ++CIP;
97 
98  if (CIP < CPUInfoEnd && *CIP == ':') {
99  ++CIP;
100  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
101  ++CIP;
102 
103  if (CIP < CPUInfoEnd) {
104  CPUStart = CIP;
105  while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
106  *CIP != ',' && *CIP != '\n'))
107  ++CIP;
108  CPULen = CIP - CPUStart;
109  }
110  }
111  }
112  }
113  }
114 
115  if (CPUStart == 0)
116  while (CIP < CPUInfoEnd && *CIP != '\n')
117  ++CIP;
118  }
119 
120  if (CPUStart == 0)
121  return generic;
122 
123  return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
124  .Case("604e", "604e")
125  .Case("604", "604")
126  .Case("7400", "7400")
127  .Case("7410", "7400")
128  .Case("7447", "7400")
129  .Case("7455", "7450")
130  .Case("G4", "g4")
131  .Case("POWER4", "970")
132  .Case("PPC970FX", "970")
133  .Case("PPC970MP", "970")
134  .Case("G5", "g5")
135  .Case("POWER5", "g5")
136  .Case("A2", "a2")
137  .Case("POWER6", "pwr6")
138  .Case("POWER7", "pwr7")
139  .Case("POWER8", "pwr8")
140  .Case("POWER8E", "pwr8")
141  .Case("POWER8NVL", "pwr8")
142  .Case("POWER9", "pwr9")
143  .Default(generic);
144 }
145 
147  // The cpuid register on arm is not accessible from user space. On Linux,
148  // it is exposed through the /proc/cpuinfo file.
149 
150  // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
151  // in all cases.
153  ProcCpuinfoContent.split(Lines, "\n");
154 
155  // Look for the CPU implementer line.
156  StringRef Implementer;
157  StringRef Hardware;
158  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
159  if (Lines[I].startswith("CPU implementer"))
160  Implementer = Lines[I].substr(15).ltrim("\t :");
161  if (Lines[I].startswith("Hardware"))
162  Hardware = Lines[I].substr(8).ltrim("\t :");
163  }
164 
165  if (Implementer == "0x41") { // ARM Ltd.
166  // MSM8992/8994 may give cpu part for the core that the kernel is running on,
167  // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
168  if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
169  return "cortex-a53";
170 
171 
172  // Look for the CPU part line.
173  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
174  if (Lines[I].startswith("CPU part"))
175  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
176  // values correspond to the "Part number" in the CP15/c0 register. The
177  // contents are specified in the various processor manuals.
178  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
179  .Case("0x926", "arm926ej-s")
180  .Case("0xb02", "mpcore")
181  .Case("0xb36", "arm1136j-s")
182  .Case("0xb56", "arm1156t2-s")
183  .Case("0xb76", "arm1176jz-s")
184  .Case("0xc08", "cortex-a8")
185  .Case("0xc09", "cortex-a9")
186  .Case("0xc0f", "cortex-a15")
187  .Case("0xc20", "cortex-m0")
188  .Case("0xc23", "cortex-m3")
189  .Case("0xc24", "cortex-m4")
190  .Case("0xd04", "cortex-a35")
191  .Case("0xd03", "cortex-a53")
192  .Case("0xd07", "cortex-a57")
193  .Case("0xd08", "cortex-a72")
194  .Case("0xd09", "cortex-a73")
195  .Default("generic");
196  }
197 
198  if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
199  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
200  if (Lines[I].startswith("CPU part")) {
201  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
202  .Case("0x516", "thunderx2t99")
203  .Case("0x0516", "thunderx2t99")
204  .Case("0xaf", "thunderx2t99")
205  .Case("0x0af", "thunderx2t99")
206  .Case("0xa1", "thunderxt88")
207  .Case("0x0a1", "thunderxt88")
208  .Default("generic");
209  }
210  }
211  }
212 
213  if (Implementer == "0x48") // HiSilicon Technologies, Inc.
214  // Look for the CPU part line.
215  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
216  if (Lines[I].startswith("CPU part"))
217  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
218  // values correspond to the "Part number" in the CP15/c0 register. The
219  // contents are specified in the various processor manuals.
220  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
221  .Case("0xd01", "tsv110")
222  .Default("generic");
223 
224  if (Implementer == "0x51") // Qualcomm Technologies, Inc.
225  // Look for the CPU part line.
226  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
227  if (Lines[I].startswith("CPU part"))
228  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
229  // values correspond to the "Part number" in the CP15/c0 register. The
230  // contents are specified in the various processor manuals.
231  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
232  .Case("0x06f", "krait") // APQ8064
233  .Case("0x201", "kryo")
234  .Case("0x205", "kryo")
235  .Case("0x211", "kryo")
236  .Case("0x800", "cortex-a73")
237  .Case("0x801", "cortex-a73")
238  .Case("0xc00", "falkor")
239  .Case("0xc01", "saphira")
240  .Default("generic");
241 
242  if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
243  // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
244  // any predictive pattern across variants and parts.
245  unsigned Variant = 0, Part = 0;
246 
247  // Look for the CPU variant line, whose value is a 1 digit hexadecimal
248  // number, corresponding to the Variant bits in the CP15/C0 register.
249  for (auto I : Lines)
250  if (I.consume_front("CPU variant"))
251  I.ltrim("\t :").getAsInteger(0, Variant);
252 
253  // Look for the CPU part line, whose value is a 3 digit hexadecimal
254  // number, corresponding to the PartNum bits in the CP15/C0 register.
255  for (auto I : Lines)
256  if (I.consume_front("CPU part"))
257  I.ltrim("\t :").getAsInteger(0, Part);
258 
259  unsigned Exynos = (Variant << 12) | Part;
260  switch (Exynos) {
261  default:
262  // Default by falling through to Exynos M1.
264 
265  case 0x1001:
266  return "exynos-m1";
267 
268  case 0x4001:
269  return "exynos-m2";
270  }
271  }
272 
273  return "generic";
274 }
275 
277  // STIDP is a privileged operation, so use /proc/cpuinfo instead.
278 
279  // The "processor 0:" line comes after a fair amount of other information,
280  // including a cache breakdown, but this should be plenty.
282  ProcCpuinfoContent.split(Lines, "\n");
283 
284  // Look for the CPU features.
285  SmallVector<StringRef, 32> CPUFeatures;
286  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
287  if (Lines[I].startswith("features")) {
288  size_t Pos = Lines[I].find(":");
289  if (Pos != StringRef::npos) {
290  Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
291  break;
292  }
293  }
294 
295  // We need to check for the presence of vector support independently of
296  // the machine type, since we may only use the vector register set when
297  // supported by the kernel (and hypervisor).
298  bool HaveVectorSupport = false;
299  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
300  if (CPUFeatures[I] == "vx")
301  HaveVectorSupport = true;
302  }
303 
304  // Now check the processor machine type.
305  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
306  if (Lines[I].startswith("processor ")) {
307  size_t Pos = Lines[I].find("machine = ");
308  if (Pos != StringRef::npos) {
309  Pos += sizeof("machine = ") - 1;
310  unsigned int Id;
311  if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
312  if (Id >= 3906 && HaveVectorSupport)
313  return "z14";
314  if (Id >= 2964 && HaveVectorSupport)
315  return "z13";
316  if (Id >= 2827)
317  return "zEC12";
318  if (Id >= 2817)
319  return "z196";
320  }
321  }
322  break;
323  }
324  }
325 
326  return "generic";
327 }
328 
330 #if !defined(__linux__) || !defined(__x86_64__)
331  return "generic";
332 #else
333  uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
334  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
335  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
336  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
337  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
338  /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
339  0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
340  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
341  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
342  /* BPF_EXIT_INSN() */
343  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
344 
345  uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
346  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
347  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
348  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
349  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
350  /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
351  0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
352  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
353  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
354  /* BPF_EXIT_INSN() */
355  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
356 
357  struct bpf_prog_load_attr {
358  uint32_t prog_type;
359  uint32_t insn_cnt;
360  uint64_t insns;
361  uint64_t license;
362  uint32_t log_level;
363  uint32_t log_size;
364  uint64_t log_buf;
365  uint32_t kern_version;
366  uint32_t prog_flags;
367  } attr = {};
368  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
369  attr.insn_cnt = 5;
370  attr.insns = (uint64_t)v3_insns;
371  attr.license = (uint64_t)"DUMMY";
372 
373  int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
374  sizeof(attr));
375  if (fd >= 0) {
376  close(fd);
377  return "v3";
378  }
379 
380  /* Clear the whole attr in case its content changed by syscall. */
381  memset(&attr, 0, sizeof(attr));
382  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
383  attr.insn_cnt = 5;
384  attr.insns = (uint64_t)v2_insns;
385  attr.license = (uint64_t)"DUMMY";
386  fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
387  if (fd >= 0) {
388  close(fd);
389  return "v2";
390  }
391  return "v1";
392 #endif
393 }
394 
395 #if defined(__i386__) || defined(_M_IX86) || \
396  defined(__x86_64__) || defined(_M_X64)
397 
398 enum VendorSignatures {
399  SIG_INTEL = 0x756e6547 /* Genu */,
400  SIG_AMD = 0x68747541 /* Auth */
401 };
402 
403 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
404 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
405 // support. Consequently, for i386, the presence of CPUID is checked first
406 // via the corresponding eflags bit.
407 // Removal of cpuid.h header motivated by PR30384
408 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
409 // or test-suite, but are used in external projects e.g. libstdcxx
410 static bool isCpuIdSupported() {
411 #if defined(__GNUC__) || defined(__clang__)
412 #if defined(__i386__)
413  int __cpuid_supported;
414  __asm__(" pushfl\n"
415  " popl %%eax\n"
416  " movl %%eax,%%ecx\n"
417  " xorl $0x00200000,%%eax\n"
418  " pushl %%eax\n"
419  " popfl\n"
420  " pushfl\n"
421  " popl %%eax\n"
422  " movl $0,%0\n"
423  " cmpl %%eax,%%ecx\n"
424  " je 1f\n"
425  " movl $1,%0\n"
426  "1:"
427  : "=r"(__cpuid_supported)
428  :
429  : "eax", "ecx");
430  if (!__cpuid_supported)
431  return false;
432 #endif
433  return true;
434 #endif
435  return true;
436 }
437 
438 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
439 /// the specified arguments. If we can't run cpuid on the host, return true.
440 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
441  unsigned *rECX, unsigned *rEDX) {
442 #if defined(__GNUC__) || defined(__clang__)
443 #if defined(__x86_64__)
444  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
445  // FIXME: should we save this for Clang?
446  __asm__("movq\t%%rbx, %%rsi\n\t"
447  "cpuid\n\t"
448  "xchgq\t%%rbx, %%rsi\n\t"
449  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
450  : "a"(value));
451  return false;
452 #elif defined(__i386__)
453  __asm__("movl\t%%ebx, %%esi\n\t"
454  "cpuid\n\t"
455  "xchgl\t%%ebx, %%esi\n\t"
456  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
457  : "a"(value));
458  return false;
459 #else
460  return true;
461 #endif
462 #elif defined(_MSC_VER)
463  // The MSVC intrinsic is portable across x86 and x64.
464  int registers[4];
465  __cpuid(registers, value);
466  *rEAX = registers[0];
467  *rEBX = registers[1];
468  *rECX = registers[2];
469  *rEDX = registers[3];
470  return false;
471 #else
472  return true;
473 #endif
474 }
475 
476 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
477 /// the 4 values in the specified arguments. If we can't run cpuid on the host,
478 /// return true.
479 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
480  unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
481  unsigned *rEDX) {
482 #if defined(__GNUC__) || defined(__clang__)
483 #if defined(__x86_64__)
484  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
485  // FIXME: should we save this for Clang?
486  __asm__("movq\t%%rbx, %%rsi\n\t"
487  "cpuid\n\t"
488  "xchgq\t%%rbx, %%rsi\n\t"
489  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
490  : "a"(value), "c"(subleaf));
491  return false;
492 #elif defined(__i386__)
493  __asm__("movl\t%%ebx, %%esi\n\t"
494  "cpuid\n\t"
495  "xchgl\t%%ebx, %%esi\n\t"
496  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
497  : "a"(value), "c"(subleaf));
498  return false;
499 #else
500  return true;
501 #endif
502 #elif defined(_MSC_VER)
503  int registers[4];
504  __cpuidex(registers, value, subleaf);
505  *rEAX = registers[0];
506  *rEBX = registers[1];
507  *rECX = registers[2];
508  *rEDX = registers[3];
509  return false;
510 #else
511  return true;
512 #endif
513 }
514 
515 // Read control register 0 (XCR0). Used to detect features such as AVX.
516 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
517 #if defined(__GNUC__) || defined(__clang__)
518  // Check xgetbv; this uses a .byte sequence instead of the instruction
519  // directly because older assemblers do not include support for xgetbv and
520  // there is no easy way to conditionally compile based on the assembler used.
521  __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
522  return false;
523 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
524  unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
525  *rEAX = Result;
526  *rEDX = Result >> 32;
527  return false;
528 #else
529  return true;
530 #endif
531 }
532 
533 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
534  unsigned *Model) {
535  *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
536  *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
537  if (*Family == 6 || *Family == 0xf) {
538  if (*Family == 0xf)
539  // Examine extended family ID if family ID is F.
540  *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
541  // Examine extended model ID if family ID is 6 or F.
542  *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
543  }
544 }
545 
546 static void
547 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
548  unsigned Brand_id, unsigned Features,
549  unsigned Features2, unsigned Features3,
550  unsigned *Type, unsigned *Subtype) {
551  if (Brand_id != 0)
552  return;
553  switch (Family) {
554  case 3:
555  *Type = X86::INTEL_i386;
556  break;
557  case 4:
558  *Type = X86::INTEL_i486;
559  break;
560  case 5:
561  if (Features & (1 << X86::FEATURE_MMX)) {
562  *Type = X86::INTEL_PENTIUM_MMX;
563  break;
564  }
565  *Type = X86::INTEL_PENTIUM;
566  break;
567  case 6:
568  switch (Model) {
569  case 0x01: // Pentium Pro processor
570  *Type = X86::INTEL_PENTIUM_PRO;
571  break;
572  case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
573  // model 03
574  case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
575  // model 05, and Intel Celeron processor, model 05
576  case 0x06: // Celeron processor, model 06
577  *Type = X86::INTEL_PENTIUM_II;
578  break;
579  case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
580  // processor, model 07
581  case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
582  // model 08, and Celeron processor, model 08
583  case 0x0a: // Pentium III Xeon processor, model 0Ah
584  case 0x0b: // Pentium III processor, model 0Bh
585  *Type = X86::INTEL_PENTIUM_III;
586  break;
587  case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
588  case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
589  // 0Dh. All processors are manufactured using the 90 nm process.
590  case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
591  // Integrated Processor with Intel QuickAssist Technology
592  *Type = X86::INTEL_PENTIUM_M;
593  break;
594  case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
595  // 0Eh. All processors are manufactured using the 65 nm process.
596  *Type = X86::INTEL_CORE_DUO;
597  break; // yonah
598  case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
599  // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
600  // mobile processor, Intel Core 2 Extreme processor, Intel
601  // Pentium Dual-Core processor, Intel Xeon processor, model
602  // 0Fh. All processors are manufactured using the 65 nm process.
603  case 0x16: // Intel Celeron processor model 16h. All processors are
604  // manufactured using the 65 nm process
605  *Type = X86::INTEL_CORE2; // "core2"
606  *Subtype = X86::INTEL_CORE2_65;
607  break;
608  case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
609  // 17h. All processors are manufactured using the 45 nm process.
610  //
611  // 45nm: Penryn , Wolfdale, Yorkfield (XE)
612  case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
613  // the 45 nm process.
614  *Type = X86::INTEL_CORE2; // "penryn"
615  *Subtype = X86::INTEL_CORE2_45;
616  break;
617  case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
618  // processors are manufactured using the 45 nm process.
619  case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
620  // As found in a Summer 2010 model iMac.
621  case 0x1f:
622  case 0x2e: // Nehalem EX
623  *Type = X86::INTEL_COREI7; // "nehalem"
624  *Subtype = X86::INTEL_COREI7_NEHALEM;
625  break;
626  case 0x25: // Intel Core i7, laptop version.
627  case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
628  // processors are manufactured using the 32 nm process.
629  case 0x2f: // Westmere EX
630  *Type = X86::INTEL_COREI7; // "westmere"
631  *Subtype = X86::INTEL_COREI7_WESTMERE;
632  break;
633  case 0x2a: // Intel Core i7 processor. All processors are manufactured
634  // using the 32 nm process.
635  case 0x2d:
636  *Type = X86::INTEL_COREI7; //"sandybridge"
637  *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
638  break;
639  case 0x3a:
640  case 0x3e: // Ivy Bridge EP
641  *Type = X86::INTEL_COREI7; // "ivybridge"
642  *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
643  break;
644 
645  // Haswell:
646  case 0x3c:
647  case 0x3f:
648  case 0x45:
649  case 0x46:
650  *Type = X86::INTEL_COREI7; // "haswell"
651  *Subtype = X86::INTEL_COREI7_HASWELL;
652  break;
653 
654  // Broadwell:
655  case 0x3d:
656  case 0x47:
657  case 0x4f:
658  case 0x56:
659  *Type = X86::INTEL_COREI7; // "broadwell"
660  *Subtype = X86::INTEL_COREI7_BROADWELL;
661  break;
662 
663  // Skylake:
664  case 0x4e: // Skylake mobile
665  case 0x5e: // Skylake desktop
666  case 0x8e: // Kaby Lake mobile
667  case 0x9e: // Kaby Lake desktop
668  *Type = X86::INTEL_COREI7; // "skylake"
669  *Subtype = X86::INTEL_COREI7_SKYLAKE;
670  break;
671 
672  // Skylake Xeon:
673  case 0x55:
674  *Type = X86::INTEL_COREI7;
675  *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
676  break;
677 
678  // Cannonlake:
679  case 0x66:
680  *Type = X86::INTEL_COREI7;
681  *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake"
682  break;
683 
684  case 0x1c: // Most 45 nm Intel Atom processors
685  case 0x26: // 45 nm Atom Lincroft
686  case 0x27: // 32 nm Atom Medfield
687  case 0x35: // 32 nm Atom Midview
688  case 0x36: // 32 nm Atom Midview
689  *Type = X86::INTEL_BONNELL;
690  break; // "bonnell"
691 
692  // Atom Silvermont codes from the Intel software optimization guide.
693  case 0x37:
694  case 0x4a:
695  case 0x4d:
696  case 0x5a:
697  case 0x5d:
698  case 0x4c: // really airmont
699  *Type = X86::INTEL_SILVERMONT;
700  break; // "silvermont"
701  // Goldmont:
702  case 0x5c: // Apollo Lake
703  case 0x5f: // Denverton
704  *Type = X86::INTEL_GOLDMONT;
705  break; // "goldmont"
706  case 0x7a:
707  *Type = X86::INTEL_GOLDMONT_PLUS;
708  break;
709  case 0x57:
710  *Type = X86::INTEL_KNL; // knl
711  break;
712  case 0x85:
713  *Type = X86::INTEL_KNM; // knm
714  break;
715 
716  default: // Unknown family 6 CPU, try to guess.
717  if (Features & (1 << X86::FEATURE_AVX512VBMI2)) {
718  *Type = X86::INTEL_COREI7;
719  *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
720  break;
721  }
722 
723  if (Features & (1 << X86::FEATURE_AVX512VBMI)) {
724  *Type = X86::INTEL_COREI7;
725  *Subtype = X86::INTEL_COREI7_CANNONLAKE;
726  break;
727  }
728 
729  if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) {
730  *Type = X86::INTEL_COREI7;
731  *Subtype = X86::INTEL_COREI7_CASCADELAKE;
732  break;
733  }
734 
735  if (Features & (1 << X86::FEATURE_AVX512VL)) {
736  *Type = X86::INTEL_COREI7;
737  *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
738  break;
739  }
740 
741  if (Features & (1 << X86::FEATURE_AVX512ER)) {
742  *Type = X86::INTEL_KNL; // knl
743  break;
744  }
745 
746  if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) {
747  if (Features3 & (1 << (X86::FEATURE_SHA - 64))) {
748  *Type = X86::INTEL_GOLDMONT;
749  } else {
750  *Type = X86::INTEL_COREI7;
751  *Subtype = X86::INTEL_COREI7_SKYLAKE;
752  }
753  break;
754  }
755  if (Features3 & (1 << (X86::FEATURE_ADX - 64))) {
756  *Type = X86::INTEL_COREI7;
757  *Subtype = X86::INTEL_COREI7_BROADWELL;
758  break;
759  }
760  if (Features & (1 << X86::FEATURE_AVX2)) {
761  *Type = X86::INTEL_COREI7;
762  *Subtype = X86::INTEL_COREI7_HASWELL;
763  break;
764  }
765  if (Features & (1 << X86::FEATURE_AVX)) {
766  *Type = X86::INTEL_COREI7;
767  *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
768  break;
769  }
770  if (Features & (1 << X86::FEATURE_SSE4_2)) {
771  if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) {
772  *Type = X86::INTEL_SILVERMONT;
773  } else {
774  *Type = X86::INTEL_COREI7;
775  *Subtype = X86::INTEL_COREI7_NEHALEM;
776  }
777  break;
778  }
779  if (Features & (1 << X86::FEATURE_SSE4_1)) {
780  *Type = X86::INTEL_CORE2; // "penryn"
781  *Subtype = X86::INTEL_CORE2_45;
782  break;
783  }
784  if (Features & (1 << X86::FEATURE_SSSE3)) {
785  if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) {
786  *Type = X86::INTEL_BONNELL; // "bonnell"
787  } else {
788  *Type = X86::INTEL_CORE2; // "core2"
789  *Subtype = X86::INTEL_CORE2_65;
790  }
791  break;
792  }
793  if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) {
794  *Type = X86::INTEL_CORE2; // "core2"
795  *Subtype = X86::INTEL_CORE2_65;
796  break;
797  }
798  if (Features & (1 << X86::FEATURE_SSE3)) {
799  *Type = X86::INTEL_CORE_DUO;
800  break;
801  }
802  if (Features & (1 << X86::FEATURE_SSE2)) {
803  *Type = X86::INTEL_PENTIUM_M;
804  break;
805  }
806  if (Features & (1 << X86::FEATURE_SSE)) {
807  *Type = X86::INTEL_PENTIUM_III;
808  break;
809  }
810  if (Features & (1 << X86::FEATURE_MMX)) {
811  *Type = X86::INTEL_PENTIUM_II;
812  break;
813  }
814  *Type = X86::INTEL_PENTIUM_PRO;
815  break;
816  }
817  break;
818  case 15: {
819  if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) {
820  *Type = X86::INTEL_NOCONA;
821  break;
822  }
823  if (Features & (1 << X86::FEATURE_SSE3)) {
824  *Type = X86::INTEL_PRESCOTT;
825  break;
826  }
827  *Type = X86::INTEL_PENTIUM_IV;
828  break;
829  }
830  default:
831  break; /*"generic"*/
832  }
833 }
834 
835 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
836  unsigned Features, unsigned *Type,
837  unsigned *Subtype) {
838  // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
839  // appears to be no way to generate the wide variety of AMD-specific targets
840  // from the information returned from CPUID.
841  switch (Family) {
842  case 4:
843  *Type = X86::AMD_i486;
844  break;
845  case 5:
846  *Type = X86::AMDPENTIUM;
847  switch (Model) {
848  case 6:
849  case 7:
850  *Subtype = X86::AMDPENTIUM_K6;
851  break; // "k6"
852  case 8:
853  *Subtype = X86::AMDPENTIUM_K62;
854  break; // "k6-2"
855  case 9:
856  case 13:
857  *Subtype = X86::AMDPENTIUM_K63;
858  break; // "k6-3"
859  case 10:
860  *Subtype = X86::AMDPENTIUM_GEODE;
861  break; // "geode"
862  }
863  break;
864  case 6:
865  if (Features & (1 << X86::FEATURE_SSE)) {
866  *Type = X86::AMD_ATHLON_XP;
867  break; // "athlon-xp"
868  }
869  *Type = X86::AMD_ATHLON;
870  break; // "athlon"
871  case 15:
872  if (Features & (1 << X86::FEATURE_SSE3)) {
873  *Type = X86::AMD_K8SSE3;
874  break; // "k8-sse3"
875  }
876  *Type = X86::AMD_K8;
877  break; // "k8"
878  case 16:
879  *Type = X86::AMDFAM10H; // "amdfam10"
880  switch (Model) {
881  case 2:
882  *Subtype = X86::AMDFAM10H_BARCELONA;
883  break;
884  case 4:
885  *Subtype = X86::AMDFAM10H_SHANGHAI;
886  break;
887  case 8:
888  *Subtype = X86::AMDFAM10H_ISTANBUL;
889  break;
890  }
891  break;
892  case 20:
893  *Type = X86::AMD_BTVER1;
894  break; // "btver1";
895  case 21:
896  *Type = X86::AMDFAM15H;
897  if (Model >= 0x60 && Model <= 0x7f) {
898  *Subtype = X86::AMDFAM15H_BDVER4;
899  break; // "bdver4"; 60h-7Fh: Excavator
900  }
901  if (Model >= 0x30 && Model <= 0x3f) {
902  *Subtype = X86::AMDFAM15H_BDVER3;
903  break; // "bdver3"; 30h-3Fh: Steamroller
904  }
905  if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
906  *Subtype = X86::AMDFAM15H_BDVER2;
907  break; // "bdver2"; 02h, 10h-1Fh: Piledriver
908  }
909  if (Model <= 0x0f) {
910  *Subtype = X86::AMDFAM15H_BDVER1;
911  break; // "bdver1"; 00h-0Fh: Bulldozer
912  }
913  break;
914  case 22:
915  *Type = X86::AMD_BTVER2;
916  break; // "btver2"
917  case 23:
918  *Type = X86::AMDFAM17H;
919  if (Model >= 0x30 && Model <= 0x3f) {
920  *Subtype = X86::AMDFAM17H_ZNVER2;
921  break; // "znver2"; 30h-3fh: Zen2
922  }
923  if (Model <= 0x0f) {
924  *Subtype = X86::AMDFAM17H_ZNVER1;
925  break; // "znver1"; 00h-0Fh: Zen1
926  }
927  break;
928  default:
929  break; // "generic"
930  }
931 }
932 
933 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
934  unsigned *FeaturesOut, unsigned *Features2Out,
935  unsigned *Features3Out) {
936  unsigned Features = 0;
937  unsigned Features2 = 0;
938  unsigned Features3 = 0;
939  unsigned EAX, EBX;
940 
941  auto setFeature = [&](unsigned F) {
942  if (F < 32)
943  Features |= 1U << (F & 0x1f);
944  else if (F < 64)
945  Features2 |= 1U << ((F - 32) & 0x1f);
946  else if (F < 96)
947  Features3 |= 1U << ((F - 64) & 0x1f);
948  else
949  llvm_unreachable("Unexpected FeatureBit");
950  };
951 
952  if ((EDX >> 15) & 1)
953  setFeature(X86::FEATURE_CMOV);
954  if ((EDX >> 23) & 1)
955  setFeature(X86::FEATURE_MMX);
956  if ((EDX >> 25) & 1)
957  setFeature(X86::FEATURE_SSE);
958  if ((EDX >> 26) & 1)
959  setFeature(X86::FEATURE_SSE2);
960 
961  if ((ECX >> 0) & 1)
962  setFeature(X86::FEATURE_SSE3);
963  if ((ECX >> 1) & 1)
964  setFeature(X86::FEATURE_PCLMUL);
965  if ((ECX >> 9) & 1)
966  setFeature(X86::FEATURE_SSSE3);
967  if ((ECX >> 12) & 1)
968  setFeature(X86::FEATURE_FMA);
969  if ((ECX >> 19) & 1)
970  setFeature(X86::FEATURE_SSE4_1);
971  if ((ECX >> 20) & 1)
972  setFeature(X86::FEATURE_SSE4_2);
973  if ((ECX >> 23) & 1)
974  setFeature(X86::FEATURE_POPCNT);
975  if ((ECX >> 25) & 1)
976  setFeature(X86::FEATURE_AES);
977 
978  if ((ECX >> 22) & 1)
979  setFeature(X86::FEATURE_MOVBE);
980 
981  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
982  // indicates that the AVX registers will be saved and restored on context
983  // switch, then we have full AVX support.
984  const unsigned AVXBits = (1 << 27) | (1 << 28);
985  bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
986  ((EAX & 0x6) == 0x6);
987  bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
988 
989  if (HasAVX)
990  setFeature(X86::FEATURE_AVX);
991 
992  bool HasLeaf7 =
993  MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
994 
995  if (HasLeaf7 && ((EBX >> 3) & 1))
996  setFeature(X86::FEATURE_BMI);
997  if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
998  setFeature(X86::FEATURE_AVX2);
999  if (HasLeaf7 && ((EBX >> 9) & 1))
1000  setFeature(X86::FEATURE_BMI2);
1001  if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1002  setFeature(X86::FEATURE_AVX512F);
1003  if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1004  setFeature(X86::FEATURE_AVX512DQ);
1005  if (HasLeaf7 && ((EBX >> 19) & 1))
1006  setFeature(X86::FEATURE_ADX);
1007  if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1008  setFeature(X86::FEATURE_AVX512IFMA);
1009  if (HasLeaf7 && ((EBX >> 23) & 1))
1010  setFeature(X86::FEATURE_CLFLUSHOPT);
1011  if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1012  setFeature(X86::FEATURE_AVX512PF);
1013  if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1014  setFeature(X86::FEATURE_AVX512ER);
1015  if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1016  setFeature(X86::FEATURE_AVX512CD);
1017  if (HasLeaf7 && ((EBX >> 29) & 1))
1018  setFeature(X86::FEATURE_SHA);
1019  if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1020  setFeature(X86::FEATURE_AVX512BW);
1021  if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1022  setFeature(X86::FEATURE_AVX512VL);
1023 
1024  if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1025  setFeature(X86::FEATURE_AVX512VBMI);
1026  if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1027  setFeature(X86::FEATURE_AVX512VBMI2);
1028  if (HasLeaf7 && ((ECX >> 8) & 1))
1029  setFeature(X86::FEATURE_GFNI);
1030  if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1031  setFeature(X86::FEATURE_VPCLMULQDQ);
1032  if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1033  setFeature(X86::FEATURE_AVX512VNNI);
1034  if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1035  setFeature(X86::FEATURE_AVX512BITALG);
1036  if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1037  setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1038 
1039  if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1040  setFeature(X86::FEATURE_AVX5124VNNIW);
1041  if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1042  setFeature(X86::FEATURE_AVX5124FMAPS);
1043 
1044  unsigned MaxExtLevel;
1045  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1046 
1047  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1048  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1049  if (HasExtLeaf1 && ((ECX >> 6) & 1))
1050  setFeature(X86::FEATURE_SSE4_A);
1051  if (HasExtLeaf1 && ((ECX >> 11) & 1))
1052  setFeature(X86::FEATURE_XOP);
1053  if (HasExtLeaf1 && ((ECX >> 16) & 1))
1054  setFeature(X86::FEATURE_FMA4);
1055 
1056  if (HasExtLeaf1 && ((EDX >> 29) & 1))
1057  setFeature(X86::FEATURE_EM64T);
1058 
1059  *FeaturesOut = Features;
1060  *Features2Out = Features2;
1061  *Features3Out = Features3;
1062 }
1063 
1065  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1066  unsigned MaxLeaf, Vendor;
1067 
1068 #if defined(__GNUC__) || defined(__clang__)
1069  //FIXME: include cpuid.h from clang or copy __get_cpuid_max here
1070  // and simplify it to not invoke __cpuid (like cpu_model.c in
1071  // compiler-rt/lib/builtins/cpu_model.c?
1072  // Opting for the second option.
1073  if(!isCpuIdSupported())
1074  return "generic";
1075 #endif
1076  if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1)
1077  return "generic";
1078  getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1079 
1080  unsigned Brand_id = EBX & 0xff;
1081  unsigned Family = 0, Model = 0;
1082  unsigned Features = 0, Features2 = 0, Features3 = 0;
1083  detectX86FamilyModel(EAX, &Family, &Model);
1084  getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3);
1085 
1086  unsigned Type = 0;
1087  unsigned Subtype = 0;
1088 
1089  if (Vendor == SIG_INTEL) {
1090  getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
1091  Features2, Features3, &Type, &Subtype);
1092  } else if (Vendor == SIG_AMD) {
1093  getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
1094  }
1095 
1096  // Check subtypes first since those are more specific.
1097 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
1098  if (Subtype == X86::ENUM) \
1099  return ARCHNAME;
1100 #include "llvm/Support/X86TargetParser.def"
1101 
1102  // Now check types.
1103 #define X86_CPU_TYPE(ARCHNAME, ENUM) \
1104  if (Type == X86::ENUM) \
1105  return ARCHNAME;
1106 #include "llvm/Support/X86TargetParser.def"
1107 
1108  return "generic";
1109 }
1110 
1111 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
1113  host_basic_info_data_t hostInfo;
1114  mach_msg_type_number_t infoCount;
1115 
1116  infoCount = HOST_BASIC_INFO_COUNT;
1117  mach_port_t hostPort = mach_host_self();
1118  host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1119  &infoCount);
1120  mach_port_deallocate(mach_task_self(), hostPort);
1121 
1122  if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1123  return "generic";
1124 
1125  switch (hostInfo.cpu_subtype) {
1127  return "601";
1129  return "602";
1131  return "603";
1133  return "603e";
1135  return "603ev";
1137  return "604";
1139  return "604e";
1141  return "620";
1143  return "750";
1145  return "7400";
1147  return "7450";
1149  return "970";
1150  default:;
1151  }
1152 
1153  return "generic";
1154 }
1155 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
1157  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1158  StringRef Content = P ? P->getBuffer() : "";
1159  return detail::getHostCPUNameForPowerPC(Content);
1160 }
1161 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1163  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1164  StringRef Content = P ? P->getBuffer() : "";
1165  return detail::getHostCPUNameForARM(Content);
1166 }
1167 #elif defined(__linux__) && defined(__s390x__)
1169  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1170  StringRef Content = P ? P->getBuffer() : "";
1171  return detail::getHostCPUNameForS390x(Content);
1172 }
1173 #else
1174 StringRef sys::getHostCPUName() { return "generic"; }
1175 #endif
1176 
1177 #if defined(__linux__) && defined(__x86_64__)
1178 // On Linux, the number of physical cores can be computed from /proc/cpuinfo,
1179 // using the number of unique physical/core id pairs. The following
1180 // implementation reads the /proc/cpuinfo format on an x86_64 system.
1181 static int computeHostNumPhysicalCores() {
1182  // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
1183  // mmapped because it appears to have 0 size.
1185  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
1186  if (std::error_code EC = Text.getError()) {
1187  llvm::errs() << "Can't read "
1188  << "/proc/cpuinfo: " << EC.message() << "\n";
1189  return -1;
1190  }
1192  (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
1193  /*KeepEmpty=*/false);
1194  int CurPhysicalId = -1;
1195  int CurCoreId = -1;
1196  SmallSet<std::pair<int, int>, 32> UniqueItems;
1197  for (auto &Line : strs) {
1198  Line = Line.trim();
1199  if (!Line.startswith("physical id") && !Line.startswith("core id"))
1200  continue;
1201  std::pair<StringRef, StringRef> Data = Line.split(':');
1202  auto Name = Data.first.trim();
1203  auto Val = Data.second.trim();
1204  if (Name == "physical id") {
1205  assert(CurPhysicalId == -1 &&
1206  "Expected a core id before seeing another physical id");
1207  Val.getAsInteger(10, CurPhysicalId);
1208  }
1209  if (Name == "core id") {
1210  assert(CurCoreId == -1 &&
1211  "Expected a physical id before seeing another core id");
1212  Val.getAsInteger(10, CurCoreId);
1213  }
1214  if (CurPhysicalId != -1 && CurCoreId != -1) {
1215  UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId));
1216  CurPhysicalId = -1;
1217  CurCoreId = -1;
1218  }
1219  }
1220  return UniqueItems.size();
1221 }
1222 #elif defined(__APPLE__) && defined(__x86_64__)
1223 #include <sys/param.h>
1224 #include <sys/sysctl.h>
1225 
1226 // Gets the number of *physical cores* on the machine.
1227 static int computeHostNumPhysicalCores() {
1228  uint32_t count;
1229  size_t len = sizeof(count);
1230  sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
1231  if (count < 1) {
1232  int nm[2];
1233  nm[0] = CTL_HW;
1234  nm[1] = HW_AVAILCPU;
1235  sysctl(nm, 2, &count, &len, NULL, 0);
1236  if (count < 1)
1237  return -1;
1238  }
1239  return count;
1240 }
1241 #else
1242 // On other systems, return -1 to indicate unknown.
1243 static int computeHostNumPhysicalCores() { return -1; }
1244 #endif
1245 
1247  static int NumCores = computeHostNumPhysicalCores();
1248  return NumCores;
1249 }
1250 
1251 #if defined(__i386__) || defined(_M_IX86) || \
1252  defined(__x86_64__) || defined(_M_X64)
1253 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1254  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1255  unsigned MaxLevel;
1256  union {
1257  unsigned u[3];
1258  char c[12];
1259  } text;
1260 
1261  if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
1262  MaxLevel < 1)
1263  return false;
1264 
1265  getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1266 
1267  Features["cx8"] = (EDX >> 8) & 1;
1268  Features["cmov"] = (EDX >> 15) & 1;
1269  Features["mmx"] = (EDX >> 23) & 1;
1270  Features["fxsr"] = (EDX >> 24) & 1;
1271  Features["sse"] = (EDX >> 25) & 1;
1272  Features["sse2"] = (EDX >> 26) & 1;
1273 
1274  Features["sse3"] = (ECX >> 0) & 1;
1275  Features["pclmul"] = (ECX >> 1) & 1;
1276  Features["ssse3"] = (ECX >> 9) & 1;
1277  Features["cx16"] = (ECX >> 13) & 1;
1278  Features["sse4.1"] = (ECX >> 19) & 1;
1279  Features["sse4.2"] = (ECX >> 20) & 1;
1280  Features["movbe"] = (ECX >> 22) & 1;
1281  Features["popcnt"] = (ECX >> 23) & 1;
1282  Features["aes"] = (ECX >> 25) & 1;
1283  Features["rdrnd"] = (ECX >> 30) & 1;
1284 
1285  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1286  // indicates that the AVX registers will be saved and restored on context
1287  // switch, then we have full AVX support.
1288  bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
1289  !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
1290  // AVX512 requires additional context to be saved by the OS.
1291  bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1292 
1293  Features["avx"] = HasAVXSave;
1294  Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
1295  // Only enable XSAVE if OS has enabled support for saving YMM state.
1296  Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1297  Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
1298 
1299  unsigned MaxExtLevel;
1300  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1301 
1302  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1303  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1304  Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
1305  Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1306  Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1307  Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1308  Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1309  Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1310  Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1311  Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1312  Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1313 
1314  Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
1315 
1316  // Miscellaneous memory related features, detected by
1317  // using the 0x80000008 leaf of the CPUID instruction
1318  bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1319  !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1320  Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1321  Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1322 
1323  bool HasLeaf7 =
1324  MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1325 
1326  Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1327  Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1328  Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1329  // AVX2 is only supported if we have the OS save support from AVX.
1330  Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
1331  Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1332  Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1333  Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1334  Features["mpx"] = HasLeaf7 && ((EBX >> 14) & 1);
1335  // AVX512 is only supported if the OS supports the context save for it.
1336  Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1337  Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1338  Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1339  Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1340  Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1341  Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1342  Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1343  Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1344  Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1345  Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1346  Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1347  Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1348  Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1349 
1350  Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1);
1351  Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1352  Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1353  Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
1354  Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
1355  Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
1356  Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
1357  Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
1358  Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1359  Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1360  Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1361  Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1362  Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
1363  Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
1364  Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
1365  Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
1366 
1367  // There are two CPUID leafs which information associated with the pconfig
1368  // instruction:
1369  // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1370  // bit of EDX), while the EAX=0x1b leaf returns information on the
1371  // availability of specific pconfig leafs.
1372  // The target feature here only refers to the the first of these two.
1373  // Users might need to check for the availability of specific pconfig
1374  // leaves using cpuid, since that information is ignored while
1375  // detecting features using the "-march=native" flag.
1376  // For more info, see X86 ISA docs.
1377  Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1378 
1379  bool HasLeafD = MaxLevel >= 0xd &&
1380  !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1381 
1382  // Only enable XSAVE if OS has enabled support for saving YMM state.
1383  Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1384  Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1385  Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1386 
1387  bool HasLeaf14 = MaxLevel >= 0x14 &&
1388  !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1389 
1390  Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1391 
1392  return true;
1393 }
1394 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1395 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1396  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1397  if (!P)
1398  return false;
1399 
1401  P->getBuffer().split(Lines, "\n");
1402 
1403  SmallVector<StringRef, 32> CPUFeatures;
1404 
1405  // Look for the CPU features.
1406  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1407  if (Lines[I].startswith("Features")) {
1408  Lines[I].split(CPUFeatures, ' ');
1409  break;
1410  }
1411 
1412 #if defined(__aarch64__)
1413  // Keep track of which crypto features we have seen
1414  enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1415  uint32_t crypto = 0;
1416 #endif
1417 
1418  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1419  StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1420 #if defined(__aarch64__)
1421  .Case("asimd", "neon")
1422  .Case("fp", "fp-armv8")
1423  .Case("crc32", "crc")
1424 #else
1425  .Case("half", "fp16")
1426  .Case("neon", "neon")
1427  .Case("vfpv3", "vfp3")
1428  .Case("vfpv3d16", "d16")
1429  .Case("vfpv4", "vfp4")
1430  .Case("idiva", "hwdiv-arm")
1431  .Case("idivt", "hwdiv")
1432 #endif
1433  .Default("");
1434 
1435 #if defined(__aarch64__)
1436  // We need to check crypto separately since we need all of the crypto
1437  // extensions to enable the subtarget feature
1438  if (CPUFeatures[I] == "aes")
1439  crypto |= CAP_AES;
1440  else if (CPUFeatures[I] == "pmull")
1441  crypto |= CAP_PMULL;
1442  else if (CPUFeatures[I] == "sha1")
1443  crypto |= CAP_SHA1;
1444  else if (CPUFeatures[I] == "sha2")
1445  crypto |= CAP_SHA2;
1446 #endif
1447 
1448  if (LLVMFeatureStr != "")
1449  Features[LLVMFeatureStr] = true;
1450  }
1451 
1452 #if defined(__aarch64__)
1453  // If we have all crypto bits we can add the feature
1454  if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1455  Features["crypto"] = true;
1456 #endif
1457 
1458  return true;
1459 }
1460 #else
1461 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1462 #endif
1463 
1464 std::string sys::getProcessTriple() {
1465  std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1466  Triple PT(Triple::normalize(TargetTripleString));
1467 
1468  if (sizeof(void *) == 8 && PT.isArch32Bit())
1469  PT = PT.get64BitArchVariant();
1470  if (sizeof(void *) == 4 && PT.isArch64Bit())
1471  PT = PT.get32BitArchVariant();
1472 
1473  return PT.str();
1474 }
Represents either an error or a value T.
Definition: ErrorOr.h:56
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
Definition: Host.cpp:56
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:267
This class represents lattice values for constants.
Definition: AllocatorList.h:23
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
Definition: Host.cpp:67
F(f)
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
Definition: Host.cpp:276
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
int getHostNumPhysicalCores()
Get the number of physical cores (as opposed to logical cores returned from thread::hardware_concurre...
Definition: Host.cpp:1246
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:29
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1280
const std::string & str() const
Definition: Triple.h:360
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1251
#define P(N)
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
Definition: Triple.cpp:1288
StringRef getHostCPUNameForBPF()
Definition: Host.cpp:329
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
std::error_code getError() const
Definition: ErrorOr.h:159
size_type size() const
Definition: SmallSet.h:159
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:159
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
size_t size() const
Definition: SmallVector.h:52
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
Definition: Host.cpp:1464
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
std::string normalize() const
Return the normalized form of this triple&#39;s string.
Definition: Triple.h:284
iterator begin() const
Definition: StringRef.h:101
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
Definition: Host.cpp:1174
static const size_t npos
Definition: StringRef.h:50
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1276
#define I(x, y, z)
Definition: MD5.cpp:58
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
Definition: Host.cpp:146
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
Definition: Triple.cpp:1351
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool getHostCPUFeatures(StringMap< bool > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
Definition: Host.cpp:1461
iterator end() const
Definition: StringRef.h:103
static int computeHostNumPhysicalCores()
Definition: Host.cpp:1243