LLVM  9.0.0svn
Host.cpp
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1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the operating system Host concept.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Config/llvm-config.h"
21 #include "llvm/Support/Debug.h"
25 #include <assert.h>
26 #include <string.h>
27 
28 // Include the platform-specific parts of this class.
29 #ifdef LLVM_ON_UNIX
30 #include "Unix/Host.inc"
31 #endif
32 #ifdef _WIN32
33 #include "Windows/Host.inc"
34 #endif
35 #ifdef _MSC_VER
36 #include <intrin.h>
37 #endif
38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
39 #include <mach/host_info.h>
40 #include <mach/mach.h>
41 #include <mach/mach_host.h>
42 #include <mach/machine.h>
43 #endif
44 
45 #define DEBUG_TYPE "host-detection"
46 
47 //===----------------------------------------------------------------------===//
48 //
49 // Implementations of the CPU detection routines
50 //
51 //===----------------------------------------------------------------------===//
52 
53 using namespace llvm;
54 
55 static std::unique_ptr<llvm::MemoryBuffer>
58  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
59  if (std::error_code EC = Text.getError()) {
60  llvm::errs() << "Can't read "
61  << "/proc/cpuinfo: " << EC.message() << "\n";
62  return nullptr;
63  }
64  return std::move(*Text);
65 }
66 
68  // Access to the Processor Version Register (PVR) on PowerPC is privileged,
69  // and so we must use an operating-system interface to determine the current
70  // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
71  const char *generic = "generic";
72 
73  // The cpu line is second (after the 'processor: 0' line), so if this
74  // buffer is too small then something has changed (or is wrong).
75  StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
76  StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
77 
78  StringRef::const_iterator CIP = CPUInfoStart;
79 
80  StringRef::const_iterator CPUStart = 0;
81  size_t CPULen = 0;
82 
83  // We need to find the first line which starts with cpu, spaces, and a colon.
84  // After the colon, there may be some additional spaces and then the cpu type.
85  while (CIP < CPUInfoEnd && CPUStart == 0) {
86  if (CIP < CPUInfoEnd && *CIP == '\n')
87  ++CIP;
88 
89  if (CIP < CPUInfoEnd && *CIP == 'c') {
90  ++CIP;
91  if (CIP < CPUInfoEnd && *CIP == 'p') {
92  ++CIP;
93  if (CIP < CPUInfoEnd && *CIP == 'u') {
94  ++CIP;
95  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
96  ++CIP;
97 
98  if (CIP < CPUInfoEnd && *CIP == ':') {
99  ++CIP;
100  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
101  ++CIP;
102 
103  if (CIP < CPUInfoEnd) {
104  CPUStart = CIP;
105  while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
106  *CIP != ',' && *CIP != '\n'))
107  ++CIP;
108  CPULen = CIP - CPUStart;
109  }
110  }
111  }
112  }
113  }
114 
115  if (CPUStart == 0)
116  while (CIP < CPUInfoEnd && *CIP != '\n')
117  ++CIP;
118  }
119 
120  if (CPUStart == 0)
121  return generic;
122 
123  return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
124  .Case("604e", "604e")
125  .Case("604", "604")
126  .Case("7400", "7400")
127  .Case("7410", "7400")
128  .Case("7447", "7400")
129  .Case("7455", "7450")
130  .Case("G4", "g4")
131  .Case("POWER4", "970")
132  .Case("PPC970FX", "970")
133  .Case("PPC970MP", "970")
134  .Case("G5", "g5")
135  .Case("POWER5", "g5")
136  .Case("A2", "a2")
137  .Case("POWER6", "pwr6")
138  .Case("POWER7", "pwr7")
139  .Case("POWER8", "pwr8")
140  .Case("POWER8E", "pwr8")
141  .Case("POWER8NVL", "pwr8")
142  .Case("POWER9", "pwr9")
143  .Default(generic);
144 }
145 
147  // The cpuid register on arm is not accessible from user space. On Linux,
148  // it is exposed through the /proc/cpuinfo file.
149 
150  // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
151  // in all cases.
153  ProcCpuinfoContent.split(Lines, "\n");
154 
155  // Look for the CPU implementer line.
156  StringRef Implementer;
157  StringRef Hardware;
158  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
159  if (Lines[I].startswith("CPU implementer"))
160  Implementer = Lines[I].substr(15).ltrim("\t :");
161  if (Lines[I].startswith("Hardware"))
162  Hardware = Lines[I].substr(8).ltrim("\t :");
163  }
164 
165  if (Implementer == "0x41") { // ARM Ltd.
166  // MSM8992/8994 may give cpu part for the core that the kernel is running on,
167  // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
168  if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
169  return "cortex-a53";
170 
171 
172  // Look for the CPU part line.
173  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
174  if (Lines[I].startswith("CPU part"))
175  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
176  // values correspond to the "Part number" in the CP15/c0 register. The
177  // contents are specified in the various processor manuals.
178  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
179  .Case("0x926", "arm926ej-s")
180  .Case("0xb02", "mpcore")
181  .Case("0xb36", "arm1136j-s")
182  .Case("0xb56", "arm1156t2-s")
183  .Case("0xb76", "arm1176jz-s")
184  .Case("0xc08", "cortex-a8")
185  .Case("0xc09", "cortex-a9")
186  .Case("0xc0f", "cortex-a15")
187  .Case("0xc20", "cortex-m0")
188  .Case("0xc23", "cortex-m3")
189  .Case("0xc24", "cortex-m4")
190  .Case("0xd04", "cortex-a35")
191  .Case("0xd03", "cortex-a53")
192  .Case("0xd07", "cortex-a57")
193  .Case("0xd08", "cortex-a72")
194  .Case("0xd09", "cortex-a73")
195  .Case("0xd0a", "cortex-a75")
196  .Case("0xd0b", "cortex-a76")
197  .Default("generic");
198  }
199 
200  if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
201  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
202  if (Lines[I].startswith("CPU part")) {
203  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
204  .Case("0x516", "thunderx2t99")
205  .Case("0x0516", "thunderx2t99")
206  .Case("0xaf", "thunderx2t99")
207  .Case("0x0af", "thunderx2t99")
208  .Case("0xa1", "thunderxt88")
209  .Case("0x0a1", "thunderxt88")
210  .Default("generic");
211  }
212  }
213  }
214 
215  if (Implementer == "0x48") // HiSilicon Technologies, Inc.
216  // Look for the CPU part line.
217  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
218  if (Lines[I].startswith("CPU part"))
219  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
220  // values correspond to the "Part number" in the CP15/c0 register. The
221  // contents are specified in the various processor manuals.
222  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
223  .Case("0xd01", "tsv110")
224  .Default("generic");
225 
226  if (Implementer == "0x51") // Qualcomm Technologies, Inc.
227  // Look for the CPU part line.
228  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
229  if (Lines[I].startswith("CPU part"))
230  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
231  // values correspond to the "Part number" in the CP15/c0 register. The
232  // contents are specified in the various processor manuals.
233  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
234  .Case("0x06f", "krait") // APQ8064
235  .Case("0x201", "kryo")
236  .Case("0x205", "kryo")
237  .Case("0x211", "kryo")
238  .Case("0x800", "cortex-a73")
239  .Case("0x801", "cortex-a73")
240  .Case("0x802", "cortex-a73")
241  .Case("0x803", "cortex-a73")
242  .Case("0x804", "cortex-a73")
243  .Case("0x805", "cortex-a73")
244  .Case("0xc00", "falkor")
245  .Case("0xc01", "saphira")
246  .Default("generic");
247 
248  if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
249  // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
250  // any predictive pattern across variants and parts.
251  unsigned Variant = 0, Part = 0;
252 
253  // Look for the CPU variant line, whose value is a 1 digit hexadecimal
254  // number, corresponding to the Variant bits in the CP15/C0 register.
255  for (auto I : Lines)
256  if (I.consume_front("CPU variant"))
257  I.ltrim("\t :").getAsInteger(0, Variant);
258 
259  // Look for the CPU part line, whose value is a 3 digit hexadecimal
260  // number, corresponding to the PartNum bits in the CP15/C0 register.
261  for (auto I : Lines)
262  if (I.consume_front("CPU part"))
263  I.ltrim("\t :").getAsInteger(0, Part);
264 
265  unsigned Exynos = (Variant << 12) | Part;
266  switch (Exynos) {
267  default:
268  // Default by falling through to Exynos M1.
270 
271  case 0x1001:
272  return "exynos-m1";
273 
274  case 0x4001:
275  return "exynos-m2";
276  }
277  }
278 
279  return "generic";
280 }
281 
283  // STIDP is a privileged operation, so use /proc/cpuinfo instead.
284 
285  // The "processor 0:" line comes after a fair amount of other information,
286  // including a cache breakdown, but this should be plenty.
288  ProcCpuinfoContent.split(Lines, "\n");
289 
290  // Look for the CPU features.
291  SmallVector<StringRef, 32> CPUFeatures;
292  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
293  if (Lines[I].startswith("features")) {
294  size_t Pos = Lines[I].find(":");
295  if (Pos != StringRef::npos) {
296  Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
297  break;
298  }
299  }
300 
301  // We need to check for the presence of vector support independently of
302  // the machine type, since we may only use the vector register set when
303  // supported by the kernel (and hypervisor).
304  bool HaveVectorSupport = false;
305  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
306  if (CPUFeatures[I] == "vx")
307  HaveVectorSupport = true;
308  }
309 
310  // Now check the processor machine type.
311  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
312  if (Lines[I].startswith("processor ")) {
313  size_t Pos = Lines[I].find("machine = ");
314  if (Pos != StringRef::npos) {
315  Pos += sizeof("machine = ") - 1;
316  unsigned int Id;
317  if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
318  if (Id >= 3906 && HaveVectorSupport)
319  return "z14";
320  if (Id >= 2964 && HaveVectorSupport)
321  return "z13";
322  if (Id >= 2827)
323  return "zEC12";
324  if (Id >= 2817)
325  return "z196";
326  }
327  }
328  break;
329  }
330  }
331 
332  return "generic";
333 }
334 
336 #if !defined(__linux__) || !defined(__x86_64__)
337  return "generic";
338 #else
339  uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
340  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
341  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
342  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
343  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
344  /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
345  0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
346  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
347  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
348  /* BPF_EXIT_INSN() */
349  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
350 
351  uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
352  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
353  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
354  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
355  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
356  /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
357  0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
358  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
359  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
360  /* BPF_EXIT_INSN() */
361  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
362 
363  struct bpf_prog_load_attr {
364  uint32_t prog_type;
365  uint32_t insn_cnt;
366  uint64_t insns;
367  uint64_t license;
368  uint32_t log_level;
369  uint32_t log_size;
370  uint64_t log_buf;
371  uint32_t kern_version;
372  uint32_t prog_flags;
373  } attr = {};
374  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
375  attr.insn_cnt = 5;
376  attr.insns = (uint64_t)v3_insns;
377  attr.license = (uint64_t)"DUMMY";
378 
379  int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
380  sizeof(attr));
381  if (fd >= 0) {
382  close(fd);
383  return "v3";
384  }
385 
386  /* Clear the whole attr in case its content changed by syscall. */
387  memset(&attr, 0, sizeof(attr));
388  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
389  attr.insn_cnt = 5;
390  attr.insns = (uint64_t)v2_insns;
391  attr.license = (uint64_t)"DUMMY";
392  fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
393  if (fd >= 0) {
394  close(fd);
395  return "v2";
396  }
397  return "v1";
398 #endif
399 }
400 
401 #if defined(__i386__) || defined(_M_IX86) || \
402  defined(__x86_64__) || defined(_M_X64)
403 
404 enum VendorSignatures {
405  SIG_INTEL = 0x756e6547 /* Genu */,
406  SIG_AMD = 0x68747541 /* Auth */
407 };
408 
409 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
410 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
411 // support. Consequently, for i386, the presence of CPUID is checked first
412 // via the corresponding eflags bit.
413 // Removal of cpuid.h header motivated by PR30384
414 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
415 // or test-suite, but are used in external projects e.g. libstdcxx
416 static bool isCpuIdSupported() {
417 #if defined(__GNUC__) || defined(__clang__)
418 #if defined(__i386__)
419  int __cpuid_supported;
420  __asm__(" pushfl\n"
421  " popl %%eax\n"
422  " movl %%eax,%%ecx\n"
423  " xorl $0x00200000,%%eax\n"
424  " pushl %%eax\n"
425  " popfl\n"
426  " pushfl\n"
427  " popl %%eax\n"
428  " movl $0,%0\n"
429  " cmpl %%eax,%%ecx\n"
430  " je 1f\n"
431  " movl $1,%0\n"
432  "1:"
433  : "=r"(__cpuid_supported)
434  :
435  : "eax", "ecx");
436  if (!__cpuid_supported)
437  return false;
438 #endif
439  return true;
440 #endif
441  return true;
442 }
443 
444 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
445 /// the specified arguments. If we can't run cpuid on the host, return true.
446 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
447  unsigned *rECX, unsigned *rEDX) {
448 #if defined(__GNUC__) || defined(__clang__)
449 #if defined(__x86_64__)
450  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
451  // FIXME: should we save this for Clang?
452  __asm__("movq\t%%rbx, %%rsi\n\t"
453  "cpuid\n\t"
454  "xchgq\t%%rbx, %%rsi\n\t"
455  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
456  : "a"(value));
457  return false;
458 #elif defined(__i386__)
459  __asm__("movl\t%%ebx, %%esi\n\t"
460  "cpuid\n\t"
461  "xchgl\t%%ebx, %%esi\n\t"
462  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
463  : "a"(value));
464  return false;
465 #else
466  return true;
467 #endif
468 #elif defined(_MSC_VER)
469  // The MSVC intrinsic is portable across x86 and x64.
470  int registers[4];
471  __cpuid(registers, value);
472  *rEAX = registers[0];
473  *rEBX = registers[1];
474  *rECX = registers[2];
475  *rEDX = registers[3];
476  return false;
477 #else
478  return true;
479 #endif
480 }
481 
482 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
483 /// the 4 values in the specified arguments. If we can't run cpuid on the host,
484 /// return true.
485 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
486  unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
487  unsigned *rEDX) {
488 #if defined(__GNUC__) || defined(__clang__)
489 #if defined(__x86_64__)
490  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
491  // FIXME: should we save this for Clang?
492  __asm__("movq\t%%rbx, %%rsi\n\t"
493  "cpuid\n\t"
494  "xchgq\t%%rbx, %%rsi\n\t"
495  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
496  : "a"(value), "c"(subleaf));
497  return false;
498 #elif defined(__i386__)
499  __asm__("movl\t%%ebx, %%esi\n\t"
500  "cpuid\n\t"
501  "xchgl\t%%ebx, %%esi\n\t"
502  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
503  : "a"(value), "c"(subleaf));
504  return false;
505 #else
506  return true;
507 #endif
508 #elif defined(_MSC_VER)
509  int registers[4];
510  __cpuidex(registers, value, subleaf);
511  *rEAX = registers[0];
512  *rEBX = registers[1];
513  *rECX = registers[2];
514  *rEDX = registers[3];
515  return false;
516 #else
517  return true;
518 #endif
519 }
520 
521 // Read control register 0 (XCR0). Used to detect features such as AVX.
522 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
523 #if defined(__GNUC__) || defined(__clang__)
524  // Check xgetbv; this uses a .byte sequence instead of the instruction
525  // directly because older assemblers do not include support for xgetbv and
526  // there is no easy way to conditionally compile based on the assembler used.
527  __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
528  return false;
529 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
530  unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
531  *rEAX = Result;
532  *rEDX = Result >> 32;
533  return false;
534 #else
535  return true;
536 #endif
537 }
538 
539 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
540  unsigned *Model) {
541  *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
542  *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
543  if (*Family == 6 || *Family == 0xf) {
544  if (*Family == 0xf)
545  // Examine extended family ID if family ID is F.
546  *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
547  // Examine extended model ID if family ID is 6 or F.
548  *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
549  }
550 }
551 
552 static void
553 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
554  unsigned Brand_id, unsigned Features,
555  unsigned Features2, unsigned Features3,
556  unsigned *Type, unsigned *Subtype) {
557  if (Brand_id != 0)
558  return;
559  switch (Family) {
560  case 3:
561  *Type = X86::INTEL_i386;
562  break;
563  case 4:
564  *Type = X86::INTEL_i486;
565  break;
566  case 5:
567  if (Features & (1 << X86::FEATURE_MMX)) {
568  *Type = X86::INTEL_PENTIUM_MMX;
569  break;
570  }
571  *Type = X86::INTEL_PENTIUM;
572  break;
573  case 6:
574  switch (Model) {
575  case 0x01: // Pentium Pro processor
576  *Type = X86::INTEL_PENTIUM_PRO;
577  break;
578  case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
579  // model 03
580  case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
581  // model 05, and Intel Celeron processor, model 05
582  case 0x06: // Celeron processor, model 06
583  *Type = X86::INTEL_PENTIUM_II;
584  break;
585  case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
586  // processor, model 07
587  case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
588  // model 08, and Celeron processor, model 08
589  case 0x0a: // Pentium III Xeon processor, model 0Ah
590  case 0x0b: // Pentium III processor, model 0Bh
591  *Type = X86::INTEL_PENTIUM_III;
592  break;
593  case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
594  case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
595  // 0Dh. All processors are manufactured using the 90 nm process.
596  case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
597  // Integrated Processor with Intel QuickAssist Technology
598  *Type = X86::INTEL_PENTIUM_M;
599  break;
600  case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
601  // 0Eh. All processors are manufactured using the 65 nm process.
602  *Type = X86::INTEL_CORE_DUO;
603  break; // yonah
604  case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
605  // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
606  // mobile processor, Intel Core 2 Extreme processor, Intel
607  // Pentium Dual-Core processor, Intel Xeon processor, model
608  // 0Fh. All processors are manufactured using the 65 nm process.
609  case 0x16: // Intel Celeron processor model 16h. All processors are
610  // manufactured using the 65 nm process
611  *Type = X86::INTEL_CORE2; // "core2"
612  *Subtype = X86::INTEL_CORE2_65;
613  break;
614  case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
615  // 17h. All processors are manufactured using the 45 nm process.
616  //
617  // 45nm: Penryn , Wolfdale, Yorkfield (XE)
618  case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
619  // the 45 nm process.
620  *Type = X86::INTEL_CORE2; // "penryn"
621  *Subtype = X86::INTEL_CORE2_45;
622  break;
623  case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
624  // processors are manufactured using the 45 nm process.
625  case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
626  // As found in a Summer 2010 model iMac.
627  case 0x1f:
628  case 0x2e: // Nehalem EX
629  *Type = X86::INTEL_COREI7; // "nehalem"
630  *Subtype = X86::INTEL_COREI7_NEHALEM;
631  break;
632  case 0x25: // Intel Core i7, laptop version.
633  case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
634  // processors are manufactured using the 32 nm process.
635  case 0x2f: // Westmere EX
636  *Type = X86::INTEL_COREI7; // "westmere"
637  *Subtype = X86::INTEL_COREI7_WESTMERE;
638  break;
639  case 0x2a: // Intel Core i7 processor. All processors are manufactured
640  // using the 32 nm process.
641  case 0x2d:
642  *Type = X86::INTEL_COREI7; //"sandybridge"
643  *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
644  break;
645  case 0x3a:
646  case 0x3e: // Ivy Bridge EP
647  *Type = X86::INTEL_COREI7; // "ivybridge"
648  *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
649  break;
650 
651  // Haswell:
652  case 0x3c:
653  case 0x3f:
654  case 0x45:
655  case 0x46:
656  *Type = X86::INTEL_COREI7; // "haswell"
657  *Subtype = X86::INTEL_COREI7_HASWELL;
658  break;
659 
660  // Broadwell:
661  case 0x3d:
662  case 0x47:
663  case 0x4f:
664  case 0x56:
665  *Type = X86::INTEL_COREI7; // "broadwell"
666  *Subtype = X86::INTEL_COREI7_BROADWELL;
667  break;
668 
669  // Skylake:
670  case 0x4e: // Skylake mobile
671  case 0x5e: // Skylake desktop
672  case 0x8e: // Kaby Lake mobile
673  case 0x9e: // Kaby Lake desktop
674  *Type = X86::INTEL_COREI7; // "skylake"
675  *Subtype = X86::INTEL_COREI7_SKYLAKE;
676  break;
677 
678  // Skylake Xeon:
679  case 0x55:
680  *Type = X86::INTEL_COREI7;
681  if (Features3 & (1 << (X86::FEATURE_AVX512BF16 - 64)))
682  *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake"
683  else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32)))
684  *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake"
685  else
686  *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
687  break;
688 
689  // Cannonlake:
690  case 0x66:
691  *Type = X86::INTEL_COREI7;
692  *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake"
693  break;
694 
695  // Icelake:
696  case 0x7d:
697  case 0x7e:
698  *Type = X86::INTEL_COREI7;
699  *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client"
700  break;
701 
702  // Icelake Xeon:
703  case 0x6a:
704  case 0x6c:
705  *Type = X86::INTEL_COREI7;
706  *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server"
707  break;
708 
709  case 0x1c: // Most 45 nm Intel Atom processors
710  case 0x26: // 45 nm Atom Lincroft
711  case 0x27: // 32 nm Atom Medfield
712  case 0x35: // 32 nm Atom Midview
713  case 0x36: // 32 nm Atom Midview
714  *Type = X86::INTEL_BONNELL;
715  break; // "bonnell"
716 
717  // Atom Silvermont codes from the Intel software optimization guide.
718  case 0x37:
719  case 0x4a:
720  case 0x4d:
721  case 0x5a:
722  case 0x5d:
723  case 0x4c: // really airmont
724  *Type = X86::INTEL_SILVERMONT;
725  break; // "silvermont"
726  // Goldmont:
727  case 0x5c: // Apollo Lake
728  case 0x5f: // Denverton
729  *Type = X86::INTEL_GOLDMONT;
730  break; // "goldmont"
731  case 0x7a:
732  *Type = X86::INTEL_GOLDMONT_PLUS;
733  break;
734  case 0x86:
735  *Type = X86::INTEL_TREMONT;
736  break;
737 
738  case 0x57:
739  *Type = X86::INTEL_KNL; // knl
740  break;
741 
742  case 0x85:
743  *Type = X86::INTEL_KNM; // knm
744  break;
745 
746  default: // Unknown family 6 CPU, try to guess.
747  if (Features & (1 << X86::FEATURE_AVX512VBMI2)) {
748  *Type = X86::INTEL_COREI7;
749  *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
750  break;
751  }
752 
753  if (Features & (1 << X86::FEATURE_AVX512VBMI)) {
754  *Type = X86::INTEL_COREI7;
755  *Subtype = X86::INTEL_COREI7_CANNONLAKE;
756  break;
757  }
758 
759  if (Features3 & (1 << (X86::FEATURE_AVX512BF16 - 64))) {
760  *Type = X86::INTEL_COREI7;
761  *Subtype = X86::INTEL_COREI7_COOPERLAKE;
762  break;
763  }
764 
765  if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) {
766  *Type = X86::INTEL_COREI7;
767  *Subtype = X86::INTEL_COREI7_CASCADELAKE;
768  break;
769  }
770 
771  if (Features & (1 << X86::FEATURE_AVX512VL)) {
772  *Type = X86::INTEL_COREI7;
773  *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
774  break;
775  }
776 
777  if (Features & (1 << X86::FEATURE_AVX512ER)) {
778  *Type = X86::INTEL_KNL; // knl
779  break;
780  }
781 
782  if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) {
783  if (Features3 & (1 << (X86::FEATURE_SHA - 64))) {
784  *Type = X86::INTEL_GOLDMONT;
785  } else {
786  *Type = X86::INTEL_COREI7;
787  *Subtype = X86::INTEL_COREI7_SKYLAKE;
788  }
789  break;
790  }
791  if (Features3 & (1 << (X86::FEATURE_ADX - 64))) {
792  *Type = X86::INTEL_COREI7;
793  *Subtype = X86::INTEL_COREI7_BROADWELL;
794  break;
795  }
796  if (Features & (1 << X86::FEATURE_AVX2)) {
797  *Type = X86::INTEL_COREI7;
798  *Subtype = X86::INTEL_COREI7_HASWELL;
799  break;
800  }
801  if (Features & (1 << X86::FEATURE_AVX)) {
802  *Type = X86::INTEL_COREI7;
803  *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
804  break;
805  }
806  if (Features & (1 << X86::FEATURE_SSE4_2)) {
807  if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) {
808  *Type = X86::INTEL_SILVERMONT;
809  } else {
810  *Type = X86::INTEL_COREI7;
811  *Subtype = X86::INTEL_COREI7_NEHALEM;
812  }
813  break;
814  }
815  if (Features & (1 << X86::FEATURE_SSE4_1)) {
816  *Type = X86::INTEL_CORE2; // "penryn"
817  *Subtype = X86::INTEL_CORE2_45;
818  break;
819  }
820  if (Features & (1 << X86::FEATURE_SSSE3)) {
821  if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) {
822  *Type = X86::INTEL_BONNELL; // "bonnell"
823  } else {
824  *Type = X86::INTEL_CORE2; // "core2"
825  *Subtype = X86::INTEL_CORE2_65;
826  }
827  break;
828  }
829  if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) {
830  *Type = X86::INTEL_CORE2; // "core2"
831  *Subtype = X86::INTEL_CORE2_65;
832  break;
833  }
834  if (Features & (1 << X86::FEATURE_SSE3)) {
835  *Type = X86::INTEL_CORE_DUO;
836  break;
837  }
838  if (Features & (1 << X86::FEATURE_SSE2)) {
839  *Type = X86::INTEL_PENTIUM_M;
840  break;
841  }
842  if (Features & (1 << X86::FEATURE_SSE)) {
843  *Type = X86::INTEL_PENTIUM_III;
844  break;
845  }
846  if (Features & (1 << X86::FEATURE_MMX)) {
847  *Type = X86::INTEL_PENTIUM_II;
848  break;
849  }
850  *Type = X86::INTEL_PENTIUM_PRO;
851  break;
852  }
853  break;
854  case 15: {
855  if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) {
856  *Type = X86::INTEL_NOCONA;
857  break;
858  }
859  if (Features & (1 << X86::FEATURE_SSE3)) {
860  *Type = X86::INTEL_PRESCOTT;
861  break;
862  }
863  *Type = X86::INTEL_PENTIUM_IV;
864  break;
865  }
866  default:
867  break; /*"generic"*/
868  }
869 }
870 
871 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
872  unsigned Features, unsigned *Type,
873  unsigned *Subtype) {
874  // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
875  // appears to be no way to generate the wide variety of AMD-specific targets
876  // from the information returned from CPUID.
877  switch (Family) {
878  case 4:
879  *Type = X86::AMD_i486;
880  break;
881  case 5:
882  *Type = X86::AMDPENTIUM;
883  switch (Model) {
884  case 6:
885  case 7:
886  *Subtype = X86::AMDPENTIUM_K6;
887  break; // "k6"
888  case 8:
889  *Subtype = X86::AMDPENTIUM_K62;
890  break; // "k6-2"
891  case 9:
892  case 13:
893  *Subtype = X86::AMDPENTIUM_K63;
894  break; // "k6-3"
895  case 10:
896  *Subtype = X86::AMDPENTIUM_GEODE;
897  break; // "geode"
898  }
899  break;
900  case 6:
901  if (Features & (1 << X86::FEATURE_SSE)) {
902  *Type = X86::AMD_ATHLON_XP;
903  break; // "athlon-xp"
904  }
905  *Type = X86::AMD_ATHLON;
906  break; // "athlon"
907  case 15:
908  if (Features & (1 << X86::FEATURE_SSE3)) {
909  *Type = X86::AMD_K8SSE3;
910  break; // "k8-sse3"
911  }
912  *Type = X86::AMD_K8;
913  break; // "k8"
914  case 16:
915  *Type = X86::AMDFAM10H; // "amdfam10"
916  switch (Model) {
917  case 2:
918  *Subtype = X86::AMDFAM10H_BARCELONA;
919  break;
920  case 4:
921  *Subtype = X86::AMDFAM10H_SHANGHAI;
922  break;
923  case 8:
924  *Subtype = X86::AMDFAM10H_ISTANBUL;
925  break;
926  }
927  break;
928  case 20:
929  *Type = X86::AMD_BTVER1;
930  break; // "btver1";
931  case 21:
932  *Type = X86::AMDFAM15H;
933  if (Model >= 0x60 && Model <= 0x7f) {
934  *Subtype = X86::AMDFAM15H_BDVER4;
935  break; // "bdver4"; 60h-7Fh: Excavator
936  }
937  if (Model >= 0x30 && Model <= 0x3f) {
938  *Subtype = X86::AMDFAM15H_BDVER3;
939  break; // "bdver3"; 30h-3Fh: Steamroller
940  }
941  if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
942  *Subtype = X86::AMDFAM15H_BDVER2;
943  break; // "bdver2"; 02h, 10h-1Fh: Piledriver
944  }
945  if (Model <= 0x0f) {
946  *Subtype = X86::AMDFAM15H_BDVER1;
947  break; // "bdver1"; 00h-0Fh: Bulldozer
948  }
949  break;
950  case 22:
951  *Type = X86::AMD_BTVER2;
952  break; // "btver2"
953  case 23:
954  *Type = X86::AMDFAM17H;
955  if (Model >= 0x30 && Model <= 0x3f) {
956  *Subtype = X86::AMDFAM17H_ZNVER2;
957  break; // "znver2"; 30h-3fh: Zen2
958  }
959  if (Model <= 0x0f) {
960  *Subtype = X86::AMDFAM17H_ZNVER1;
961  break; // "znver1"; 00h-0Fh: Zen1
962  }
963  break;
964  default:
965  break; // "generic"
966  }
967 }
968 
969 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
970  unsigned *FeaturesOut, unsigned *Features2Out,
971  unsigned *Features3Out) {
972  unsigned Features = 0;
973  unsigned Features2 = 0;
974  unsigned Features3 = 0;
975  unsigned EAX, EBX;
976 
977  auto setFeature = [&](unsigned F) {
978  if (F < 32)
979  Features |= 1U << (F & 0x1f);
980  else if (F < 64)
981  Features2 |= 1U << ((F - 32) & 0x1f);
982  else if (F < 96)
983  Features3 |= 1U << ((F - 64) & 0x1f);
984  else
985  llvm_unreachable("Unexpected FeatureBit");
986  };
987 
988  if ((EDX >> 15) & 1)
989  setFeature(X86::FEATURE_CMOV);
990  if ((EDX >> 23) & 1)
991  setFeature(X86::FEATURE_MMX);
992  if ((EDX >> 25) & 1)
993  setFeature(X86::FEATURE_SSE);
994  if ((EDX >> 26) & 1)
995  setFeature(X86::FEATURE_SSE2);
996 
997  if ((ECX >> 0) & 1)
998  setFeature(X86::FEATURE_SSE3);
999  if ((ECX >> 1) & 1)
1000  setFeature(X86::FEATURE_PCLMUL);
1001  if ((ECX >> 9) & 1)
1002  setFeature(X86::FEATURE_SSSE3);
1003  if ((ECX >> 12) & 1)
1004  setFeature(X86::FEATURE_FMA);
1005  if ((ECX >> 19) & 1)
1006  setFeature(X86::FEATURE_SSE4_1);
1007  if ((ECX >> 20) & 1)
1008  setFeature(X86::FEATURE_SSE4_2);
1009  if ((ECX >> 23) & 1)
1010  setFeature(X86::FEATURE_POPCNT);
1011  if ((ECX >> 25) & 1)
1012  setFeature(X86::FEATURE_AES);
1013 
1014  if ((ECX >> 22) & 1)
1015  setFeature(X86::FEATURE_MOVBE);
1016 
1017  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1018  // indicates that the AVX registers will be saved and restored on context
1019  // switch, then we have full AVX support.
1020  const unsigned AVXBits = (1 << 27) | (1 << 28);
1021  bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1022  ((EAX & 0x6) == 0x6);
1023  bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1024 
1025  if (HasAVX)
1026  setFeature(X86::FEATURE_AVX);
1027 
1028  bool HasLeaf7 =
1029  MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1030 
1031  if (HasLeaf7 && ((EBX >> 3) & 1))
1032  setFeature(X86::FEATURE_BMI);
1033  if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1034  setFeature(X86::FEATURE_AVX2);
1035  if (HasLeaf7 && ((EBX >> 9) & 1))
1036  setFeature(X86::FEATURE_BMI2);
1037  if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1038  setFeature(X86::FEATURE_AVX512F);
1039  if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1040  setFeature(X86::FEATURE_AVX512DQ);
1041  if (HasLeaf7 && ((EBX >> 19) & 1))
1042  setFeature(X86::FEATURE_ADX);
1043  if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1044  setFeature(X86::FEATURE_AVX512IFMA);
1045  if (HasLeaf7 && ((EBX >> 23) & 1))
1046  setFeature(X86::FEATURE_CLFLUSHOPT);
1047  if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1048  setFeature(X86::FEATURE_AVX512PF);
1049  if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1050  setFeature(X86::FEATURE_AVX512ER);
1051  if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1052  setFeature(X86::FEATURE_AVX512CD);
1053  if (HasLeaf7 && ((EBX >> 29) & 1))
1054  setFeature(X86::FEATURE_SHA);
1055  if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1056  setFeature(X86::FEATURE_AVX512BW);
1057  if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1058  setFeature(X86::FEATURE_AVX512VL);
1059 
1060  if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1061  setFeature(X86::FEATURE_AVX512VBMI);
1062  if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1063  setFeature(X86::FEATURE_AVX512VBMI2);
1064  if (HasLeaf7 && ((ECX >> 8) & 1))
1065  setFeature(X86::FEATURE_GFNI);
1066  if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1067  setFeature(X86::FEATURE_VPCLMULQDQ);
1068  if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1069  setFeature(X86::FEATURE_AVX512VNNI);
1070  if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1071  setFeature(X86::FEATURE_AVX512BITALG);
1072  if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1073  setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1074 
1075  if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1076  setFeature(X86::FEATURE_AVX5124VNNIW);
1077  if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1078  setFeature(X86::FEATURE_AVX5124FMAPS);
1079 
1080  unsigned MaxExtLevel;
1081  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1082 
1083  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1084  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1085  if (HasExtLeaf1 && ((ECX >> 6) & 1))
1086  setFeature(X86::FEATURE_SSE4_A);
1087  if (HasExtLeaf1 && ((ECX >> 11) & 1))
1088  setFeature(X86::FEATURE_XOP);
1089  if (HasExtLeaf1 && ((ECX >> 16) & 1))
1090  setFeature(X86::FEATURE_FMA4);
1091 
1092  if (HasExtLeaf1 && ((EDX >> 29) & 1))
1093  setFeature(X86::FEATURE_EM64T);
1094 
1095  *FeaturesOut = Features;
1096  *Features2Out = Features2;
1097  *Features3Out = Features3;
1098 }
1099 
1101  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1102  unsigned MaxLeaf, Vendor;
1103 
1104 #if defined(__GNUC__) || defined(__clang__)
1105  //FIXME: include cpuid.h from clang or copy __get_cpuid_max here
1106  // and simplify it to not invoke __cpuid (like cpu_model.c in
1107  // compiler-rt/lib/builtins/cpu_model.c?
1108  // Opting for the second option.
1109  if(!isCpuIdSupported())
1110  return "generic";
1111 #endif
1112  if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1)
1113  return "generic";
1114  getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1115 
1116  unsigned Brand_id = EBX & 0xff;
1117  unsigned Family = 0, Model = 0;
1118  unsigned Features = 0, Features2 = 0, Features3 = 0;
1119  detectX86FamilyModel(EAX, &Family, &Model);
1120  getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3);
1121 
1122  unsigned Type = 0;
1123  unsigned Subtype = 0;
1124 
1125  if (Vendor == SIG_INTEL) {
1126  getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
1127  Features2, Features3, &Type, &Subtype);
1128  } else if (Vendor == SIG_AMD) {
1129  getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
1130  }
1131 
1132  // Check subtypes first since those are more specific.
1133 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
1134  if (Subtype == X86::ENUM) \
1135  return ARCHNAME;
1136 #include "llvm/Support/X86TargetParser.def"
1137 
1138  // Now check types.
1139 #define X86_CPU_TYPE(ARCHNAME, ENUM) \
1140  if (Type == X86::ENUM) \
1141  return ARCHNAME;
1142 #include "llvm/Support/X86TargetParser.def"
1143 
1144  return "generic";
1145 }
1146 
1147 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
1149  host_basic_info_data_t hostInfo;
1150  mach_msg_type_number_t infoCount;
1151 
1152  infoCount = HOST_BASIC_INFO_COUNT;
1153  mach_port_t hostPort = mach_host_self();
1154  host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1155  &infoCount);
1156  mach_port_deallocate(mach_task_self(), hostPort);
1157 
1158  if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1159  return "generic";
1160 
1161  switch (hostInfo.cpu_subtype) {
1163  return "601";
1165  return "602";
1167  return "603";
1169  return "603e";
1171  return "603ev";
1173  return "604";
1175  return "604e";
1177  return "620";
1179  return "750";
1181  return "7400";
1183  return "7450";
1185  return "970";
1186  default:;
1187  }
1188 
1189  return "generic";
1190 }
1191 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
1193  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1194  StringRef Content = P ? P->getBuffer() : "";
1195  return detail::getHostCPUNameForPowerPC(Content);
1196 }
1197 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1199  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1200  StringRef Content = P ? P->getBuffer() : "";
1201  return detail::getHostCPUNameForARM(Content);
1202 }
1203 #elif defined(__linux__) && defined(__s390x__)
1205  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1206  StringRef Content = P ? P->getBuffer() : "";
1207  return detail::getHostCPUNameForS390x(Content);
1208 }
1209 #else
1210 StringRef sys::getHostCPUName() { return "generic"; }
1211 #endif
1212 
1213 #if defined(__linux__) && defined(__x86_64__)
1214 // On Linux, the number of physical cores can be computed from /proc/cpuinfo,
1215 // using the number of unique physical/core id pairs. The following
1216 // implementation reads the /proc/cpuinfo format on an x86_64 system.
1217 static int computeHostNumPhysicalCores() {
1218  // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
1219  // mmapped because it appears to have 0 size.
1221  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
1222  if (std::error_code EC = Text.getError()) {
1223  llvm::errs() << "Can't read "
1224  << "/proc/cpuinfo: " << EC.message() << "\n";
1225  return -1;
1226  }
1228  (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
1229  /*KeepEmpty=*/false);
1230  int CurPhysicalId = -1;
1231  int CurCoreId = -1;
1232  SmallSet<std::pair<int, int>, 32> UniqueItems;
1233  for (auto &Line : strs) {
1234  Line = Line.trim();
1235  if (!Line.startswith("physical id") && !Line.startswith("core id"))
1236  continue;
1237  std::pair<StringRef, StringRef> Data = Line.split(':');
1238  auto Name = Data.first.trim();
1239  auto Val = Data.second.trim();
1240  if (Name == "physical id") {
1241  assert(CurPhysicalId == -1 &&
1242  "Expected a core id before seeing another physical id");
1243  Val.getAsInteger(10, CurPhysicalId);
1244  }
1245  if (Name == "core id") {
1246  assert(CurCoreId == -1 &&
1247  "Expected a physical id before seeing another core id");
1248  Val.getAsInteger(10, CurCoreId);
1249  }
1250  if (CurPhysicalId != -1 && CurCoreId != -1) {
1251  UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId));
1252  CurPhysicalId = -1;
1253  CurCoreId = -1;
1254  }
1255  }
1256  return UniqueItems.size();
1257 }
1258 #elif defined(__APPLE__) && defined(__x86_64__)
1259 #include <sys/param.h>
1260 #include <sys/sysctl.h>
1261 
1262 // Gets the number of *physical cores* on the machine.
1263 static int computeHostNumPhysicalCores() {
1264  uint32_t count;
1265  size_t len = sizeof(count);
1266  sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
1267  if (count < 1) {
1268  int nm[2];
1269  nm[0] = CTL_HW;
1270  nm[1] = HW_AVAILCPU;
1271  sysctl(nm, 2, &count, &len, NULL, 0);
1272  if (count < 1)
1273  return -1;
1274  }
1275  return count;
1276 }
1277 #else
1278 // On other systems, return -1 to indicate unknown.
1279 static int computeHostNumPhysicalCores() { return -1; }
1280 #endif
1281 
1283  static int NumCores = computeHostNumPhysicalCores();
1284  return NumCores;
1285 }
1286 
1287 #if defined(__i386__) || defined(_M_IX86) || \
1288  defined(__x86_64__) || defined(_M_X64)
1289 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1290  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1291  unsigned MaxLevel;
1292  union {
1293  unsigned u[3];
1294  char c[12];
1295  } text;
1296 
1297  if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
1298  MaxLevel < 1)
1299  return false;
1300 
1301  getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1302 
1303  Features["cx8"] = (EDX >> 8) & 1;
1304  Features["cmov"] = (EDX >> 15) & 1;
1305  Features["mmx"] = (EDX >> 23) & 1;
1306  Features["fxsr"] = (EDX >> 24) & 1;
1307  Features["sse"] = (EDX >> 25) & 1;
1308  Features["sse2"] = (EDX >> 26) & 1;
1309 
1310  Features["sse3"] = (ECX >> 0) & 1;
1311  Features["pclmul"] = (ECX >> 1) & 1;
1312  Features["ssse3"] = (ECX >> 9) & 1;
1313  Features["cx16"] = (ECX >> 13) & 1;
1314  Features["sse4.1"] = (ECX >> 19) & 1;
1315  Features["sse4.2"] = (ECX >> 20) & 1;
1316  Features["movbe"] = (ECX >> 22) & 1;
1317  Features["popcnt"] = (ECX >> 23) & 1;
1318  Features["aes"] = (ECX >> 25) & 1;
1319  Features["rdrnd"] = (ECX >> 30) & 1;
1320 
1321  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1322  // indicates that the AVX registers will be saved and restored on context
1323  // switch, then we have full AVX support.
1324  bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
1325  !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
1326  // AVX512 requires additional context to be saved by the OS.
1327  bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1328 
1329  Features["avx"] = HasAVXSave;
1330  Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
1331  // Only enable XSAVE if OS has enabled support for saving YMM state.
1332  Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1333  Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
1334 
1335  unsigned MaxExtLevel;
1336  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1337 
1338  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1339  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1340  Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
1341  Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1342  Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1343  Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1344  Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1345  Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1346  Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1347  Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1348  Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1349 
1350  Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
1351 
1352  // Miscellaneous memory related features, detected by
1353  // using the 0x80000008 leaf of the CPUID instruction
1354  bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1355  !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1356  Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1357  Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1358 
1359  bool HasLeaf7 =
1360  MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1361 
1362  Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1363  Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1364  Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1365  // AVX2 is only supported if we have the OS save support from AVX.
1366  Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
1367  Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1368  Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1369  Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1370  Features["mpx"] = HasLeaf7 && ((EBX >> 14) & 1);
1371  // AVX512 is only supported if the OS supports the context save for it.
1372  Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1373  Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1374  Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1375  Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1376  Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1377  Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1378  Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1379  Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1380  Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1381  Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1382  Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1383  Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1384  Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1385 
1386  Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1);
1387  Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1388  Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1389  Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
1390  Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
1391  Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
1392  Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
1393  Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
1394  Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1395  Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1396  Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1397  Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1398  Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
1399  Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
1400  Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
1401  Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
1402  Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
1403 
1404  // There are two CPUID leafs which information associated with the pconfig
1405  // instruction:
1406  // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1407  // bit of EDX), while the EAX=0x1b leaf returns information on the
1408  // availability of specific pconfig leafs.
1409  // The target feature here only refers to the the first of these two.
1410  // Users might need to check for the availability of specific pconfig
1411  // leaves using cpuid, since that information is ignored while
1412  // detecting features using the "-march=native" flag.
1413  // For more info, see X86 ISA docs.
1414  Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1415  bool HasLeaf7Subleaf1 =
1416  MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1417  Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
1418 
1419  bool HasLeafD = MaxLevel >= 0xd &&
1420  !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1421 
1422  // Only enable XSAVE if OS has enabled support for saving YMM state.
1423  Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1424  Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1425  Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1426 
1427  bool HasLeaf14 = MaxLevel >= 0x14 &&
1428  !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1429 
1430  Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1431 
1432  return true;
1433 }
1434 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1435 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1436  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1437  if (!P)
1438  return false;
1439 
1441  P->getBuffer().split(Lines, "\n");
1442 
1443  SmallVector<StringRef, 32> CPUFeatures;
1444 
1445  // Look for the CPU features.
1446  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1447  if (Lines[I].startswith("Features")) {
1448  Lines[I].split(CPUFeatures, ' ');
1449  break;
1450  }
1451 
1452 #if defined(__aarch64__)
1453  // Keep track of which crypto features we have seen
1454  enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1455  uint32_t crypto = 0;
1456 #endif
1457 
1458  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1459  StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1460 #if defined(__aarch64__)
1461  .Case("asimd", "neon")
1462  .Case("fp", "fp-armv8")
1463  .Case("crc32", "crc")
1464 #else
1465  .Case("half", "fp16")
1466  .Case("neon", "neon")
1467  .Case("vfpv3", "vfp3")
1468  .Case("vfpv3d16", "d16")
1469  .Case("vfpv4", "vfp4")
1470  .Case("idiva", "hwdiv-arm")
1471  .Case("idivt", "hwdiv")
1472 #endif
1473  .Default("");
1474 
1475 #if defined(__aarch64__)
1476  // We need to check crypto separately since we need all of the crypto
1477  // extensions to enable the subtarget feature
1478  if (CPUFeatures[I] == "aes")
1479  crypto |= CAP_AES;
1480  else if (CPUFeatures[I] == "pmull")
1481  crypto |= CAP_PMULL;
1482  else if (CPUFeatures[I] == "sha1")
1483  crypto |= CAP_SHA1;
1484  else if (CPUFeatures[I] == "sha2")
1485  crypto |= CAP_SHA2;
1486 #endif
1487 
1488  if (LLVMFeatureStr != "")
1489  Features[LLVMFeatureStr] = true;
1490  }
1491 
1492 #if defined(__aarch64__)
1493  // If we have all crypto bits we can add the feature
1494  if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1495  Features["crypto"] = true;
1496 #endif
1497 
1498  return true;
1499 }
1500 #else
1501 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1502 #endif
1503 
1504 std::string sys::getProcessTriple() {
1505  std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1506  Triple PT(Triple::normalize(TargetTripleString));
1507 
1508  if (sizeof(void *) == 8 && PT.isArch32Bit())
1509  PT = PT.get64BitArchVariant();
1510  if (sizeof(void *) == 4 && PT.isArch64Bit())
1511  PT = PT.get32BitArchVariant();
1512 
1513  return PT.str();
1514 }
Represents either an error or a value T.
Definition: ErrorOr.h:56
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
Definition: Host.cpp:56
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:267
This class represents lattice values for constants.
Definition: AllocatorList.h:23
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
Definition: Host.cpp:67
F(f)
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
Definition: Host.cpp:282
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
int getHostNumPhysicalCores()
Get the number of physical cores (as opposed to logical cores returned from thread::hardware_concurre...
Definition: Host.cpp:1282
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:29
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1294
const std::string & str() const
Definition: Triple.h:364
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1258
#define P(N)
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
Definition: Triple.cpp:1302
StringRef getHostCPUNameForBPF()
Definition: Host.cpp:335
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
std::error_code getError() const
Definition: ErrorOr.h:159
size_type size() const
Definition: SmallSet.h:159
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:159
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
size_t size() const
Definition: SmallVector.h:52
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
Definition: Host.cpp:1504
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
std::string normalize() const
Return the normalized form of this triple&#39;s string.
Definition: Triple.h:288
iterator begin() const
Definition: StringRef.h:101
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
Definition: Host.cpp:1210
static const size_t npos
Definition: StringRef.h:50
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1290
#define I(x, y, z)
Definition: MD5.cpp:58
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
Definition: Host.cpp:146
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
Definition: Triple.cpp:1366
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool getHostCPUFeatures(StringMap< bool > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
Definition: Host.cpp:1501
iterator end() const
Definition: StringRef.h:103
static int computeHostNumPhysicalCores()
Definition: Host.cpp:1279