LLVM 22.0.0git
CSKYAsmBackend.h
Go to the documentation of this file.
1//===-- CSKYAsmBackend.h - CSKY Assembler Backend -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYASMBACKEND_H
10#define LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYASMBACKEND_H
11
16
17namespace llvm {
18
20
21public:
24
25 std::optional<bool> evaluateFixup(const MCFragment &, MCFixup &, MCValue &,
26 uint64_t &) override;
27 void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target,
28 uint8_t *Data, uint64_t Value, bool IsResolved) override;
29
30 MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override;
31
33 uint64_t Value) const override;
34
36 const MCSubtargetInfo &STI) const override;
37 void relaxInstruction(MCInst &Inst,
38 const MCSubtargetInfo &STI) const override;
39
41 const MCValue &, uint64_t,
42 bool) const override;
43
45 const MCSubtargetInfo *STI) const override;
46
48
49 std::unique_ptr<MCObjectTargetWriter>
50 createObjectTargetWriter() const override;
51};
52} // namespace llvm
53
54#endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYASMBACKEND_H
mir Rename Register Operands
PowerPC TLS Dynamic Call Fixup
raw_pwrite_stream & OS
#define OP(OPC)
Definition: Instruction.h:46
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool shouldForceRelocation(const MCFixup &Fixup, const MCValue &Target)
MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
bool fixupNeedsRelaxationAdvanced(const MCFragment &, const MCFixup &, const MCValue &, uint64_t, bool) const override
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
CSKYAsmBackend(const MCSubtargetInfo &STI, const MCTargetOptions &OP)
std::optional< bool > evaluateFixup(const MCFragment &, MCFixup &, MCValue &, uint64_t &) override
bool mayNeedRelaxation(unsigned Opcode, ArrayRef< MCOperand > Operands, const MCSubtargetInfo &STI) const override
Check whether the given instruction (encoded as Opcode+Operands) may need relaxation.
void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, uint8_t *Data, uint64_t Value, bool IsResolved) override
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:55
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:61
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:188
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:75
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
endianness
Definition: bit.h:71
Target independent information on a fixup kind.
Definition: MCAsmBackend.h:38