16#ifndef LLVM_MCA_STAGES_MICROOPQUEUESTAGE_H
17#define LLVM_MCA_STAGES_MICROOPQUEUESTAGE_H
28 unsigned NextAvailableSlotIdx;
29 unsigned CurrentInstructionSlotIdx;
34 const unsigned MaxIPC;
38 unsigned AvailableEntries;
43 bool IsZeroLatencyStage;
54 unsigned getNormalizedOpcodes(
const InstRef &
IR)
const {
55 unsigned NormalizedOpcodes =
56 std::min(
static_cast<unsigned>(Buffer.
size()),
57 IR.getInstruction()->getDesc().NumMicroOps);
58 return NormalizedOpcodes ? NormalizedOpcodes : 1U;
61 Error moveInstructions();
65 bool ZeroLatencyStage =
true);
68 if (MaxIPC && CurrentIPC == MaxIPC)
70 unsigned NormalizedOpcodes = getNormalizedOpcodes(
IR);
71 if (NormalizedOpcodes > AvailableEntries)
77 return AvailableEntries != Buffer.
size();
Legalize the Machine IR a function s Machine IR
This file defines the SmallVector class.
This file defines a stage.
Lightweight error class with error context and mandatory checking.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An InstRef contains both a SourceMgr index and Instruction pair.
A stage that simulates a queue of instruction opcodes.
bool isAvailable(const InstRef &IR) const override
Returns true if it can execute IR during this cycle.
Error cycleEnd() override
Called once at the end of each cycle.
bool hasWorkToComplete() const override
Returns true if some instructions are still executing this stage.
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
Error cycleStart() override
Called once at the start of each cycle.
This is an optimization pass for GlobalISel generic memory operations.