RISCVAsmBackend.cpp File Reference

#include "RISCVAsmBackend.h"
#include "RISCVMCExpr.h"
#include "llvm/ADT/APInt.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCValue.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/EndianStream.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
#include "llvm/BinaryFormat/ELFRelocs/RISCV_nonstandard.def"

Go to the source code of this file.

Macros
#define	ELF_RELOC(NAME, ID)   .Case(#NAME, ID)
#define	ELF_RISCV_NONSTANDARD_RELOC(_VENDOR, NAME, ID)   .Case(#NAME, ID)

Functions
static uint64_t	adjustFixupValue (const MCFixup &Fixup, uint64_t Value, MCContext &Ctx)

Variables
static cl::opt< bool >	RelaxBranches ("riscv-asm-relax-branches", cl::init(true), cl::Hidden)
static cl::opt< bool >	ULEB128Reloc ("riscv-uleb128-reloc", cl::init(true), cl::Hidden, cl::desc("Emit R_RISCV_SET_ULEB128/E_RISCV_SUB_ULEB128 if appropriate"))

Macro Definition Documentation

ELF_RELOC

#define ELF_RELOC	(		NAME,
			ID
	)		.Case(#NAME, ID)

ELF_RISCV_NONSTANDARD_RELOC

#define ELF_RISCV_NONSTANDARD_RELOC	(		_VENDOR,
			NAME,
			ID
	)		.Case(#NAME, ID)

Function Documentation

adjustFixupValue()

static uint64_t adjustFixupValue ( const MCFixup &  Fixup, uint64_t  Value, MCContext &  Ctx  )

static

Definition at line 408 of file RISCVAsmBackend.cpp.

References Fixup, llvm::RISCV::fixup_riscv_12_i, llvm::RISCV::fixup_riscv_branch, llvm::RISCV::fixup_riscv_call, llvm::RISCV::fixup_riscv_call_plt, llvm::RISCV::fixup_riscv_got_hi20, llvm::RISCV::fixup_riscv_hi20, llvm::RISCV::fixup_riscv_jal, llvm::RISCV::fixup_riscv_lo12_i, llvm::RISCV::fixup_riscv_lo12_s, llvm::RISCV::fixup_riscv_pcrel_hi20, llvm::RISCV::fixup_riscv_pcrel_lo12_i, llvm::RISCV::fixup_riscv_pcrel_lo12_s, llvm::RISCV::fixup_riscv_rvc_branch, llvm::RISCV::fixup_riscv_rvc_jump, llvm::RISCV::fixup_riscv_tls_gd_hi20, llvm::RISCV::fixup_riscv_tls_got_hi20, llvm::RISCV::fixup_riscv_tlsdesc_hi20, llvm::RISCV::fixup_riscv_tlsdesc_load_lo12, llvm::RISCV::fixup_riscv_tprel_hi20, llvm::RISCV::fixup_riscv_tprel_lo12_i, llvm::RISCV::fixup_riscv_tprel_lo12_s, llvm::FK_Data_1, llvm::FK_Data_2, llvm::FK_Data_4, llvm::FK_Data_8, llvm::FK_Data_leb128, llvm_unreachable, and llvm::MCContext::reportError().

Variable Documentation

RelaxBranches

cl::opt< bool > RelaxBranches("riscv-asm-relax-branches", cl::init(true), cl::Hidden) ( "riscv-asm-relax-branches"  , cl::init(true)  , cl::Hidden    )

static

Referenced by llvm::RISCVAsmBackend::fixupNeedsRelaxationAdvanced().

ULEB128Reloc

cl::opt< bool > ULEB128Reloc("riscv-uleb128-reloc", cl::init(true), cl::Hidden, cl::desc("Emit R_RISCV_SET_ULEB128/E_RISCV_SUB_ULEB128 if appropriate")) ( "riscv-uleb128-reloc"  , cl::init(true)  , cl::Hidden  , cl::desc("Emit R_RISCV_SET_ULEB128/E_RISCV_SUB_ULEB128 if appropriate")    )

static

Referenced by llvm::RISCVAsmBackend::relaxLEB128().