17#define DEBUG_TYPE "llvm-mca"
23 : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
24 AvailableEntries(SM.isOutOfOrder() ? SM.MicroOpBufferSize : 0),
25 MaxRetirePerCycle(0) {
27 "RetireControlUnit is not available for in-order processors");
37 NumROBEntries = AvailableEntries;
38 assert(NumROBEntries &&
"Invalid reorder buffer size!");
39 Queue.resize(2 * NumROBEntries);
46 assert((AvailableEntries >= Entries) &&
"Reorder Buffer unavailable!");
48 unsigned TokenID = NextAvailableSlotIdx;
49 Queue[NextAvailableSlotIdx] = {
IR, Entries,
false};
50 NextAvailableSlotIdx += std::max(1U, Entries);
51 NextAvailableSlotIdx %= Queue.size();
54 AvailableEntries -= Entries;
62 assert(Inst &&
"Invalid RUToken in the RCU queue.");
67unsigned RetireControlUnit::computeNextSlotIdx()
const {
69 unsigned NextSlotIdx = CurrentInstructionSlotIdx + std::max(1U, Current.
NumSlots);
70 return NextSlotIdx % Queue.size();
74 return Queue[computeNextSlotIdx()];
82 CurrentInstructionSlotIdx += std::max(1U, Current.
NumSlots);
83 CurrentInstructionSlotIdx %= Queue.size();
84 AvailableEntries += Current.
NumSlots;
85 Current = {
InstRef(), 0U,
false };
89 assert(Queue.size() > TokenID);
90 assert(Queue[TokenID].
IR.getInstruction() &&
"Instruction was not dispatched!");
91 assert(Queue[TokenID].Executed ==
false &&
"Instruction already executed!");
92 Queue[TokenID].Executed =
true;
97 dbgs() <<
"Retire Unit: { Total ROB Entries =" << NumROBEntries
98 <<
", Available ROB entries=" << AvailableEntries <<
" }\n";
Legalize the Machine IR a function s Machine IR
This file simulates the hardware responsible for retiring instructions.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
An InstRef contains both a SourceMgr index and Instruction pair.
Instruction * getInstruction()
unsigned getNumMicroOps() const
An instruction propagated through the simulated instruction pipeline.
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Machine model for scheduling, bundling, and heuristics.
bool isOutOfOrder() const
Return true if machine supports out of order execution.
bool hasExtraProcessorInfo() const
const MCExtraProcessorInfo & getExtraProcessorInfo() const
static const unsigned UnhandledTokenID
RetireControlUnit(const MCSchedModel &SM)
void onInstructionExecuted(unsigned TokenID)
const RUToken & getCurrentToken() const
unsigned dispatch(const InstRef &IS)
const RUToken & peekNextToken() const
void consumeCurrentToken()