14#ifndef LLVM_MCA_HARDWAREUNITS_RETIRECONTROLUNIT_H
15#define LLVM_MCA_HARDWAREUNITS_RETIRECONTROLUNIT_H
58 unsigned NextAvailableSlotIdx;
59 unsigned CurrentInstructionSlotIdx;
60 unsigned NumROBEntries;
61 unsigned AvailableEntries;
62 unsigned MaxRetirePerCycle;
63 std::vector<RUToken> Queue;
65 unsigned normalizeQuantity(
unsigned Quantity)
const {
69 Quantity = std::min(Quantity, NumROBEntries);
74 return std::max(Quantity, 1U);
77 unsigned computeNextSlotIdx()
const;
82 bool isEmpty()
const {
return AvailableEntries == NumROBEntries; }
85 return AvailableEntries >= normalizeQuantity(Quantity);
This file defines a base class for describing a simulated hardware unit.
This file defines abstractions used by the Pipeline to model register reads, register writes and inst...
An InstRef contains both a SourceMgr index and Instruction pair.
This is an optimization pass for GlobalISel generic memory operations.
Machine model for scheduling, bundling, and heuristics.
This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO back...
bool isAvailable(unsigned Quantity=1) const
unsigned getMaxRetirePerCycle() const
static const unsigned UnhandledTokenID
void onInstructionExecuted(unsigned TokenID)
const RUToken & getCurrentToken() const
unsigned dispatch(const InstRef &IS)
const RUToken & peekNextToken() const
void consumeCurrentToken()