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PPCTargetMachine.cpp
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00001 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // Top-level implementation for the PowerPC target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "PPCTargetMachine.h"
00015 #include "PPC.h"
00016 #include "PPCTargetObjectFile.h"
00017 #include "PPCTargetTransformInfo.h"
00018 #include "llvm/CodeGen/Passes.h"
00019 #include "llvm/IR/Function.h"
00020 #include "llvm/IR/LegacyPassManager.h"
00021 #include "llvm/MC/MCStreamer.h"
00022 #include "llvm/Support/CommandLine.h"
00023 #include "llvm/Support/FormattedStream.h"
00024 #include "llvm/Support/TargetRegistry.h"
00025 #include "llvm/Target/TargetOptions.h"
00026 #include "llvm/Transforms/Scalar.h"
00027 using namespace llvm;
00028 
00029 static cl::
00030 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
00031                         cl::desc("Disable CTR loops for PPC"));
00032 
00033 static cl::
00034 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
00035                             cl::desc("Disable PPC loop preinc prep"));
00036 
00037 static cl::opt<bool>
00038 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
00039   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
00040 
00041 static cl::
00042 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
00043                                 cl::desc("Disable VSX Swap Removal for PPC"));
00044 
00045 static cl::opt<bool>
00046 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
00047              cl::desc("Enable optimizations on complex GEPs"),
00048              cl::init(true));
00049 
00050 static cl::opt<bool>
00051 EnablePrefetch("enable-ppc-prefetching",
00052                   cl::desc("disable software prefetching on PPC"),
00053                   cl::init(false), cl::Hidden);
00054 
00055 extern "C" void LLVMInitializePowerPCTarget() {
00056   // Register the targets
00057   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
00058   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
00059   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
00060 }
00061 
00062 /// Return the datalayout string of a subtarget.
00063 static std::string getDataLayoutString(const Triple &T) {
00064   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
00065   std::string Ret;
00066 
00067   // Most PPC* platforms are big endian, PPC64LE is little endian.
00068   if (T.getArch() == Triple::ppc64le)
00069     Ret = "e";
00070   else
00071     Ret = "E";
00072 
00073   Ret += DataLayout::getManglingComponent(T);
00074 
00075   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
00076   // pointers.
00077   if (!is64Bit || T.getOS() == Triple::Lv2)
00078     Ret += "-p:32:32";
00079 
00080   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
00081   // documentation are wrong; these are correct (i.e. "what gcc does").
00082   if (is64Bit || !T.isOSDarwin())
00083     Ret += "-i64:64";
00084   else
00085     Ret += "-f64:32:64";
00086 
00087   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
00088   if (is64Bit)
00089     Ret += "-n32:64";
00090   else
00091     Ret += "-n32";
00092 
00093   return Ret;
00094 }
00095 
00096 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
00097   std::string FullFS = FS;
00098   Triple TargetTriple(TT);
00099 
00100   // Make sure 64-bit features are available when CPUname is generic
00101   if (TargetTriple.getArch() == Triple::ppc64 ||
00102       TargetTriple.getArch() == Triple::ppc64le) {
00103     if (!FullFS.empty())
00104       FullFS = "+64bit," + FullFS;
00105     else
00106       FullFS = "+64bit";
00107   }
00108 
00109   if (OL >= CodeGenOpt::Default) {
00110     if (!FullFS.empty())
00111       FullFS = "+crbits," + FullFS;
00112     else
00113       FullFS = "+crbits";
00114   }
00115 
00116   if (OL != CodeGenOpt::None) {
00117      if (!FullFS.empty())
00118       FullFS = "+invariant-function-descriptors," + FullFS;
00119     else
00120       FullFS = "+invariant-function-descriptors";
00121   }
00122 
00123   return FullFS;
00124 }
00125 
00126 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
00127   // If it isn't a Mach-O file then it's going to be a linux ELF
00128   // object file.
00129   if (TT.isOSDarwin())
00130     return make_unique<TargetLoweringObjectFileMachO>();
00131 
00132   return make_unique<PPC64LinuxTargetObjectFile>();
00133 }
00134 
00135 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
00136                                                  const TargetOptions &Options) {
00137   if (Options.MCOptions.getABIName().startswith("elfv1"))
00138     return PPCTargetMachine::PPC_ABI_ELFv1;
00139   else if (Options.MCOptions.getABIName().startswith("elfv2"))
00140     return PPCTargetMachine::PPC_ABI_ELFv2;
00141 
00142   assert(Options.MCOptions.getABIName().empty() &&
00143    "Unknown target-abi option!");
00144 
00145   if (!TT.isMacOSX()) {
00146     switch (TT.getArch()) {
00147     case Triple::ppc64le:
00148       return PPCTargetMachine::PPC_ABI_ELFv2;
00149     case Triple::ppc64:
00150       return PPCTargetMachine::PPC_ABI_ELFv1;
00151     default:
00152       // Fallthrough.
00153       ;
00154     }
00155   }
00156   return PPCTargetMachine::PPC_ABI_UNKNOWN;
00157 }
00158 
00159 // The FeatureString here is a little subtle. We are modifying the feature string
00160 // with what are (currently) non-function specific overrides as it goes into the
00161 // LLVMTargetMachine constructor and then using the stored value in the
00162 // Subtarget constructor below it.
00163 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
00164                                    StringRef FS, const TargetOptions &Options,
00165                                    Reloc::Model RM, CodeModel::Model CM,
00166                                    CodeGenOpt::Level OL)
00167     : LLVMTargetMachine(T, getDataLayoutString(Triple(TT)), TT, CPU,
00168                         computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
00169       TLOF(createTLOF(Triple(getTargetTriple()))),
00170       TargetABI(computeTargetABI(Triple(TT), Options)) {
00171   initAsmInfo();
00172 }
00173 
00174 PPCTargetMachine::~PPCTargetMachine() {}
00175 
00176 void PPC32TargetMachine::anchor() { }
00177 
00178 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
00179                                        StringRef CPU, StringRef FS,
00180                                        const TargetOptions &Options,
00181                                        Reloc::Model RM, CodeModel::Model CM,
00182                                        CodeGenOpt::Level OL)
00183   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
00184 }
00185 
00186 void PPC64TargetMachine::anchor() { }
00187 
00188 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
00189                                        StringRef CPU,  StringRef FS,
00190                                        const TargetOptions &Options,
00191                                        Reloc::Model RM, CodeModel::Model CM,
00192                                        CodeGenOpt::Level OL)
00193   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
00194 }
00195 
00196 const PPCSubtarget *
00197 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
00198   Attribute CPUAttr = F.getFnAttribute("target-cpu");
00199   Attribute FSAttr = F.getFnAttribute("target-features");
00200 
00201   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
00202                         ? CPUAttr.getValueAsString().str()
00203                         : TargetCPU;
00204   std::string FS = !FSAttr.hasAttribute(Attribute::None)
00205                        ? FSAttr.getValueAsString().str()
00206                        : TargetFS;
00207 
00208   auto &I = SubtargetMap[CPU + FS];
00209   if (!I) {
00210     // This needs to be done before we create a new subtarget since any
00211     // creation will depend on the TM and the code generation flags on the
00212     // function that reside in TargetOptions.
00213     resetTargetOptions(F);
00214     I = llvm::make_unique<PPCSubtarget>(
00215         TargetTriple, CPU,
00216         // FIXME: It would be good to have the subtarget additions here
00217         // not necessary. Anything that turns them on/off (overrides) ends
00218         // up being put at the end of the feature string, but the defaults
00219         // shouldn't require adding them. Fixing this means pulling Feature64Bit
00220         // out of most of the target cpus in the .td file and making it set only
00221         // as part of initialization via the TargetTriple.
00222         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
00223   }
00224   return I.get();
00225 }
00226 
00227 //===----------------------------------------------------------------------===//
00228 // Pass Pipeline Configuration
00229 //===----------------------------------------------------------------------===//
00230 
00231 namespace {
00232 /// PPC Code Generator Pass Configuration Options.
00233 class PPCPassConfig : public TargetPassConfig {
00234 public:
00235   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
00236     : TargetPassConfig(TM, PM) {}
00237 
00238   PPCTargetMachine &getPPCTargetMachine() const {
00239     return getTM<PPCTargetMachine>();
00240   }
00241 
00242   void addIRPasses() override;
00243   bool addPreISel() override;
00244   bool addILPOpts() override;
00245   bool addInstSelector() override;
00246   void addMachineSSAOptimization() override;
00247   void addPreRegAlloc() override;
00248   void addPreSched2() override;
00249   void addPreEmitPass() override;
00250 };
00251 } // namespace
00252 
00253 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
00254   return new PPCPassConfig(this, PM);
00255 }
00256 
00257 void PPCPassConfig::addIRPasses() {
00258   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
00259 
00260   // For the BG/Q (or if explicitly requested), add explicit data prefetch
00261   // intrinsics.
00262   bool UsePrefetching =
00263     Triple(TM->getTargetTriple()).getVendor() == Triple::BGQ &&           
00264     getOptLevel() != CodeGenOpt::None;
00265   if (EnablePrefetch.getNumOccurrences() > 0)
00266     UsePrefetching = EnablePrefetch;
00267   if (UsePrefetching)
00268     addPass(createPPCLoopDataPrefetchPass());
00269 
00270   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
00271     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
00272     // and lower a GEP with multiple indices to either arithmetic operations or
00273     // multiple GEPs with single index.
00274     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
00275     // Call EarlyCSE pass to find and remove subexpressions in the lowered
00276     // result.
00277     addPass(createEarlyCSEPass());
00278     // Do loop invariant code motion in case part of the lowered result is
00279     // invariant.
00280     addPass(createLICMPass());
00281   }
00282 
00283   TargetPassConfig::addIRPasses();
00284 }
00285 
00286 bool PPCPassConfig::addPreISel() {
00287   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
00288     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
00289 
00290   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
00291     addPass(createPPCCTRLoops(getPPCTargetMachine()));
00292 
00293   return false;
00294 }
00295 
00296 bool PPCPassConfig::addILPOpts() {
00297   addPass(&EarlyIfConverterID);
00298   return true;
00299 }
00300 
00301 bool PPCPassConfig::addInstSelector() {
00302   // Install an instruction selector.
00303   addPass(createPPCISelDag(getPPCTargetMachine()));
00304 
00305 #ifndef NDEBUG
00306   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
00307     addPass(createPPCCTRLoopsVerify());
00308 #endif
00309 
00310   addPass(createPPCVSXCopyPass());
00311   return false;
00312 }
00313 
00314 void PPCPassConfig::addMachineSSAOptimization() {
00315   TargetPassConfig::addMachineSSAOptimization();
00316   // For little endian, remove where possible the vector swap instructions
00317   // introduced at code generation to normalize vector element order.
00318   if (Triple(TM->getTargetTriple()).getArch() == Triple::ppc64le &&
00319       !DisableVSXSwapRemoval)
00320     addPass(createPPCVSXSwapRemovalPass());
00321 }
00322 
00323 void PPCPassConfig::addPreRegAlloc() {
00324   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
00325   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
00326              &PPCVSXFMAMutateID);
00327   if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
00328     addPass(createPPCTLSDynamicCallPass());
00329 }
00330 
00331 void PPCPassConfig::addPreSched2() {
00332   if (getOptLevel() != CodeGenOpt::None)
00333     addPass(&IfConverterID);
00334 }
00335 
00336 void PPCPassConfig::addPreEmitPass() {
00337   if (getOptLevel() != CodeGenOpt::None)
00338     addPass(createPPCEarlyReturnPass(), false);
00339   // Must run branch selection immediately preceding the asm printer.
00340   addPass(createPPCBranchSelectionPass(), false);
00341 }
00342 
00343 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
00344   return TargetIRAnalysis(
00345       [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });
00346 }