LLVM API Documentation

PPCTargetMachine.cpp
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00001 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // Top-level implementation for the PowerPC target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "PPCTargetMachine.h"
00015 #include "PPC.h"
00016 #include "llvm/CodeGen/Passes.h"
00017 #include "llvm/IR/Function.h"
00018 #include "llvm/MC/MCStreamer.h"
00019 #include "llvm/PassManager.h"
00020 #include "llvm/Support/CommandLine.h"
00021 #include "llvm/Support/FormattedStream.h"
00022 #include "llvm/Support/TargetRegistry.h"
00023 #include "llvm/Target/TargetOptions.h"
00024 using namespace llvm;
00025 
00026 static cl::
00027 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
00028                         cl::desc("Disable CTR loops for PPC"));
00029 
00030 static cl::opt<bool>
00031 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
00032   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
00033 
00034 extern "C" void LLVMInitializePowerPCTarget() {
00035   // Register the targets
00036   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
00037   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
00038   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
00039 }
00040 
00041 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
00042   std::string FullFS = FS;
00043   Triple TargetTriple(TT);
00044 
00045   // Make sure 64-bit features are available when CPUname is generic
00046   if (TargetTriple.getArch() == Triple::ppc64 ||
00047       TargetTriple.getArch() == Triple::ppc64le) {
00048     if (!FullFS.empty())
00049       FullFS = "+64bit," + FullFS;
00050     else
00051       FullFS = "+64bit";
00052   }
00053 
00054   if (OL >= CodeGenOpt::Default) {
00055     if (!FullFS.empty())
00056       FullFS = "+crbits," + FullFS;
00057     else
00058       FullFS = "+crbits";
00059   }
00060   return FullFS;
00061 }
00062 
00063 // The FeatureString here is a little subtle. We are modifying the feature string
00064 // with what are (currently) non-function specific overrides as it goes into the
00065 // LLVMTargetMachine constructor and then using the stored value in the
00066 // Subtarget constructor below it.
00067 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
00068                                    StringRef FS, const TargetOptions &Options,
00069                                    Reloc::Model RM, CodeModel::Model CM,
00070                                    CodeGenOpt::Level OL)
00071     : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
00072                         CM, OL),
00073       Subtarget(TT, CPU, TargetFS, *this) {
00074   initAsmInfo();
00075 }
00076 
00077 void PPC32TargetMachine::anchor() { }
00078 
00079 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
00080                                        StringRef CPU, StringRef FS,
00081                                        const TargetOptions &Options,
00082                                        Reloc::Model RM, CodeModel::Model CM,
00083                                        CodeGenOpt::Level OL)
00084   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
00085 }
00086 
00087 void PPC64TargetMachine::anchor() { }
00088 
00089 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
00090                                        StringRef CPU,  StringRef FS,
00091                                        const TargetOptions &Options,
00092                                        Reloc::Model RM, CodeModel::Model CM,
00093                                        CodeGenOpt::Level OL)
00094   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
00095 }
00096 
00097 const PPCSubtarget *
00098 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
00099   AttributeSet FnAttrs = F.getAttributes();
00100   Attribute CPUAttr =
00101       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
00102   Attribute FSAttr =
00103       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
00104 
00105   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
00106                         ? CPUAttr.getValueAsString().str()
00107                         : TargetCPU;
00108   std::string FS = !FSAttr.hasAttribute(Attribute::None)
00109                        ? FSAttr.getValueAsString().str()
00110                        : TargetFS;
00111 
00112   auto &I = SubtargetMap[CPU + FS];
00113   if (!I) {
00114     // This needs to be done before we create a new subtarget since any
00115     // creation will depend on the TM and the code generation flags on the
00116     // function that reside in TargetOptions.
00117     resetTargetOptions(F);
00118     I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
00119   }
00120   return I.get();
00121 }
00122 
00123 //===----------------------------------------------------------------------===//
00124 // Pass Pipeline Configuration
00125 //===----------------------------------------------------------------------===//
00126 
00127 namespace {
00128 /// PPC Code Generator Pass Configuration Options.
00129 class PPCPassConfig : public TargetPassConfig {
00130 public:
00131   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
00132     : TargetPassConfig(TM, PM) {}
00133 
00134   PPCTargetMachine &getPPCTargetMachine() const {
00135     return getTM<PPCTargetMachine>();
00136   }
00137 
00138   const PPCSubtarget &getPPCSubtarget() const {
00139     return *getPPCTargetMachine().getSubtargetImpl();
00140   }
00141 
00142   void addIRPasses() override;
00143   bool addPreISel() override;
00144   bool addILPOpts() override;
00145   bool addInstSelector() override;
00146   bool addPreRegAlloc() override;
00147   bool addPreSched2() override;
00148   bool addPreEmitPass() override;
00149 };
00150 } // namespace
00151 
00152 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
00153   return new PPCPassConfig(this, PM);
00154 }
00155 
00156 void PPCPassConfig::addIRPasses() {
00157   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
00158   TargetPassConfig::addIRPasses();
00159 }
00160 
00161 bool PPCPassConfig::addPreISel() {
00162   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
00163     addPass(createPPCCTRLoops(getPPCTargetMachine()));
00164 
00165   return false;
00166 }
00167 
00168 bool PPCPassConfig::addILPOpts() {
00169   addPass(&EarlyIfConverterID);
00170   return true;
00171 }
00172 
00173 bool PPCPassConfig::addInstSelector() {
00174   // Install an instruction selector.
00175   addPass(createPPCISelDag(getPPCTargetMachine()));
00176 
00177 #ifndef NDEBUG
00178   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
00179     addPass(createPPCCTRLoopsVerify());
00180 #endif
00181 
00182   addPass(createPPCVSXCopyPass());
00183   return false;
00184 }
00185 
00186 bool PPCPassConfig::addPreRegAlloc() {
00187   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
00188   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
00189              &PPCVSXFMAMutateID);
00190   return false;
00191 }
00192 
00193 bool PPCPassConfig::addPreSched2() {
00194   addPass(createPPCVSXCopyCleanupPass());
00195 
00196   if (getOptLevel() != CodeGenOpt::None)
00197     addPass(&IfConverterID);
00198 
00199   return true;
00200 }
00201 
00202 bool PPCPassConfig::addPreEmitPass() {
00203   if (getOptLevel() != CodeGenOpt::None)
00204     addPass(createPPCEarlyReturnPass());
00205   // Must run branch selection immediately preceding the asm printer.
00206   addPass(createPPCBranchSelectionPass());
00207   return false;
00208 }
00209 
00210 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
00211   // Add first the target-independent BasicTTI pass, then our PPC pass. This
00212   // allows the PPC pass to delegate to the target independent layer when
00213   // appropriate.
00214   PM.add(createBasicTargetTransformInfoPass(this));
00215   PM.add(createPPCTargetTransformInfoPass(this));
00216 }
00217