LLVM API Documentation

PPCTargetMachine.cpp
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00001 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // Top-level implementation for the PowerPC target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "PPCTargetMachine.h"
00015 #include "PPCTargetObjectFile.h"
00016 #include "PPC.h"
00017 #include "llvm/CodeGen/Passes.h"
00018 #include "llvm/IR/Function.h"
00019 #include "llvm/MC/MCStreamer.h"
00020 #include "llvm/PassManager.h"
00021 #include "llvm/Support/CommandLine.h"
00022 #include "llvm/Support/FormattedStream.h"
00023 #include "llvm/Support/TargetRegistry.h"
00024 #include "llvm/Target/TargetOptions.h"
00025 #include "llvm/Transforms/Scalar.h"
00026 using namespace llvm;
00027 
00028 static cl::
00029 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
00030                         cl::desc("Disable CTR loops for PPC"));
00031 
00032 static cl::opt<bool>
00033 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
00034   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
00035 
00036 static cl::opt<bool>
00037 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
00038              cl::desc("Enable optimizations on complex GEPs"),
00039              cl::init(true));
00040 
00041 extern "C" void LLVMInitializePowerPCTarget() {
00042   // Register the targets
00043   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
00044   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
00045   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
00046 }
00047 
00048 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
00049   std::string FullFS = FS;
00050   Triple TargetTriple(TT);
00051 
00052   // Make sure 64-bit features are available when CPUname is generic
00053   if (TargetTriple.getArch() == Triple::ppc64 ||
00054       TargetTriple.getArch() == Triple::ppc64le) {
00055     if (!FullFS.empty())
00056       FullFS = "+64bit," + FullFS;
00057     else
00058       FullFS = "+64bit";
00059   }
00060 
00061   if (OL >= CodeGenOpt::Default) {
00062     if (!FullFS.empty())
00063       FullFS = "+crbits," + FullFS;
00064     else
00065       FullFS = "+crbits";
00066   }
00067   return FullFS;
00068 }
00069 
00070 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
00071   // If it isn't a Mach-O file then it's going to be a linux ELF
00072   // object file.
00073   if (TT.isOSDarwin())
00074     return make_unique<TargetLoweringObjectFileMachO>();
00075 
00076   return make_unique<PPC64LinuxTargetObjectFile>();
00077 }
00078 
00079 // The FeatureString here is a little subtle. We are modifying the feature string
00080 // with what are (currently) non-function specific overrides as it goes into the
00081 // LLVMTargetMachine constructor and then using the stored value in the
00082 // Subtarget constructor below it.
00083 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
00084                                    StringRef FS, const TargetOptions &Options,
00085                                    Reloc::Model RM, CodeModel::Model CM,
00086                                    CodeGenOpt::Level OL)
00087     : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
00088                         CM, OL),
00089       TLOF(createTLOF(Triple(getTargetTriple()))),
00090       Subtarget(TT, CPU, TargetFS, *this) {
00091   initAsmInfo();
00092 }
00093 
00094 PPCTargetMachine::~PPCTargetMachine() {}
00095 
00096 void PPC32TargetMachine::anchor() { }
00097 
00098 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
00099                                        StringRef CPU, StringRef FS,
00100                                        const TargetOptions &Options,
00101                                        Reloc::Model RM, CodeModel::Model CM,
00102                                        CodeGenOpt::Level OL)
00103   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
00104 }
00105 
00106 void PPC64TargetMachine::anchor() { }
00107 
00108 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
00109                                        StringRef CPU,  StringRef FS,
00110                                        const TargetOptions &Options,
00111                                        Reloc::Model RM, CodeModel::Model CM,
00112                                        CodeGenOpt::Level OL)
00113   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
00114 }
00115 
00116 const PPCSubtarget *
00117 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
00118   AttributeSet FnAttrs = F.getAttributes();
00119   Attribute CPUAttr =
00120       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
00121   Attribute FSAttr =
00122       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
00123 
00124   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
00125                         ? CPUAttr.getValueAsString().str()
00126                         : TargetCPU;
00127   std::string FS = !FSAttr.hasAttribute(Attribute::None)
00128                        ? FSAttr.getValueAsString().str()
00129                        : TargetFS;
00130 
00131   auto &I = SubtargetMap[CPU + FS];
00132   if (!I) {
00133     // This needs to be done before we create a new subtarget since any
00134     // creation will depend on the TM and the code generation flags on the
00135     // function that reside in TargetOptions.
00136     resetTargetOptions(F);
00137     I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
00138   }
00139   return I.get();
00140 }
00141 
00142 //===----------------------------------------------------------------------===//
00143 // Pass Pipeline Configuration
00144 //===----------------------------------------------------------------------===//
00145 
00146 namespace {
00147 /// PPC Code Generator Pass Configuration Options.
00148 class PPCPassConfig : public TargetPassConfig {
00149 public:
00150   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
00151     : TargetPassConfig(TM, PM) {}
00152 
00153   PPCTargetMachine &getPPCTargetMachine() const {
00154     return getTM<PPCTargetMachine>();
00155   }
00156 
00157   const PPCSubtarget &getPPCSubtarget() const {
00158     return *getPPCTargetMachine().getSubtargetImpl();
00159   }
00160 
00161   void addIRPasses() override;
00162   bool addPreISel() override;
00163   bool addILPOpts() override;
00164   bool addInstSelector() override;
00165   void addPreRegAlloc() override;
00166   void addPreSched2() override;
00167   void addPreEmitPass() override;
00168 };
00169 } // namespace
00170 
00171 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
00172   return new PPCPassConfig(this, PM);
00173 }
00174 
00175 void PPCPassConfig::addIRPasses() {
00176   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
00177 
00178   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
00179     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
00180     // and lower a GEP with multiple indices to either arithmetic operations or
00181     // multiple GEPs with single index.
00182     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
00183     // Call EarlyCSE pass to find and remove subexpressions in the lowered
00184     // result.
00185     addPass(createEarlyCSEPass());
00186     // Do loop invariant code motion in case part of the lowered result is
00187     // invariant.
00188     addPass(createLICMPass());
00189   }
00190 
00191   TargetPassConfig::addIRPasses();
00192 }
00193 
00194 bool PPCPassConfig::addPreISel() {
00195   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
00196     addPass(createPPCCTRLoops(getPPCTargetMachine()));
00197 
00198   return false;
00199 }
00200 
00201 bool PPCPassConfig::addILPOpts() {
00202   addPass(&EarlyIfConverterID);
00203   return true;
00204 }
00205 
00206 bool PPCPassConfig::addInstSelector() {
00207   // Install an instruction selector.
00208   addPass(createPPCISelDag(getPPCTargetMachine()));
00209 
00210 #ifndef NDEBUG
00211   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
00212     addPass(createPPCCTRLoopsVerify());
00213 #endif
00214 
00215   addPass(createPPCVSXCopyPass());
00216   return false;
00217 }
00218 
00219 void PPCPassConfig::addPreRegAlloc() {
00220   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
00221   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
00222              &PPCVSXFMAMutateID);
00223 }
00224 
00225 void PPCPassConfig::addPreSched2() {
00226   addPass(createPPCVSXCopyCleanupPass(), false);
00227 
00228   if (getOptLevel() != CodeGenOpt::None)
00229     addPass(&IfConverterID);
00230 }
00231 
00232 void PPCPassConfig::addPreEmitPass() {
00233   if (getOptLevel() != CodeGenOpt::None)
00234     addPass(createPPCEarlyReturnPass(), false);
00235   // Must run branch selection immediately preceding the asm printer.
00236   addPass(createPPCBranchSelectionPass(), false);
00237 }
00238 
00239 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
00240   // Add first the target-independent BasicTTI pass, then our PPC pass. This
00241   // allows the PPC pass to delegate to the target independent layer when
00242   // appropriate.
00243   PM.add(createBasicTargetTransformInfoPass(this));
00244   PM.add(createPPCTargetTransformInfoPass(this));
00245 }
00246