LLVM API Documentation

PPCTargetMachine.cpp
Go to the documentation of this file.
00001 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // Top-level implementation for the PowerPC target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "PPCTargetMachine.h"
00015 #include "PPC.h"
00016 #include "PPCTargetObjectFile.h"
00017 #include "llvm/CodeGen/Passes.h"
00018 #include "llvm/IR/Function.h"
00019 #include "llvm/MC/MCStreamer.h"
00020 #include "llvm/PassManager.h"
00021 #include "llvm/Support/CommandLine.h"
00022 #include "llvm/Support/FormattedStream.h"
00023 #include "llvm/Support/TargetRegistry.h"
00024 #include "llvm/Target/TargetOptions.h"
00025 #include "llvm/Transforms/Scalar.h"
00026 using namespace llvm;
00027 
00028 static cl::
00029 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
00030                         cl::desc("Disable CTR loops for PPC"));
00031 
00032 static cl::opt<bool>
00033 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
00034   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
00035 
00036 static cl::opt<bool>
00037 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
00038              cl::desc("Enable optimizations on complex GEPs"),
00039              cl::init(true));
00040 
00041 extern "C" void LLVMInitializePowerPCTarget() {
00042   // Register the targets
00043   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
00044   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
00045   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
00046 }
00047 
00048 /// Return the datalayout string of a subtarget.
00049 static std::string getDataLayoutString(const Triple &T) {
00050   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
00051   std::string Ret;
00052 
00053   // Most PPC* platforms are big endian, PPC64LE is little endian.
00054   if (T.getArch() == Triple::ppc64le)
00055     Ret = "e";
00056   else
00057     Ret = "E";
00058 
00059   Ret += DataLayout::getManglingComponent(T);
00060 
00061   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
00062   // pointers.
00063   if (!is64Bit || T.getOS() == Triple::Lv2)
00064     Ret += "-p:32:32";
00065 
00066   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
00067   // documentation are wrong; these are correct (i.e. "what gcc does").
00068   if (is64Bit || !T.isOSDarwin())
00069     Ret += "-i64:64";
00070   else
00071     Ret += "-f64:32:64";
00072 
00073   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
00074   if (is64Bit)
00075     Ret += "-n32:64";
00076   else
00077     Ret += "-n32";
00078 
00079   return Ret;
00080 }
00081 
00082 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
00083   std::string FullFS = FS;
00084   Triple TargetTriple(TT);
00085 
00086   // Make sure 64-bit features are available when CPUname is generic
00087   if (TargetTriple.getArch() == Triple::ppc64 ||
00088       TargetTriple.getArch() == Triple::ppc64le) {
00089     if (!FullFS.empty())
00090       FullFS = "+64bit," + FullFS;
00091     else
00092       FullFS = "+64bit";
00093   }
00094 
00095   if (OL >= CodeGenOpt::Default) {
00096     if (!FullFS.empty())
00097       FullFS = "+crbits," + FullFS;
00098     else
00099       FullFS = "+crbits";
00100   }
00101 
00102   if (OL != CodeGenOpt::None) {
00103      if (!FullFS.empty())
00104       FullFS = "+invariant-function-descriptors," + FullFS;
00105     else
00106       FullFS = "+invariant-function-descriptors";
00107   }
00108 
00109   return FullFS;
00110 }
00111 
00112 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
00113   // If it isn't a Mach-O file then it's going to be a linux ELF
00114   // object file.
00115   if (TT.isOSDarwin())
00116     return make_unique<TargetLoweringObjectFileMachO>();
00117 
00118   return make_unique<PPC64LinuxTargetObjectFile>();
00119 }
00120 
00121 // The FeatureString here is a little subtle. We are modifying the feature string
00122 // with what are (currently) non-function specific overrides as it goes into the
00123 // LLVMTargetMachine constructor and then using the stored value in the
00124 // Subtarget constructor below it.
00125 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
00126                                    StringRef FS, const TargetOptions &Options,
00127                                    Reloc::Model RM, CodeModel::Model CM,
00128                                    CodeGenOpt::Level OL)
00129     : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
00130                         CM, OL),
00131       TLOF(createTLOF(Triple(getTargetTriple()))),
00132       DL(getDataLayoutString(Triple(TT))), Subtarget(TT, CPU, TargetFS, *this) {
00133   initAsmInfo();
00134 }
00135 
00136 PPCTargetMachine::~PPCTargetMachine() {}
00137 
00138 void PPC32TargetMachine::anchor() { }
00139 
00140 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
00141                                        StringRef CPU, StringRef FS,
00142                                        const TargetOptions &Options,
00143                                        Reloc::Model RM, CodeModel::Model CM,
00144                                        CodeGenOpt::Level OL)
00145   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
00146 }
00147 
00148 void PPC64TargetMachine::anchor() { }
00149 
00150 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
00151                                        StringRef CPU,  StringRef FS,
00152                                        const TargetOptions &Options,
00153                                        Reloc::Model RM, CodeModel::Model CM,
00154                                        CodeGenOpt::Level OL)
00155   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
00156 }
00157 
00158 const PPCSubtarget *
00159 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
00160   AttributeSet FnAttrs = F.getAttributes();
00161   Attribute CPUAttr =
00162       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
00163   Attribute FSAttr =
00164       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
00165 
00166   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
00167                         ? CPUAttr.getValueAsString().str()
00168                         : TargetCPU;
00169   std::string FS = !FSAttr.hasAttribute(Attribute::None)
00170                        ? FSAttr.getValueAsString().str()
00171                        : TargetFS;
00172 
00173   auto &I = SubtargetMap[CPU + FS];
00174   if (!I) {
00175     // This needs to be done before we create a new subtarget since any
00176     // creation will depend on the TM and the code generation flags on the
00177     // function that reside in TargetOptions.
00178     resetTargetOptions(F);
00179     I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
00180   }
00181   return I.get();
00182 }
00183 
00184 //===----------------------------------------------------------------------===//
00185 // Pass Pipeline Configuration
00186 //===----------------------------------------------------------------------===//
00187 
00188 namespace {
00189 /// PPC Code Generator Pass Configuration Options.
00190 class PPCPassConfig : public TargetPassConfig {
00191 public:
00192   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
00193     : TargetPassConfig(TM, PM) {}
00194 
00195   PPCTargetMachine &getPPCTargetMachine() const {
00196     return getTM<PPCTargetMachine>();
00197   }
00198 
00199   const PPCSubtarget &getPPCSubtarget() const {
00200     return *getPPCTargetMachine().getSubtargetImpl();
00201   }
00202 
00203   void addIRPasses() override;
00204   bool addPreISel() override;
00205   bool addILPOpts() override;
00206   bool addInstSelector() override;
00207   void addPreRegAlloc() override;
00208   void addPreSched2() override;
00209   void addPreEmitPass() override;
00210 };
00211 } // namespace
00212 
00213 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
00214   return new PPCPassConfig(this, PM);
00215 }
00216 
00217 void PPCPassConfig::addIRPasses() {
00218   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
00219 
00220   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
00221     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
00222     // and lower a GEP with multiple indices to either arithmetic operations or
00223     // multiple GEPs with single index.
00224     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
00225     // Call EarlyCSE pass to find and remove subexpressions in the lowered
00226     // result.
00227     addPass(createEarlyCSEPass());
00228     // Do loop invariant code motion in case part of the lowered result is
00229     // invariant.
00230     addPass(createLICMPass());
00231   }
00232 
00233   TargetPassConfig::addIRPasses();
00234 }
00235 
00236 bool PPCPassConfig::addPreISel() {
00237   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
00238     addPass(createPPCCTRLoops(getPPCTargetMachine()));
00239 
00240   return false;
00241 }
00242 
00243 bool PPCPassConfig::addILPOpts() {
00244   addPass(&EarlyIfConverterID);
00245   return true;
00246 }
00247 
00248 bool PPCPassConfig::addInstSelector() {
00249   // Install an instruction selector.
00250   addPass(createPPCISelDag(getPPCTargetMachine()));
00251 
00252 #ifndef NDEBUG
00253   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
00254     addPass(createPPCCTRLoopsVerify());
00255 #endif
00256 
00257   addPass(createPPCVSXCopyPass());
00258   return false;
00259 }
00260 
00261 void PPCPassConfig::addPreRegAlloc() {
00262   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
00263   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
00264              &PPCVSXFMAMutateID);
00265 }
00266 
00267 void PPCPassConfig::addPreSched2() {
00268   addPass(createPPCVSXCopyCleanupPass(), false);
00269 
00270   if (getOptLevel() != CodeGenOpt::None)
00271     addPass(&IfConverterID);
00272 }
00273 
00274 void PPCPassConfig::addPreEmitPass() {
00275   if (getOptLevel() != CodeGenOpt::None)
00276     addPass(createPPCEarlyReturnPass(), false);
00277   // Must run branch selection immediately preceding the asm printer.
00278   addPass(createPPCBranchSelectionPass(), false);
00279 }
00280 
00281 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
00282   // Add first the target-independent BasicTTI pass, then our PPC pass. This
00283   // allows the PPC pass to delegate to the target independent layer when
00284   // appropriate.
00285   PM.add(createBasicTargetTransformInfoPass(this));
00286   PM.add(createPPCTargetTransformInfoPass(this));
00287 }