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PPCTargetMachine.cpp
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00001 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // Top-level implementation for the PowerPC target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "PPCTargetMachine.h"
00015 #include "PPC.h"
00016 #include "PPCTargetObjectFile.h"
00017 #include "PPCTargetTransformInfo.h"
00018 #include "llvm/CodeGen/Passes.h"
00019 #include "llvm/IR/Function.h"
00020 #include "llvm/IR/LegacyPassManager.h"
00021 #include "llvm/MC/MCStreamer.h"
00022 #include "llvm/Support/CommandLine.h"
00023 #include "llvm/Support/FormattedStream.h"
00024 #include "llvm/Support/TargetRegistry.h"
00025 #include "llvm/Target/TargetOptions.h"
00026 #include "llvm/Transforms/Scalar.h"
00027 using namespace llvm;
00028 
00029 static cl::
00030 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
00031                         cl::desc("Disable CTR loops for PPC"));
00032 
00033 static cl::
00034 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
00035                             cl::desc("Disable PPC loop preinc prep"));
00036 
00037 static cl::opt<bool>
00038 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
00039   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
00040 
00041 static cl::opt<bool>
00042 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
00043              cl::desc("Enable optimizations on complex GEPs"),
00044              cl::init(true));
00045 
00046 static cl::opt<bool>
00047 EnablePrefetch("enable-ppc-prefetching",
00048                   cl::desc("disable software prefetching on PPC"),
00049                   cl::init(false), cl::Hidden);
00050 
00051 extern "C" void LLVMInitializePowerPCTarget() {
00052   // Register the targets
00053   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
00054   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
00055   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
00056 }
00057 
00058 /// Return the datalayout string of a subtarget.
00059 static std::string getDataLayoutString(const Triple &T) {
00060   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
00061   std::string Ret;
00062 
00063   // Most PPC* platforms are big endian, PPC64LE is little endian.
00064   if (T.getArch() == Triple::ppc64le)
00065     Ret = "e";
00066   else
00067     Ret = "E";
00068 
00069   Ret += DataLayout::getManglingComponent(T);
00070 
00071   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
00072   // pointers.
00073   if (!is64Bit || T.getOS() == Triple::Lv2)
00074     Ret += "-p:32:32";
00075 
00076   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
00077   // documentation are wrong; these are correct (i.e. "what gcc does").
00078   if (is64Bit || !T.isOSDarwin())
00079     Ret += "-i64:64";
00080   else
00081     Ret += "-f64:32:64";
00082 
00083   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
00084   if (is64Bit)
00085     Ret += "-n32:64";
00086   else
00087     Ret += "-n32";
00088 
00089   return Ret;
00090 }
00091 
00092 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
00093   std::string FullFS = FS;
00094   Triple TargetTriple(TT);
00095 
00096   // Make sure 64-bit features are available when CPUname is generic
00097   if (TargetTriple.getArch() == Triple::ppc64 ||
00098       TargetTriple.getArch() == Triple::ppc64le) {
00099     if (!FullFS.empty())
00100       FullFS = "+64bit," + FullFS;
00101     else
00102       FullFS = "+64bit";
00103   }
00104 
00105   if (OL >= CodeGenOpt::Default) {
00106     if (!FullFS.empty())
00107       FullFS = "+crbits," + FullFS;
00108     else
00109       FullFS = "+crbits";
00110   }
00111 
00112   if (OL != CodeGenOpt::None) {
00113      if (!FullFS.empty())
00114       FullFS = "+invariant-function-descriptors," + FullFS;
00115     else
00116       FullFS = "+invariant-function-descriptors";
00117   }
00118 
00119   return FullFS;
00120 }
00121 
00122 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
00123   // If it isn't a Mach-O file then it's going to be a linux ELF
00124   // object file.
00125   if (TT.isOSDarwin())
00126     return make_unique<TargetLoweringObjectFileMachO>();
00127 
00128   return make_unique<PPC64LinuxTargetObjectFile>();
00129 }
00130 
00131 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
00132                                                  const TargetOptions &Options) {
00133   if (Options.MCOptions.getABIName().startswith("elfv1"))
00134     return PPCTargetMachine::PPC_ABI_ELFv1;
00135   else if (Options.MCOptions.getABIName().startswith("elfv2"))
00136     return PPCTargetMachine::PPC_ABI_ELFv2;
00137 
00138   assert(Options.MCOptions.getABIName().empty() &&
00139    "Unknown target-abi option!");
00140 
00141   if (!TT.isMacOSX()) {
00142     switch (TT.getArch()) {
00143     case Triple::ppc64le:
00144       return PPCTargetMachine::PPC_ABI_ELFv2;
00145     case Triple::ppc64:
00146       return PPCTargetMachine::PPC_ABI_ELFv1;
00147     default:
00148       // Fallthrough.
00149       ;
00150     }
00151   }
00152   return PPCTargetMachine::PPC_ABI_UNKNOWN;
00153 }
00154 
00155 // The FeatureString here is a little subtle. We are modifying the feature string
00156 // with what are (currently) non-function specific overrides as it goes into the
00157 // LLVMTargetMachine constructor and then using the stored value in the
00158 // Subtarget constructor below it.
00159 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
00160                                    StringRef FS, const TargetOptions &Options,
00161                                    Reloc::Model RM, CodeModel::Model CM,
00162                                    CodeGenOpt::Level OL)
00163     : LLVMTargetMachine(T, getDataLayoutString(Triple(TT)), TT, CPU,
00164                         computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
00165       TLOF(createTLOF(Triple(getTargetTriple()))),
00166       TargetABI(computeTargetABI(Triple(TT), Options)) {
00167   initAsmInfo();
00168 }
00169 
00170 PPCTargetMachine::~PPCTargetMachine() {}
00171 
00172 void PPC32TargetMachine::anchor() { }
00173 
00174 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
00175                                        StringRef CPU, StringRef FS,
00176                                        const TargetOptions &Options,
00177                                        Reloc::Model RM, CodeModel::Model CM,
00178                                        CodeGenOpt::Level OL)
00179   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
00180 }
00181 
00182 void PPC64TargetMachine::anchor() { }
00183 
00184 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
00185                                        StringRef CPU,  StringRef FS,
00186                                        const TargetOptions &Options,
00187                                        Reloc::Model RM, CodeModel::Model CM,
00188                                        CodeGenOpt::Level OL)
00189   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
00190 }
00191 
00192 const PPCSubtarget *
00193 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
00194   Attribute CPUAttr = F.getFnAttribute("target-cpu");
00195   Attribute FSAttr = F.getFnAttribute("target-features");
00196 
00197   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
00198                         ? CPUAttr.getValueAsString().str()
00199                         : TargetCPU;
00200   std::string FS = !FSAttr.hasAttribute(Attribute::None)
00201                        ? FSAttr.getValueAsString().str()
00202                        : TargetFS;
00203 
00204   auto &I = SubtargetMap[CPU + FS];
00205   if (!I) {
00206     // This needs to be done before we create a new subtarget since any
00207     // creation will depend on the TM and the code generation flags on the
00208     // function that reside in TargetOptions.
00209     resetTargetOptions(F);
00210     I = llvm::make_unique<PPCSubtarget>(
00211         TargetTriple, CPU,
00212         // FIXME: It would be good to have the subtarget additions here
00213         // not necessary. Anything that turns them on/off (overrides) ends
00214         // up being put at the end of the feature string, but the defaults
00215         // shouldn't require adding them. Fixing this means pulling Feature64Bit
00216         // out of most of the target cpus in the .td file and making it set only
00217         // as part of initialization via the TargetTriple.
00218         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
00219   }
00220   return I.get();
00221 }
00222 
00223 //===----------------------------------------------------------------------===//
00224 // Pass Pipeline Configuration
00225 //===----------------------------------------------------------------------===//
00226 
00227 namespace {
00228 /// PPC Code Generator Pass Configuration Options.
00229 class PPCPassConfig : public TargetPassConfig {
00230 public:
00231   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
00232     : TargetPassConfig(TM, PM) {}
00233 
00234   PPCTargetMachine &getPPCTargetMachine() const {
00235     return getTM<PPCTargetMachine>();
00236   }
00237 
00238   void addIRPasses() override;
00239   bool addPreISel() override;
00240   bool addILPOpts() override;
00241   bool addInstSelector() override;
00242   void addPreRegAlloc() override;
00243   void addPreSched2() override;
00244   void addPreEmitPass() override;
00245 };
00246 } // namespace
00247 
00248 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
00249   return new PPCPassConfig(this, PM);
00250 }
00251 
00252 void PPCPassConfig::addIRPasses() {
00253   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
00254 
00255   // For the BG/Q (or if explicitly requested), add explicit data prefetch
00256   // intrinsics.
00257   bool UsePrefetching =
00258     Triple(TM->getTargetTriple()).getVendor() == Triple::BGQ &&           
00259     getOptLevel() != CodeGenOpt::None;
00260   if (EnablePrefetch.getNumOccurrences() > 0)
00261     UsePrefetching = EnablePrefetch;
00262   if (UsePrefetching)
00263     addPass(createPPCLoopDataPrefetchPass());
00264 
00265   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
00266     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
00267     // and lower a GEP with multiple indices to either arithmetic operations or
00268     // multiple GEPs with single index.
00269     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
00270     // Call EarlyCSE pass to find and remove subexpressions in the lowered
00271     // result.
00272     addPass(createEarlyCSEPass());
00273     // Do loop invariant code motion in case part of the lowered result is
00274     // invariant.
00275     addPass(createLICMPass());
00276   }
00277 
00278   TargetPassConfig::addIRPasses();
00279 }
00280 
00281 bool PPCPassConfig::addPreISel() {
00282   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
00283     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
00284 
00285   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
00286     addPass(createPPCCTRLoops(getPPCTargetMachine()));
00287 
00288   return false;
00289 }
00290 
00291 bool PPCPassConfig::addILPOpts() {
00292   addPass(&EarlyIfConverterID);
00293   return true;
00294 }
00295 
00296 bool PPCPassConfig::addInstSelector() {
00297   // Install an instruction selector.
00298   addPass(createPPCISelDag(getPPCTargetMachine()));
00299 
00300 #ifndef NDEBUG
00301   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
00302     addPass(createPPCCTRLoopsVerify());
00303 #endif
00304 
00305   addPass(createPPCVSXCopyPass());
00306   return false;
00307 }
00308 
00309 void PPCPassConfig::addPreRegAlloc() {
00310   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
00311   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
00312              &PPCVSXFMAMutateID);
00313   if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
00314     addPass(createPPCTLSDynamicCallPass());
00315 }
00316 
00317 void PPCPassConfig::addPreSched2() {
00318   if (getOptLevel() != CodeGenOpt::None)
00319     addPass(&IfConverterID);
00320 }
00321 
00322 void PPCPassConfig::addPreEmitPass() {
00323   if (getOptLevel() != CodeGenOpt::None)
00324     addPass(createPPCEarlyReturnPass(), false);
00325   // Must run branch selection immediately preceding the asm printer.
00326   addPass(createPPCBranchSelectionPass(), false);
00327 }
00328 
00329 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
00330   return TargetIRAnalysis(
00331       [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });
00332 }