LLVM  10.0.0svn
NVPTXTargetTransformInfo.h
Go to the documentation of this file.
1 //===-- NVPTXTargetTransformInfo.h - NVPTX specific TTI ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// NVPTX target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
18 
19 #include "NVPTXTargetMachine.h"
24 
25 namespace llvm {
26 
27 class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
29  typedef TargetTransformInfo TTI;
30  friend BaseT;
31 
32  const NVPTXSubtarget *ST;
33  const NVPTXTargetLowering *TLI;
34 
35  const NVPTXSubtarget *getST() const { return ST; };
36  const NVPTXTargetLowering *getTLI() const { return TLI; };
37 
38 public:
39  explicit NVPTXTTIImpl(const NVPTXTargetMachine *TM, const Function &F)
40  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()),
41  TLI(ST->getTargetLowering()) {}
42 
43  bool hasBranchDivergence() { return true; }
44 
45  bool isSourceOfDivergence(const Value *V);
46 
47  unsigned getFlatAddressSpace() const {
49  }
50 
51  // Loads and stores can be vectorized if the alignment is at least as big as
52  // the load/store we want to vectorize.
53  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
54  unsigned Alignment,
55  unsigned AddrSpace) const {
56  return Alignment >= ChainSizeInBytes;
57  }
58  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
59  unsigned Alignment,
60  unsigned AddrSpace) const {
61  return isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment, AddrSpace);
62  }
63 
64  // NVPTX has infinite registers of all kinds, but the actual machine doesn't.
65  // We conservatively return 1 here which is just enough to enable the
66  // vectorizers but disables heuristics based on the number of registers.
67  // FIXME: Return a more reasonable number, while keeping an eye on
68  // LoopVectorizer's unrolling heuristics.
69  unsigned getNumberOfRegisters(bool Vector) const { return 1; }
70 
71  // Only <2 x half> should be vectorized, so always return 32 for the vector
72  // register size.
73  unsigned getRegisterBitWidth(bool Vector) const { return 32; }
74  unsigned getMinVectorRegisterBitWidth() const { return 32; }
75 
76  // We don't want to prevent inlining because of target-cpu and -features
77  // attributes that were added to newer versions of LLVM/Clang: There are
78  // no incompatible functions in PTX, ptxas will throw errors in such cases.
79  bool areInlineCompatible(const Function *Caller,
80  const Function *Callee) const {
81  return true;
82  }
83 
84  // Increase the inlining cost threshold by a factor of 5, reflecting that
85  // calls are particularly expensive in NVPTX.
86  unsigned getInliningThresholdMultiplier() { return 5; }
87 
89  unsigned Opcode, Type *Ty,
95 
98  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) {
99  // Volatile loads/stores are only supported for shared and global address
100  // spaces, or for generic AS that maps to them.
101  if (!(AddrSpace == llvm::ADDRESS_SPACE_GENERIC ||
102  AddrSpace == llvm::ADDRESS_SPACE_GLOBAL ||
103  AddrSpace == llvm::ADDRESS_SPACE_SHARED))
104  return false;
105 
106  switch(I->getOpcode()){
107  default:
108  return false;
109  case Instruction::Load:
110  case Instruction::Store:
111  return true;
112  }
113  }
114 };
115 
116 } // end namespace llvm
117 
118 #endif
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getFlatAddressSpace() const
NVPTXTTIImpl(const NVPTXTargetMachine *TM, const Function &F)
The main scalar evolution driver.
F(f)
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:77
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value *> Args=ArrayRef< const Value *>())
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
bool isSourceOfDivergence(const Value *V)
unsigned getMinVectorRegisterBitWidth() const
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace)
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
OperandValueProperties
Additional properties of an operand&#39;s values.
unsigned getInliningThresholdMultiplier()
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
unsigned getRegisterBitWidth(bool Vector) const
NVPTXTargetMachine.
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:509
unsigned getNumberOfRegisters(bool Vector) const
Parameters that control the generic loop unrolling transformation.
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
#define I(x, y, z)
Definition: MD5.cpp:58
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
LLVM Value Representation.
Definition: Value.h:74
static const Function * getParent(const Value *V)
const DataLayout & getDataLayout() const
OperandValueKind
Additional information about an operand&#39;s possible values.
This pass exposes codegen information to IR-level passes.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
This file describes how to lower LLVM code to machine code.