LLVM  8.0.0svn
NVPTXTargetTransformInfo.h
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1 //===-- NVPTXTargetTransformInfo.h - NVPTX specific TTI ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// NVPTX target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
19 
20 #include "NVPTX.h"
21 #include "NVPTXTargetMachine.h"
25 
26 namespace llvm {
27 
28 class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
30  typedef TargetTransformInfo TTI;
31  friend BaseT;
32 
33  const NVPTXSubtarget *ST;
34  const NVPTXTargetLowering *TLI;
35 
36  const NVPTXSubtarget *getST() const { return ST; };
37  const NVPTXTargetLowering *getTLI() const { return TLI; };
38 
39 public:
40  explicit NVPTXTTIImpl(const NVPTXTargetMachine *TM, const Function &F)
41  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()),
42  TLI(ST->getTargetLowering()) {}
43 
44  bool hasBranchDivergence() { return true; }
45 
46  bool isSourceOfDivergence(const Value *V);
47 
48  unsigned getFlatAddressSpace() const {
50  }
51 
52  // Loads and stores can be vectorized if the alignment is at least as big as
53  // the load/store we want to vectorize.
54  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
55  unsigned Alignment,
56  unsigned AddrSpace) const {
57  return Alignment >= ChainSizeInBytes;
58  }
59  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
60  unsigned Alignment,
61  unsigned AddrSpace) const {
62  return isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment, AddrSpace);
63  }
64 
65  // NVPTX has infinite registers of all kinds, but the actual machine doesn't.
66  // We conservatively return 1 here which is just enough to enable the
67  // vectorizers but disables heuristics based on the number of registers.
68  // FIXME: Return a more reasonable number, while keeping an eye on
69  // LoopVectorizer's unrolling heuristics.
70  unsigned getNumberOfRegisters(bool Vector) const { return 1; }
71 
72  // Only <2 x half> should be vectorized, so always return 32 for the vector
73  // register size.
74  unsigned getRegisterBitWidth(bool Vector) const { return 32; }
75  unsigned getMinVectorRegisterBitWidth() const { return 32; }
76 
77  // We don't want to prevent inlining because of target-cpu and -features
78  // attributes that were added to newer versions of LLVM/Clang: There are
79  // no incompatible functions in PTX, ptxas will throw errors in such cases.
80  bool areInlineCompatible(const Function *Caller,
81  const Function *Callee) const {
82  return true;
83  }
84 
85  // Increase the inlining cost threshold by a factor of 5, reflecting that
86  // calls are particularly expensive in NVPTX.
87  unsigned getInliningThresholdMultiplier() { return 5; }
88 
90  unsigned Opcode, Type *Ty,
96 
99  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) {
100  // Volatile loads/stores are only supported for shared and global address
101  // spaces, or for generic AS that maps to them.
102  if (!(AddrSpace == llvm::ADDRESS_SPACE_GENERIC ||
103  AddrSpace == llvm::ADDRESS_SPACE_GLOBAL ||
104  AddrSpace == llvm::ADDRESS_SPACE_SHARED))
105  return false;
106 
107  switch(I->getOpcode()){
108  default:
109  return false;
110  case Instruction::Load:
111  case Instruction::Store:
112  return true;
113  }
114  }
115 };
116 
117 } // end namespace llvm
118 
119 #endif
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getFlatAddressSpace() const
NVPTXTTIImpl(const NVPTXTargetMachine *TM, const Function &F)
The main scalar evolution driver.
F(f)
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:78
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:126
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value *> Args=ArrayRef< const Value *>())
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
bool isSourceOfDivergence(const Value *V)
unsigned getMinVectorRegisterBitWidth() const
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace)
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
OperandValueProperties
Additional properties of an operand&#39;s values.
unsigned getInliningThresholdMultiplier()
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
unsigned getRegisterBitWidth(bool Vector) const
NVPTXTargetMachine.
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:459
unsigned getNumberOfRegisters(bool Vector) const
Parameters that control the generic loop unrolling transformation.
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
#define I(x, y, z)
Definition: MD5.cpp:58
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
LLVM Value Representation.
Definition: Value.h:73
static const Function * getParent(const Value *V)
const DataLayout & getDataLayout() const
OperandValueKind
Additional information about an operand&#39;s possible values.
This pass exposes codegen information to IR-level passes.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
This file describes how to lower LLVM code to machine code.