15#ifndef LLVM_CODEGEN_LIVESTACKS_H
16#define LLVM_CODEGEN_LIVESTACKS_H
25#include <unordered_map>
33class TargetRegisterClass;
34class TargetRegisterInfo;
44 using SS2IntervalMap = std::unordered_map<int, LiveInterval>;
45 SS2IntervalMap S2IMap;
48 std::map<int, const TargetRegisterClass *> S2RCMap;
64 assert(Slot >= 0 &&
"Spill slot indice must be >= 0");
65 SS2IntervalMap::iterator
I = S2IMap.find(Slot);
66 assert(
I != S2IMap.end() &&
"Interval does not exist for stack slot");
71 assert(Slot >= 0 &&
"Spill slot indice must be >= 0");
72 SS2IntervalMap::const_iterator
I = S2IMap.find(Slot);
73 assert(
I != S2IMap.end() &&
"Interval does not exist for stack slot");
77 bool hasInterval(
int Slot)
const {
return S2IMap.count(Slot); }
80 assert(Slot >= 0 &&
"Spill slot indice must be >= 0");
81 std::map<int, const TargetRegisterClass *>::const_iterator
I =
84 "Register class info does not exist for stack slot");
This header defines various interfaces for pass management in LLVM.
Machine Check Debug Module
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A container for analyses that lazily runs them and caches their results.
Represent the analysis usage information of a pass.
Allocate memory in an ever growing pool, as if by bump-pointer.
LiveInterval - This class represents the liveness of a register, or stack slot.
LiveStacks run(MachineFunction &MF, MachineFunctionAnalysisManager &)
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &AM)
LiveStacksPrinterPass(raw_ostream &OS)
void print(raw_ostream &O, const Module *=nullptr) const override
print - Implement the dump method.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
bool runOnMachineFunction(MachineFunction &) override
runOnMachineFunction - pass entry point
LiveStacksWrapperLegacy()
const LiveStacks & getLS() const
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
SS2IntervalMap::const_iterator const_iterator
LiveInterval & getInterval(int Slot)
bool hasInterval(int Slot) const
unsigned getNumIntervals() const
VNInfo::Allocator & getVNInfoAllocator()
SS2IntervalMap::iterator iterator
LiveInterval & getOrCreateInterval(int Slot, const TargetRegisterClass *RC)
void print(raw_ostream &O, const Module *M=nullptr) const
print - Implement the dump method.
const TargetRegisterClass * getIntervalRegClass(int Slot) const
const_iterator end() const
const LiveInterval & getInterval(int Slot) const
const_iterator begin() const
void init(MachineFunction &MF)
init - analysis entry point
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
A Module instance is used to store all the information related to an LLVM module.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
A set of analyses that are preserved following a run of a transformation pass.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
This is an optimization pass for GlobalISel generic memory operations.
void initializeLiveStacksWrapperLegacyPass(PassRegistry &)
A CRTP mix-in that provides informational APIs needed for analysis passes.
A special type used by analysis passes to provide an address that identifies that particular analysis...
A CRTP mix-in to automatically provide informational APIs needed for passes.