PPCISelLowering.h File Reference

#include "PPCInstrInfo.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Metadata.h"
#include "llvm/IR/Type.h"
#include <optional>
#include <utility>

Go to the source code of this file.

Classes
class	llvm::PPCTargetLowering
struct	llvm::PPCTargetLowering::CallFlags
	Structure that collects some common arguments that get passed around between the functions for call lowering. More...

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::PPCISD
namespace	llvm::PPC
	Define some predicates that are used for node matching.

Enumerations
enum	llvm::PPCISD::NodeType : unsigned {   llvm::PPCISD::FIRST_NUMBER = ISD::BUILTIN_OP_END , llvm::PPCISD::FSEL , llvm::PPCISD::XSMAXC , llvm::PPCISD::XSMINC ,   llvm::PPCISD::FCFID , llvm::PPCISD::FCFIDU , llvm::PPCISD::FCFIDS , llvm::PPCISD::FCFIDUS ,   llvm::PPCISD::FCTIDZ , llvm::PPCISD::FCTIWZ , llvm::PPCISD::FCTIDUZ , llvm::PPCISD::FCTIWUZ ,   llvm::PPCISD::VEXTS , llvm::PPCISD::FRE , llvm::PPCISD::FRSQRTE , llvm::PPCISD::FTSQRT ,   llvm::PPCISD::FSQRT , llvm::PPCISD::VPERM , llvm::PPCISD::XXSPLT , llvm::PPCISD::XXSPLTI_SP_TO_DP ,   llvm::PPCISD::XXSPLTI32DX , llvm::PPCISD::VECINSERT , llvm::PPCISD::VECSHL , llvm::PPCISD::XXPERMDI ,   llvm::PPCISD::XXPERM , llvm::PPCISD::CMPB , llvm::PPCISD::Hi , llvm::PPCISD::Lo ,   llvm::PPCISD::DYNALLOC , llvm::PPCISD::DYNAREAOFFSET , llvm::PPCISD::PROBED_ALLOCA , llvm::PPCISD::GlobalBaseReg ,   llvm::PPCISD::SRL , llvm::PPCISD::SRA , llvm::PPCISD::SHL , llvm::PPCISD::FNMSUB ,   llvm::PPCISD::EXTSWSLI , llvm::PPCISD::SRA_ADDZE , llvm::PPCISD::CALL , llvm::PPCISD::CALL_NOP ,   llvm::PPCISD::CALL_NOTOC , llvm::PPCISD::MTCTR , llvm::PPCISD::BCTRL , llvm::PPCISD::BCTRL_LOAD_TOC ,   llvm::PPCISD::CALL_RM , llvm::PPCISD::CALL_NOP_RM , llvm::PPCISD::CALL_NOTOC_RM , llvm::PPCISD::BCTRL_RM ,   llvm::PPCISD::BCTRL_LOAD_TOC_RM , llvm::PPCISD::RET_GLUE , llvm::PPCISD::MFOCRF , llvm::PPCISD::MFVSR ,   llvm::PPCISD::MTVSRA , llvm::PPCISD::MTVSRZ , llvm::PPCISD::BUILD_FP128 , llvm::PPCISD::BUILD_SPE64 ,   llvm::PPCISD::EXTRACT_SPE , llvm::PPCISD::SINT_VEC_TO_FP , llvm::PPCISD::UINT_VEC_TO_FP , llvm::PPCISD::SCALAR_TO_VECTOR_PERMUTED ,   llvm::PPCISD::ANDI_rec_1_EQ_BIT , llvm::PPCISD::ANDI_rec_1_GT_BIT , llvm::PPCISD::READ_TIME_BASE , llvm::PPCISD::EH_SJLJ_SETJMP ,   llvm::PPCISD::EH_SJLJ_LONGJMP , llvm::PPCISD::VCMP , llvm::PPCISD::VCMP_rec , llvm::PPCISD::COND_BRANCH ,   llvm::PPCISD::BDNZ , llvm::PPCISD::BDZ , llvm::PPCISD::FADDRTZ , llvm::PPCISD::MFFS ,   llvm::PPCISD::TC_RETURN , llvm::PPCISD::CR6SET , llvm::PPCISD::CR6UNSET , llvm::PPCISD::PPC32_GOT ,   llvm::PPCISD::PPC32_PICGOT , llvm::PPCISD::ADDIS_GOT_TPREL_HA , llvm::PPCISD::LD_GOT_TPREL_L , llvm::PPCISD::ADD_TLS ,   llvm::PPCISD::ADDIS_TLSGD_HA , llvm::PPCISD::ADDI_TLSGD_L , llvm::PPCISD::GET_TLS_ADDR , llvm::PPCISD::GET_TPOINTER ,   llvm::PPCISD::ADDI_TLSGD_L_ADDR , llvm::PPCISD::TLSGD_AIX , llvm::PPCISD::GET_TLS_MOD_AIX , llvm::PPCISD::TLSLD_AIX ,   llvm::PPCISD::ADDIS_TLSLD_HA , llvm::PPCISD::ADDI_TLSLD_L , llvm::PPCISD::GET_TLSLD_ADDR , llvm::PPCISD::ADDI_TLSLD_L_ADDR ,   llvm::PPCISD::ADDIS_DTPREL_HA , llvm::PPCISD::ADDI_DTPREL_L , llvm::PPCISD::PADDI_DTPREL , llvm::PPCISD::VADD_SPLAT ,   llvm::PPCISD::SC , llvm::PPCISD::CLRBHRB , llvm::PPCISD::MFBHRBE , llvm::PPCISD::RFEBB ,   llvm::PPCISD::XXSWAPD , llvm::PPCISD::SWAP_NO_CHAIN , llvm::PPCISD::FP_EXTEND_HALF , llvm::PPCISD::MAT_PCREL_ADDR ,   llvm::PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR , llvm::PPCISD::TLS_LOCAL_EXEC_MAT_ADDR , llvm::PPCISD::ACC_BUILD , llvm::PPCISD::PAIR_BUILD ,   llvm::PPCISD::EXTRACT_VSX_REG , llvm::PPCISD::XXMFACC , llvm::PPCISD::FIRST_STRICTFP_OPCODE , llvm::PPCISD::STRICT_FCTIDZ = FIRST_STRICTFP_OPCODE ,   llvm::PPCISD::STRICT_FCTIWZ , llvm::PPCISD::STRICT_FCTIDUZ , llvm::PPCISD::STRICT_FCTIWUZ , llvm::PPCISD::STRICT_FCFID ,   llvm::PPCISD::STRICT_FCFIDU , llvm::PPCISD::STRICT_FCFIDS , llvm::PPCISD::STRICT_FCFIDUS , llvm::PPCISD::STRICT_FADDRTZ ,   llvm::PPCISD::LAST_STRICTFP_OPCODE = STRICT_FADDRTZ , llvm::PPCISD::SETBC , llvm::PPCISD::SETBCR , llvm::PPCISD::FIRST_MEMORY_OPCODE ,   llvm::PPCISD::STBRX = FIRST_MEMORY_OPCODE , llvm::PPCISD::LBRX , llvm::PPCISD::STFIWX , llvm::PPCISD::LFIWAX ,   llvm::PPCISD::LFIWZX , llvm::PPCISD::LXSIZX , llvm::PPCISD::STXSIX , llvm::PPCISD::LXVD2X ,   llvm::PPCISD::LXVRZX , llvm::PPCISD::LOAD_VEC_BE , llvm::PPCISD::LD_VSX_LH , llvm::PPCISD::LD_SPLAT ,   llvm::PPCISD::ZEXT_LD_SPLAT , llvm::PPCISD::SEXT_LD_SPLAT , llvm::PPCISD::STXVD2X , llvm::PPCISD::STORE_VEC_BE ,   llvm::PPCISD::ST_VSR_SCAL_INT , llvm::PPCISD::ATOMIC_CMP_SWAP_8 , llvm::PPCISD::ATOMIC_CMP_SWAP_16 , llvm::PPCISD::STORE_COND ,   llvm::PPCISD::TOC_ENTRY , llvm::PPCISD::LAST_MEMORY_OPCODE = TOC_ENTRY }
enum	llvm::PPC::MemOpFlags {   llvm::PPC::MOF_None = 0 , llvm::PPC::MOF_SExt = 1 , llvm::PPC::MOF_ZExt = 1 << 1 , llvm::PPC::MOF_NoExt = 1 << 2 ,   llvm::PPC::MOF_NotAddNorCst = 1 << 5 , llvm::PPC::MOF_RPlusSImm16 = 1 << 6 , llvm::PPC::MOF_RPlusLo = 1 << 7 , llvm::PPC::MOF_RPlusSImm16Mult4 = 1 << 8 ,   llvm::PPC::MOF_RPlusSImm16Mult16 = 1 << 9 , llvm::PPC::MOF_RPlusSImm34 = 1 << 10 , llvm::PPC::MOF_RPlusR = 1 << 11 , llvm::PPC::MOF_PCRel = 1 << 12 ,   llvm::PPC::MOF_AddrIsSImm32 = 1 << 13 , llvm::PPC::MOF_SubWordInt = 1 << 15 , llvm::PPC::MOF_WordInt = 1 << 16 , llvm::PPC::MOF_DoubleWordInt = 1 << 17 ,   llvm::PPC::MOF_ScalarFloat = 1 << 18 , llvm::PPC::MOF_Vector = 1 << 19 , llvm::PPC::MOF_Vector256 = 1 << 20 , llvm::PPC::MOF_SubtargetBeforeP9 = 1 << 22 ,   llvm::PPC::MOF_SubtargetP9 = 1 << 23 , llvm::PPC::MOF_SubtargetP10 = 1 << 24 , llvm::PPC::MOF_SubtargetSPE = 1 << 25 }
enum	llvm::PPC::AddrMode {   llvm::PPC::AM_None , llvm::PPC::AM_DForm , llvm::PPC::AM_DSForm , llvm::PPC::AM_DQForm ,   llvm::PPC::AM_PrefixDForm , llvm::PPC::AM_XForm , llvm::PPC::AM_PCRel }

Functions
bool	llvm::PPC::isVPKUHUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
	isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
bool	llvm::PPC::isVPKUWUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
	isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
bool	llvm::PPC::isVPKUDUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
	isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
bool	llvm::PPC::isVMRGLShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
	isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
bool	llvm::PPC::isVMRGHShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
	isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
bool	llvm::PPC::isVMRGEOShuffleMask (ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
	isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instruction
bool	llvm::PPC::isXXSLDWIShuffleMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
	isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction.
bool	llvm::PPC::isXXBRHShuffleMask (ShuffleVectorSDNode *N)
	isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.
bool	llvm::PPC::isXXBRWShuffleMask (ShuffleVectorSDNode *N)
	isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.
bool	llvm::PPC::isXXBRDShuffleMask (ShuffleVectorSDNode *N)
	isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.
bool	llvm::PPC::isXXBRQShuffleMask (ShuffleVectorSDNode *N)
	isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.
bool	llvm::PPC::isXXPERMDIShuffleMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
	isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.
int	llvm::PPC::isVSLDOIShuffleMask (SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
	isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.
bool	llvm::PPC::isSplatShuffleMask (ShuffleVectorSDNode *N, unsigned EltSize)
	isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW.
bool	llvm::PPC::isXXINSERTWMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
	isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction introduced in ISA 3.0.
unsigned	llvm::PPC::getSplatIdxForPPCMnemonics (SDNode *N, unsigned EltSize, SelectionDAG &DAG)
	getSplatIdxForPPCMnemonics - Return the splat index as a value that is appropriate for PPC mnemonics (which have a big endian bias - namely elements are counted from the left of the vector register).
SDValue	llvm::PPC::get_VSPLTI_elt (SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
	get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted.
FastISel *	llvm::PPC::createFastISel (FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
bool	llvm::isIntS16Immediate (SDNode *N, int16_t &Imm)
	isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate, and if the value can be accurately represented as a sign extension from a 16-bit value.
bool	llvm::isIntS16Immediate (SDValue Op, int16_t &Imm)
bool	llvm::isIntS34Immediate (SDNode *N, int64_t &Imm)
	isIntS34Immediate - This method tests if value of node given can be accurately represented as a sign extension from a 34-bit value.
bool	llvm::isIntS34Immediate (SDValue Op, int64_t &Imm)
bool	llvm::convertToNonDenormSingle (APInt &ArgAPInt)
bool	llvm::convertToNonDenormSingle (APFloat &ArgAPFloat)
bool	llvm::checkConvertToNonDenormSingle (APFloat &ArgAPFloat)