RISCVInterleavedAccess.cpp File Reference

#include "RISCV.h"
#include "RISCVISelLowering.h"
#include "RISCVSubtarget.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/PatternMatch.h"

Go to the source code of this file.

Functions
static bool	isMultipleOfN (const Value *V, const DataLayout &DL, unsigned N)
static bool	getMemOperands (unsigned Factor, VectorType *VTy, Type *XLenTy, Instruction *I, Value *&Ptr, Value *&Mask, Value *&VL, Align &Alignment)
	Do the common operand retrieval and validition required by the routines below.

Variables
static const Intrinsic::ID	FixedVlsegIntrIds []
static const Intrinsic::ID	FixedVlssegIntrIds []
static const Intrinsic::ID	ScalableVlsegIntrIds []
static const Intrinsic::ID	FixedVssegIntrIds []
static const Intrinsic::ID	FixedVsssegIntrIds []
static const Intrinsic::ID	ScalableVssegIntrIds []

Function Documentation

getMemOperands()

bool getMemOperands ( unsigned Factor, VectorType * VTy, Type * XLenTy, Instruction * I, Value *& Ptr, Value *& Mask, Value *& VL, Align & Alignment )

static

Do the common operand retrieval and validition required by the routines below.

Definition at line 119 of file RISCVInterleavedAccess.cpp.

References assert(), llvm::cast(), DL, llvm::dyn_cast(), llvm::Constant::getAllOnesValue(), llvm::Value::getType(), I, II, llvm::isa(), isMultipleOfN(), llvm_unreachable, and Ptr.

Referenced by llvm::RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(), llvm::RISCVTargetLowering::lowerInterleavedLoad(), llvm::RISCVTargetLowering::lowerInterleavedStore(), and llvm::RISCVTargetLowering::lowerInterleaveIntrinsicToStore().

isMultipleOfN()

bool isMultipleOfN ( const Value * V, const DataLayout & DL, unsigned N )

static

Definition at line 96 of file RISCVInterleavedAccess.cpp.

References assert(), llvm::CallingConv::C, llvm::computeKnownBits(), llvm::KnownBits::countMinTrailingZeros(), DL, llvm::isPowerOf2_32(), llvm::Log2_32(), llvm::PatternMatch::m_CombineOr(), llvm::PatternMatch::m_ConstantInt(), llvm::PatternMatch::m_NUWMul(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::match(), and N.

Referenced by getMemOperands().

Variable Documentation

FixedVlsegIntrIds

const Intrinsic::ID FixedVlsegIntrIds[]

static

Initial value:

= {
    Intrinsic::riscv_seg2_load_mask, Intrinsic::riscv_seg3_load_mask,
    Intrinsic::riscv_seg4_load_mask, Intrinsic::riscv_seg5_load_mask,
    Intrinsic::riscv_seg6_load_mask, Intrinsic::riscv_seg7_load_mask,
    Intrinsic::riscv_seg8_load_mask}

Definition at line 60 of file RISCVInterleavedAccess.cpp.

Referenced by llvm::RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(), and llvm::RISCVTargetLowering::lowerInterleavedLoad().

FixedVlssegIntrIds

const Intrinsic::ID FixedVlssegIntrIds[]

static

Initial value:

= {
    Intrinsic::riscv_sseg2_load_mask, Intrinsic::riscv_sseg3_load_mask,
    Intrinsic::riscv_sseg4_load_mask, Intrinsic::riscv_sseg5_load_mask,
    Intrinsic::riscv_sseg6_load_mask, Intrinsic::riscv_sseg7_load_mask,
    Intrinsic::riscv_sseg8_load_mask}

Definition at line 66 of file RISCVInterleavedAccess.cpp.

Referenced by llvm::RISCVTargetLowering::lowerInterleavedLoad().

FixedVssegIntrIds

const Intrinsic::ID FixedVssegIntrIds[]

static

Initial value:

= {
    Intrinsic::riscv_seg2_store_mask, Intrinsic::riscv_seg3_store_mask,
    Intrinsic::riscv_seg4_store_mask, Intrinsic::riscv_seg5_store_mask,
    Intrinsic::riscv_seg6_store_mask, Intrinsic::riscv_seg7_store_mask,
    Intrinsic::riscv_seg8_store_mask}

Definition at line 78 of file RISCVInterleavedAccess.cpp.

Referenced by llvm::RISCVTargetLowering::lowerInterleavedStore(), and llvm::RISCVTargetLowering::lowerInterleaveIntrinsicToStore().

FixedVsssegIntrIds

const Intrinsic::ID FixedVsssegIntrIds[]

static

Initial value:

= {
    Intrinsic::riscv_sseg2_store_mask, Intrinsic::riscv_sseg3_store_mask,
    Intrinsic::riscv_sseg4_store_mask, Intrinsic::riscv_sseg5_store_mask,
    Intrinsic::riscv_sseg6_store_mask, Intrinsic::riscv_sseg7_store_mask,
    Intrinsic::riscv_sseg8_store_mask}

Definition at line 84 of file RISCVInterleavedAccess.cpp.

Referenced by llvm::RISCVTargetLowering::lowerInterleavedStore().

ScalableVlsegIntrIds

const Intrinsic::ID ScalableVlsegIntrIds[]

static

Initial value:

= {
    Intrinsic::riscv_vlseg2_mask, Intrinsic::riscv_vlseg3_mask,
    Intrinsic::riscv_vlseg4_mask, Intrinsic::riscv_vlseg5_mask,
    Intrinsic::riscv_vlseg6_mask, Intrinsic::riscv_vlseg7_mask,
    Intrinsic::riscv_vlseg8_mask}

Definition at line 72 of file RISCVInterleavedAccess.cpp.

Referenced by llvm::RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad().

ScalableVssegIntrIds

const Intrinsic::ID ScalableVssegIntrIds[]

static

Initial value:

= {
    Intrinsic::riscv_vsseg2_mask, Intrinsic::riscv_vsseg3_mask,
    Intrinsic::riscv_vsseg4_mask, Intrinsic::riscv_vsseg5_mask,
    Intrinsic::riscv_vsseg6_mask, Intrinsic::riscv_vsseg7_mask,
    Intrinsic::riscv_vsseg8_mask}

Definition at line 90 of file RISCVInterleavedAccess.cpp.

Referenced by llvm::RISCVTargetLowering::lowerInterleaveIntrinsicToStore().