25#define DEBUG_TYPE "ve-disassembler"
36 virtual ~VEDisassembler() =
default;
47 return new VEDisassembler(STI, Ctx);
57 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
58 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
59 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
60 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
61 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
62 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
63 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
64 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
65 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,
70 VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13,
71 VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20,
72 VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27,
73 VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34,
74 VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41,
75 VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48,
76 VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55,
77 VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62,
81 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,
82 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13,
83 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,
84 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
85 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
86 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
87 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
88 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
89 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
94 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
95 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
96 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
99 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7,
100 VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15,
101 VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23,
102 VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31,
103 VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39,
104 VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47,
105 VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55,
106 VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63};
109 VE::VM0, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5,
110 VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11,
111 VE::VM12, VE::VM13, VE::VM14, VE::VM15};
114 VE::VMP3, VE::VMP4, VE::VMP5,
118 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
119 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
120 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3,
121 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
122 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3,
123 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7,
124 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11,
125 VE::PMC12, VE::PMC13, VE::PMC14};
160 if (RegNo % 2 || RegNo > 63)
170 unsigned Reg = VE::NoRegister;
194 if (RegNo % 2 || RegNo > 15)
207 if (Reg == VE::NoRegister)
265#include "VEGenDisassemblerTables.inc"
270 bool IsLittleEndian) {
272 if (Bytes.
size() < 8) {
277 Insn = IsLittleEndian
295 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
303 Result = decodeInstruction(DecoderTableVE64, Instr,
Insn, Address,
this, STI);
318 unsigned sy = fieldFromInstruction(insn, 40, 7);
319 bool cy = fieldFromInstruction(insn, 47, 1);
320 unsigned sz = fieldFromInstruction(insn, 32, 7);
321 bool cz = fieldFromInstruction(insn, 39, 1);
322 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));
351 unsigned sz = fieldFromInstruction(insn, 32, 7);
352 bool cz = fieldFromInstruction(insn, 39, 1);
353 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));
374 unsigned sx = fieldFromInstruction(insn, 48, 7);
378 status = DecodeSX(
MI, sx,
Address, Decoder);
388 status = DecodeSX(
MI, sx,
Address, Decoder);
398 unsigned sx = fieldFromInstruction(insn, 48, 7);
402 status = DecodeSX(
MI, sx,
Address, Decoder);
412 status = DecodeSX(
MI, sx,
Address, Decoder);
469 unsigned sx = fieldFromInstruction(insn, 48, 7);
470 bool cy = fieldFromInstruction(insn, 47, 1);
471 unsigned sy = fieldFromInstruction(insn, 40, 7);
475 status = DecodeSX(
MI, sx,
Address, Decoder);
485 if (cy && !isImmOnly) {
486 status = DecodeSX(
MI, sy,
Address, Decoder);
497 status = DecodeSX(
MI, sx,
Address, Decoder);
535 uint64_t tgt = SignExtend64<7>(insn);
542 uint64_t tgt = SignExtend64<32>(insn);
549#define BCm_kind(NAME) \
563#define BCRm_kind(NAME) \
573 switch (
MI.getOpcode()) {
601 unsigned cf = fieldFromInstruction(insn, 48, 4);
602 bool cy = fieldFromInstruction(insn, 47, 1);
603 unsigned sy = fieldFromInstruction(insn, 40, 7);
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
static bool isLoad(int Opcode)
#define LLVM_EXTERNAL_VISIBILITY
static DecodeStatus DecodeBranchCondition(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeV64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder, bool isImmOnly, bool isUImm, DecodeFunc DecodeSX)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRDOperand(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCASI32(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus readInstruction64(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn, bool IsLittleEndian)
Read four bytes from the ArrayRef and return 32 bit word.
static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchConditionAlways(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static const unsigned I32RegDecoderTable[]
DecodeStatus(* DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static const unsigned F128RegDecoderTable[]
static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static bool isIntegerBCKind(MCInst &MI)
static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static const unsigned V64RegDecoderTable[]
static const unsigned I64RegDecoderTable[]
static DecodeStatus DecodeTS1AMI32(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static const unsigned F32RegDecoderTable[]
static DecodeStatus DecodeASX(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static const unsigned VM512RegDecoderTable[]
static DecodeStatus DecodeVM512RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder, bool isLoad, DecodeFunc DecodeSX)
static DecodeStatus DecodeVMRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder, bool isLoad, DecodeFunc DecodeSX)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEDisassembler()
static DecodeStatus DecodeCASI64(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCCOperand(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static const unsigned VMRegDecoderTable[]
static MCDisassembler * createVEDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeSIMM32(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)
static const unsigned MiscRegDecoderTable[]
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
static MCOperand createReg(MCRegister Reg)
static MCOperand createImm(int64_t Val)
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheVETarget()
static VECC::CondCode VEValToCondCode(unsigned Val, bool IsInteger)
static VERD::RoundingMode VEValToRD(unsigned Val)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.