LLVM 20.0.0git
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#include "MCTargetDesc/XtensaMCTargetDesc.h"
#include "TargetInfo/XtensaTargetInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDecoderOps.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Endian.h"
#include "XtensaGenDisassemblerTables.inc"
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "Xtensa-disassembler" |
Typedefs | |
using | DecodeStatus = MCDisassembler::DecodeStatus |
Functions | |
static MCDisassembler * | createXtensaDisassembler (const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) |
LLVM_EXTERNAL_VISIBILITY void | LLVMInitializeXtensaDisassembler () |
static DecodeStatus | DecodeARRegisterClass (MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeSRRegisterClass (MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) |
static bool | tryAddingSymbolicOperand (int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t InstSize, MCInst &MI, const void *Decoder) |
static DecodeStatus | decodeCallOperand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeJumpOperand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeBranchOperand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeL32ROperand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeImm8Operand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeImm8_sh8Operand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeImm12Operand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeUimm4Operand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeUimm5Operand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeImm1_16Operand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeShimm1_31Operand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeB4constOperand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeB4constuOperand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeMem8Operand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeMem16Operand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | decodeMem32Operand (MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) |
static DecodeStatus | readInstruction24 (ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsLittleEndian) |
Read three bytes from the ArrayRef and return 24 bit data. | |
Variables | |
static const unsigned | ARDecoderTable [] |
static const unsigned | SRDecoderTable [] = {Xtensa::SAR, 3} |
static int64_t | TableB4const [16] |
static int64_t | TableB4constu [16] |
#define DEBUG_TYPE "Xtensa-disassembler" |
Definition at line 28 of file XtensaDisassembler.cpp.
Definition at line 30 of file XtensaDisassembler.cpp.
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Definition at line 51 of file XtensaDisassembler.cpp.
Referenced by LLVMInitializeXtensaDisassembler().
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Definition at line 67 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), ARDecoderTable, llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by decodeMem16Operand(), decodeMem32Operand(), and decodeMem8Operand().
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Definition at line 203 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), llvm::MCDisassembler::Success, and TableB4const.
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Definition at line 213 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), llvm::MCDisassembler::Success, and TableB4constu.
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Definition at line 120 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), llvm::MCInst::getOpcode(), llvm::MCDisassembler::Success, and tryAddingSymbolicOperand().
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Definition at line 106 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 165 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 186 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 157 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 150 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 113 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 141 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 230 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), DecodeARRegisterClass(), and llvm::MCDisassembler::Success.
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Definition at line 238 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), DecodeARRegisterClass(), and llvm::MCDisassembler::Success.
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Definition at line 222 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), DecodeARRegisterClass(), and llvm::MCDisassembler::Success.
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Definition at line 193 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 80 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, SRDecoderTable, and llvm::MCDisassembler::Success.
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Definition at line 172 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 179 of file XtensaDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaDisassembler | ( | ) |
Definition at line 57 of file XtensaDisassembler.cpp.
References createXtensaDisassembler(), llvm::getTheXtensaTarget(), and llvm::TargetRegistry::RegisterMCDisassembler().
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Read three bytes from the ArrayRef and return 24 bit data.
Definition at line 247 of file XtensaDisassembler.cpp.
References llvm::MCDisassembler::Fail, Insn, llvm::report_fatal_error(), llvm::ArrayRef< T >::size(), Size, and llvm::MCDisassembler::Success.
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Definition at line 97 of file XtensaDisassembler.cpp.
References isBranch(), MI, llvm::Offset, and llvm::MCDisassembler::tryAddingSymbolicOperand().
Referenced by decodeBranchOperand().
Definition at line 62 of file XtensaDisassembler.cpp.
Referenced by DecodeARRegisterClass().
Definition at line 78 of file XtensaDisassembler.cpp.
Referenced by DecodeSRRegisterClass().
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Definition at line 201 of file XtensaDisassembler.cpp.
Referenced by decodeB4constOperand().
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Definition at line 211 of file XtensaDisassembler.cpp.
Referenced by decodeB4constuOperand().