28#define DEBUG_TYPE "Xtensa-disassembler"
41 bool hasDensity()
const {
54 return new XtensaDisassembler(STI, Ctx,
true);
63 Xtensa::A0, Xtensa::SP, Xtensa::A2, Xtensa::A3, Xtensa::A4, Xtensa::A5,
64 Xtensa::A6, Xtensa::A7, Xtensa::A8, Xtensa::A9, Xtensa::A10, Xtensa::A11,
65 Xtensa::A12, Xtensa::A13, Xtensa::A14, Xtensa::A15};
69 const void *Decoder) {
82 const void *Decoder) {
100 const void *Decoder) {
107 int64_t Address,
const void *Decoder) {
108 assert(isUInt<18>(Imm) &&
"Invalid immediate");
114 int64_t Address,
const void *Decoder) {
115 assert(isUInt<18>(Imm) &&
"Invalid immediate");
121 int64_t Address,
const void *Decoder) {
127 assert(isUInt<12>(Imm) &&
"Invalid immediate");
129 Address, 0, 3, Inst, Decoder))
133 assert(isUInt<8>(Imm) &&
"Invalid immediate");
135 Address, 0, 3, Inst, Decoder))
142 int64_t Address,
const void *Decoder) {
144 assert(isUInt<16>(Imm) &&
"Invalid immediate");
146 SignExtend64<17>((Imm << 2) + 0x40000 + (Address & 0x3))));
151 int64_t Address,
const void *Decoder) {
152 assert(isUInt<8>(Imm) &&
"Invalid immediate");
159 const void *Decoder) {
160 assert(isUInt<8>(Imm) &&
"Invalid immediate");
166 int64_t Address,
const void *Decoder) {
167 assert(isUInt<12>(Imm) &&
"Invalid immediate");
173 int64_t Address,
const void *Decoder) {
174 assert(isUInt<4>(Imm) &&
"Invalid immediate");
180 int64_t Address,
const void *Decoder) {
181 assert(isUInt<5>(Imm) &&
"Invalid immediate");
187 int64_t Address,
const void *Decoder) {
188 assert(isUInt<4>(Imm) &&
"Invalid immediate");
195 const void *Decoder) {
196 assert(isUInt<5>(Imm) &&
"Invalid immediate");
202 8, 10, 12, 16, 32, 64, 128, 256};
204 int64_t Address,
const void *Decoder) {
205 assert(isUInt<4>(Imm) &&
"Invalid immediate");
212 8, 10, 12, 16, 32, 64, 128, 256};
215 const void *Decoder) {
216 assert(isUInt<4>(Imm) &&
"Invalid immediate");
223 int64_t Address,
const void *Decoder) {
224 assert(isUInt<12>(Imm) &&
"Invalid immediate");
231 int64_t Address,
const void *Decoder) {
232 assert(isUInt<12>(Imm) &&
"Invalid immediate");
239 int64_t Address,
const void *Decoder) {
240 assert(isUInt<12>(Imm) &&
"Invalid immediate");
249 bool IsLittleEndian) {
251 if (Bytes.
size() < 3) {
256 if (!IsLittleEndian) {
259 Insn = (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
266#include "XtensaGenDisassemblerTables.inc"
278 LLVM_DEBUG(
dbgs() <<
"Trying Xtensa 24-bit instruction table :\n");
279 Result = decodeInstruction(DecoderTable24,
MI,
Insn, Address,
this, STI);
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
static bool isBranch(unsigned Opcode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static DecodeStatus decodeMem16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static int64_t TableB4const[16]
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaDisassembler()
static DecodeStatus decodeImm8_sh8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus decodeImm8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus decodeL32ROperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus decodeImm12Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t InstSize, MCInst &MI, const void *Decoder)
static DecodeStatus decodeMem32Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus decodeUimm4Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static const unsigned SRDecoderTable[]
static DecodeStatus decodeImm1_16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus decodeMem8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus readInstruction24(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsLittleEndian)
Read three bytes from the ArrayRef and return 24 bit data.
static DecodeStatus decodeUimm5Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static MCDisassembler * createXtensaDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeCallOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus decodeB4constuOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static const unsigned ARDecoderTable[]
static DecodeStatus decodeB4constOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static int64_t TableB4constu[16]
static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus decodeJumpOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus decodeBranchOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
Target - Wrapper for Target specific information.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Target & getTheXtensaTarget()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.