LLVM 20.0.0git
|
#include "llvm/MCA/Stages/DispatchStage.h"
Public Member Functions | |
DispatchStage (const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI, unsigned MaxDispatchWidth, RetireControlUnit &R, RegisterFile &F) | |
bool | isAvailable (const InstRef &IR) const override |
Returns true if it can execute IR during this cycle. | |
bool | hasWorkToComplete () const override |
Returns true if some instructions are still executing this stage. | |
Error | cycleStart () override |
Called once at the start of each cycle. | |
Error | execute (InstRef &IR) override |
The primary action that this stage performs on instruction IR. | |
void | dump () const |
Public Member Functions inherited from llvm::mca::Stage | |
Stage ()=default | |
virtual | ~Stage () |
virtual bool | isAvailable (const InstRef &IR) const |
Returns true if it can execute IR during this cycle. | |
virtual bool | hasWorkToComplete () const =0 |
Returns true if some instructions are still executing this stage. | |
virtual Error | cycleStart () |
Called once at the start of each cycle. | |
virtual Error | cycleResume () |
Called after the pipeline is resumed from pausing state. | |
virtual Error | cycleEnd () |
Called once at the end of each cycle. | |
virtual Error | execute (InstRef &IR)=0 |
The primary action that this stage performs on instruction IR. | |
void | setNextInSequence (Stage *NextStage) |
bool | checkNextStage (const InstRef &IR) const |
Error | moveToTheNextStage (InstRef &IR) |
Called when an instruction is ready to move the next pipeline stage. | |
void | addListener (HWEventListener *Listener) |
Add a listener to receive callbacks during the execution of this stage. | |
template<typename EventT > | |
void | notifyEvent (const EventT &Event) const |
Notify listeners of a particular hardware event. | |
Additional Inherited Members | |
Protected Member Functions inherited from llvm::mca::Stage | |
const std::set< HWEventListener * > & | getListeners () const |
Definition at line 49 of file DispatchStage.h.
llvm::mca::DispatchStage::DispatchStage | ( | const MCSubtargetInfo & | Subtarget, |
const MCRegisterInfo & | MRI, | ||
unsigned | MaxDispatchWidth, | ||
RetireControlUnit & | R, | ||
RegisterFile & | F | ||
) |
Definition at line 28 of file DispatchStage.cpp.
References llvm::MCSubtargetInfo::getSchedModel(), and llvm::MCSchedModel::IssueWidth.
|
overridevirtual |
Called once at the start of each cycle.
This can be used as a setup phase to prepare for the executions during the cycle.
Reimplemented from llvm::mca::Stage.
Definition at line 134 of file DispatchStage.cpp.
References assert(), and llvm::mca::RegisterFile::getNumRegisterFiles().
void llvm::mca::DispatchStage::dump | ( | ) | const |
Definition at line 180 of file DispatchStage.cpp.
References llvm::mca::RegisterFile::dump(), and llvm::mca::RetireControlUnit::dump().
The primary action that this stage performs on instruction IR.
Implements llvm::mca::Stage.
Definition at line 174 of file DispatchStage.cpp.
|
inlineoverridevirtual |
Returns true if some instructions are still executing this stage.
Implements llvm::mca::Stage.
Definition at line 76 of file DispatchStage.h.
Returns true if it can execute IR during this cycle.
Reimplemented from llvm::mca::Stage.
Definition at line 154 of file DispatchStage.cpp.
References llvm::mca::InstructionBase::getBeginGroup(), llvm::mca::InstructionBase::getNumMicroOps(), and IR.