18#ifndef LLVM_MCA_STAGES_DISPATCHSTAGE_H
19#define LLVM_MCA_STAGES_DISPATCHSTAGE_H
50 unsigned DispatchWidth;
51 unsigned AvailableEntries;
60 bool canDispatch(
const InstRef &
IR)
const;
63 void notifyInstructionDispatched(
const InstRef &
IR,
unsigned const MachineRegisterInfo * MRI
Legalize the Machine IR a function s Machine IR
This file defines abstractions used by the Pipeline to model register reads, register writes and inst...
This file defines a register mapping file class.
This file simulates the hardware responsible for retiring instructions.
This file defines a stage.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Lightweight error class with error context and mandatory checking.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasWorkToComplete() const override
Returns true if some instructions are still executing this stage.
Error cycleStart() override
Called once at the start of each cycle.
bool isAvailable(const InstRef &IR) const override
Returns true if it can execute IR during this cycle.
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
An InstRef contains both a SourceMgr index and Instruction pair.
Manages hardware register files, and tracks register definitions for register renaming purposes.
This is an optimization pass for GlobalISel generic memory operations.
This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO back...