23#define DEBUG_TYPE "llvm-mca"
32 : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
33 CarryOver(0U), STI(Subtarget), RCU(R), PRF(
F) {
38void DispatchStage::notifyInstructionDispatched(
const InstRef &
IR,
40 unsigned UOps)
const {
42 notifyEvent<HWInstructionEvent>(
46bool DispatchStage::checkPRF(
const InstRef &
IR)
const {
48 for (
const WriteState &RegDef :
IR.getInstruction()->getDefs())
51 const unsigned RegisterMask = PRF.
isAvailable(RegDefs);
54 notifyEvent<HWStallEvent>(
62bool DispatchStage::checkRCU(
const InstRef &
IR)
const {
63 const unsigned NumMicroOps =
IR.getInstruction()->getNumMicroOps();
66 notifyEvent<HWStallEvent>(
71bool DispatchStage::canDispatch(
const InstRef &
IR)
const {
72 bool CanDispatch = checkRCU(
IR);
73 CanDispatch &= checkPRF(
IR);
78Error DispatchStage::dispatch(InstRef
IR) {
79 assert(!CarryOver &&
"Cannot dispatch another instruction!");
80 Instruction &IS = *
IR.getInstruction();
81 const unsigned NumMicroOps = IS.getNumMicroOps();
82 if (NumMicroOps > DispatchWidth) {
83 assert(AvailableEntries == DispatchWidth);
85 CarryOver = NumMicroOps - DispatchWidth;
88 assert(AvailableEntries >= NumMicroOps);
89 AvailableEntries -= NumMicroOps;
97 if (IS.isOptimizableMove())
110 if (!IS.isEliminated()) {
111 for (ReadState &RS : IS.getUses())
119 for (WriteState &WS : IS.getDefs())
125 IS.dispatch(RCUTokenID);
129 notifyInstructionDispatched(
IR, RegisterFiles,
130 std::min(DispatchWidth, NumMicroOps));
138 AvailableEntries = DispatchWidth;
142 AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
143 unsigned DispatchedOpcodes = DispatchWidth - AvailableEntries;
144 CarryOver -= DispatchedOpcodes;
145 assert(CarriedOver &&
"Invalid dispatched instruction");
148 notifyInstructionDispatched(CarriedOver, RegisterFiles, DispatchedOpcodes);
156 if (!AvailableEntries)
161 unsigned Required = std::min(NumMicroOps, DispatchWidth);
162 if (Required > AvailableEntries)
165 if (Inst.
getBeginGroup() && AvailableEntries != DispatchWidth)
171 return canDispatch(
IR);
175 assert(canDispatch(
IR) &&
"Cannot dispatch another instruction!");
unsigned const MachineRegisterInfo * MRI
This file models the dispatch component of an instruction pipeline.
This file defines the main interface for hardware event listeners.
Legalize the Machine IR a function s Machine IR
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A scheduler for Processor Resource Units and Processor Resource Groups.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Subclass of Error for the sole purpose of identifying the success path in the type system.
Lightweight error class with error context and mandatory checking.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
reference emplace_back(ArgTypes &&... Args)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Error cycleStart() override
Called once at the start of each cycle.
bool isAvailable(const InstRef &IR) const override
Returns true if it can execute IR during this cycle.
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI, unsigned MaxDispatchWidth, RetireControlUnit &R, RegisterFile &F)
An InstRef contains both a SourceMgr index and Instruction pair.
unsigned getNumMicroOps() const
bool getBeginGroup() const
An instruction propagated through the simulated instruction pipeline.
Manages hardware register files, and tracks register definitions for register renaming purposes.
void addRegisterWrite(WriteRef Write, MutableArrayRef< unsigned > UsedPhysRegs)
unsigned isAvailable(ArrayRef< MCPhysReg > Regs) const
unsigned getNumRegisterFiles() const
bool tryEliminateMoveOrSwap(MutableArrayRef< WriteState > Writes, MutableArrayRef< ReadState > Reads)
void addRegisterRead(ReadState &RS, const MCSubtargetInfo &STI) const
Error moveToTheNextStage(InstRef &IR)
Called when an instruction is ready to move the next pipeline stage.
bool checkNextStage(const InstRef &IR) const
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO back...
bool isAvailable(unsigned Quantity=1) const
unsigned dispatch(const InstRef &IS)