LLVM 20.0.0git
NVPTXInstrInfo.h
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1//===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the NVPTX implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
14#define LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
15
16#include "NVPTX.h"
17#include "NVPTXRegisterInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#include "NVPTXGenInstrInfo.inc"
22
23namespace llvm {
24
27 virtual void anchor();
28public:
29 explicit NVPTXInstrInfo();
30
31 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
32
33 /* The following virtual functions are used in register allocation.
34 * They are not implemented because the existing interface and the logic
35 * at the caller side do not work for the elementized vector load and store.
36 *
37 * virtual Register isLoadFromStackSlot(const MachineInstr *MI,
38 * int &FrameIndex) const;
39 * virtual Register isStoreToStackSlot(const MachineInstr *MI,
40 * int &FrameIndex) const;
41 * virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
42 * MachineBasicBlock::iterator MBBI,
43 * unsigned SrcReg, bool isKill, int FrameIndex,
44 * const TargetRegisterClass *RC,
45 * Register VReg) const;
46 * virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
47 * MachineBasicBlock::iterator MBBI,
48 * unsigned DestReg, int FrameIndex,
49 * const TargetRegisterClass *RC,
50 * const TargetRegisterInfo *TRI,
51 * Register VReg) const;
52 */
53
55 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
56 bool KillSrc) const override;
57
58 // Branch analysis.
62 bool AllowModify) const override;
64 int *BytesRemoved = nullptr) const override;
67 const DebugLoc &DL,
68 int *BytesAdded = nullptr) const override;
69};
70
71} // namespace llvm
72
73#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define I(x, y, z)
Definition: MD5.cpp:58
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
const NVPTXRegisterInfo & getRegisterInfo() const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18